On Sun, Nov 24, 2024 at 08:03:53AM +0300, Michael Tokarev wrote:
> 23.11.2024 20:01, Stafford Horne wrote:
> > On Sat, Nov 23, 2024 at 03:12:12PM +0300, Michael Tokarev wrote:
> > > On 23.11.2024 13:38, Stafford Horne wrote:
> > > > This series has 2 fixes for OpenRISC that came in over that past f
On Sat, Nov 23, 2024 at 11:18:53PM -0600, Rob Landley wrote:
...
> I'm attempting to regression test as many targets as I can to get consistent
> basic behavior out of:
>
> https://landley.net/bin/mkroot/0.8.11/
>
> I'm trying to get a new release out with the 6.12 kernel which is why I'm
> rev
On 11/23/24 02:28, Stafford Horne wrote:
Just a guess, but given the alignment change, I suspect it's barfing on the
statically linked initramfs? That seems the most likely step to go off the
rails given the failing patch is a symbol alignment change in the flattened
device tree plumbing, and I t
23.11.2024 20:01, Stafford Horne wrote:
On Sat, Nov 23, 2024 at 03:12:12PM +0300, Michael Tokarev wrote:
On 23.11.2024 13:38, Stafford Horne wrote:
This series has 2 fixes for OpenRISC that came in over that past few months.
Ahmad Fatoum (1):
hw/openrisc/openrisc_sim: keep serial@9000
Thanks. This patch at least guarantees normal read/write access to
addresses with r/w flags, although there is still a risk of
misidentifying accessible regions within continuous address spaces.
Actually, initially I did write a patch with a modified page size as
an argument, but I soon found that
Hi,
On 11/21/24 13:42, Erwin Jansen wrote:
Would a good next step be to work out some more details in a document
that outlines what process we are using, what we are planning to do and
include a set of suggestions as a starting point to see if we can
upstream some of the changes to the larger
Hi all,
very recently, I've been working on enabling clang builds on Windows
[1]. As part of it, the major blocking point is that currently, clang
does not support gcc_attribute on Windows.
The change proposed [2] was to use the compiler option [3]
-mno-ms-bitfields, which enables the same beh
On 11/23/24 11:11, Stafford Horne wrote:
On Sat, Nov 23, 2024 at 07:39:57AM -0600, Richard Henderson wrote:
On 11/23/24 04:38, Stafford Horne wrote:
+or1k_timer->ttcr = or1k_timer->ttcr_offset +
+(now - or1k_timer->clk_offset + TIMER_PERIOD - 1) / TIMER_PERIOD;
Better using DIV_RO
On Sat, Nov 23, 2024 at 09:07:05AM -0600, Richard Henderson wrote:
> From: J. Neuschäfer
>
> This aligns with strace, and is very useful when tracing multi-threaded
> programs. The result is the same in single-threaded programs.
>
> Signed-off-by: J. Neuschäfer
> Message-Id: 20241024-strace-v1-1-
Currently, the v1-patch is not yet capable of achieving the desired effect.
It still requires passing the number of variable arguments to the helper_print()
function:
static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
{
TCGv src1;
decode_save_opc(ctx, 0);
For example:
static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
{
TCGv src1;
decode_save_opc(ctx, 0);
src1 = get_address(ctx, a->rs1, 0);
gen_helper_print("src1 %x\n", src1);
...
return true;
}
When the TCG executes instruc
Hi all,
Recently, I have been working on functional simulation and verification of
an extended complex instruction set for an AI chip based on the RISC-V
architecture using QEMU.
Given the complexity of some instructions, I attempted to introduce a set of
helper functions that can print certain i
Signed-off-by: Chao Liu
---
target/riscv/helper.h| 13
target/riscv/op_helper.c | 46
2 files changed, 59 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 451261ce5a..667da16988 100644
--- a/target/riscv/help
On Sat, Nov 23, 2024 at 07:39:57AM -0600, Richard Henderson wrote:
> On 11/23/24 04:38, Stafford Horne wrote:
> > +or1k_timer->ttcr = or1k_timer->ttcr_offset +
> > +(now - or1k_timer->clk_offset + TIMER_PERIOD - 1) / TIMER_PERIOD;
>
> Better using DIV_ROUND_UP.
Sure, I can change it t
On Sat, Nov 23, 2024 at 03:12:12PM +0300, Michael Tokarev wrote:
> On 23.11.2024 13:38, Stafford Horne wrote:
> > This series has 2 fixes for OpenRISC that came in over that past few months.
> >
> > Ahmad Fatoum (1):
> >hw/openrisc/openrisc_sim: keep serial@9000 as default
> >
> > Joel Ho
For reviewers: note also that I have signed a tag with my GPG key
fingerprint 635020F967A7716479EF49E0175C464E541B6D47 that has had
this new uid added to it.
See https://github.com/quic/qemu/tree/bcain-email-addr-update-oss.qualcomm.com
and
https://github.com/quic/qemu/releases/tag/bcain-email-ad
From: Brian Cain
Also: add mapping for "quic_bc...@quicinc.com" which was ~briefly
used for some replies to mailing list traffic.
Signed-off-by: Brian Cain
Signed-off-by: Brian Cain
---
.mailmap| 2 ++
MAINTAINERS | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/.mail
Thomas Huth writes:
> On 21/11/2024 18.31, Alex Bennée wrote:
>> Peter Maydell writes:
>>
>>> On Thu, 21 Nov 2024 at 16:58, Alex Bennée wrote:
This is a mostly testing focused set of patches but a few bug fixes as
well. I plan to send the PR in on Monday. I can drop any patches
The following changes since commit 34754a3a627e1937be7f3daaa0c5e73d91c7d9b5:
Update version for v9.2.0-rc1 release (2024-11-20 18:27:48 +)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-lu-20241122
for you to fetch changes up to d95fd9838b540e69da9
From: J. Neuschäfer
This aligns with strace, and is very useful when tracing multi-threaded
programs. The result is the same in single-threaded programs.
Signed-off-by: J. Neuschäfer
Message-Id: 20241024-strace-v1-1-56c416143...@gmx.net
[rth: Use TaskState.ts_tid via get_task_state()]
Signed-of
From: Ilya Leoshkevich
print_mmap() assumes that mmap() receives arguments via memory if
mmap2() is present. s390x (as opposed to s390) does not fit this
pattern: it does not have mmap2(), but mmap() still receives arguments
via memory.
Fix by sharing the detection logic between syscall.c and st
On 11/22/24 16:50, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
docs/system/arm/fby35.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
diff --git a/docs/system/arm/fby35.rst b/docs/system/arm/fby35.rst
index 742b887d44c..bf6da6b
On 11/22/24 16:50, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
docs/system/arm/emulation.rst | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Richard Henderson
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index 50d0250b1eb..47f5123a31d 100
On 11/22/24 16:50, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
target/arm/tcg/cpu32.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Oops. :-)
Reviewed-by: Richard Henderson
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index 20c2737f17b..4e589b74
On 11/22/24 16:50, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
docs/system/arm/emulation.rst | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Richard Henderson
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index af613b9c8b8..50d0250b1eb 10
On 11/22/24 16:50, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
docs/system/arm/emulation.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index 2956c22a1b7
On 11/22/24 16:50, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
docs/system/arm/emulation.rst | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson
r~
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index a2a
On 11/23/24 04:38, Stafford Horne wrote:
+or1k_timer->ttcr = or1k_timer->ttcr_offset +
+(now - or1k_timer->clk_offset + TIMER_PERIOD - 1) / TIMER_PERIOD;
Better using DIV_ROUND_UP.
+/* Zero the count by applying a negative offset to the counter */
+or1k_timer->ttcr
On 23.11.2024 13:38, Stafford Horne wrote:
This series has 2 fixes for OpenRISC that came in over that past few months.
Ahmad Fatoum (1):
hw/openrisc/openrisc_sim: keep serial@9000 as default
Joel Holdsworth (1):
hw/openrisc: Fixed undercounting of TTCR in continuous mode
Is there a
From: Joel Holdsworth
In the existing design, TTCR is prone to undercounting when running in
continuous mode. This manifests as a timer interrupt appearing to
trigger a few cycles prior to the deadline set in SPR_TTMR_TP.
When the timer triggers, the virtual time delta in nanoseconds between
the
This series has 2 fixes for OpenRISC that came in over that past few months.
Ahmad Fatoum (1):
hw/openrisc/openrisc_sim: keep serial@9000 as default
Joel Holdsworth (1):
hw/openrisc: Fixed undercounting of TTCR in continuous mode
hw/openrisc/cputimer.c | 26 +++--
From: Ahmad Fatoum
We used to only have a single UART on the platform and it was located at
address 0x9000. When the number of UARTs was increased to 4, the
first UART remained at it's location, but instead of being the first one
to be registered, it became the last.
This caused QEMU to pick
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: 2024年11月22日 15:02
> To: Wafer ; m...@redhat.com;
> jasow...@redhat.com; gr...@kaod.org
> Cc: epere...@redhat.com; qemu-devel@nongnu.org; Angus Chen
>
> Subject: Re: [PATCH] hw/virtio: Fix getting the correct ring number on load
On Fri, Nov 22, 2024 at 06:54:21PM -0600, Rob Landley wrote:
> On 11/22/24 10:35, Stafford Horne wrote:
> > > I just regression tested linux-6.12 against qemu-9.2.0-rc1 and I'm still
> > > getting no output from or1k, with the current image or the old or1k
> > > release
> > > image that worked und
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