[PATCH v2 0/2] chardev/char-mux: tweak mux bitset operations

Patchset tweaks bitset operations by changing a constant to unsigned long, introduces a static compile check and simplifies bitset operations. v1..v2: Rebase on latest master, incorporate review tags. Roman Penyaev (2): chardev/char-mux: shift unsigned long to avoid 32-bit overflow chardev/c

[PATCH v2 1/2] chardev/char-mux: shift unsigned long to avoid 32-bit overflow

Allthough the size of MAX_MUX is equal to 4 and likely will never change, this patch changes type of constant to unsigned long to be on the safe side. Also add a static compile check that MAX_MUX never bigger than `sizeof(d->mux_bitset)`. Signed-off-by: Roman Penyaev Reviewed-by: "Marc-André Lur

[PATCH v2 2/2] chardev/char-mux: make boolean bit check instead of find_next_bit()

This patch simplifies (and makes less confusing) bit checks by replacing `find_next_bit()` calls with boolean AND operation. Resolves: Coverity CID 1563776 Signed-off-by: Roman Penyaev Reviewed-by: "Marc-André Lureau" Cc: Peter Maydell Reviewed-by: Clément Mathieu--Drif Cc: qemu-devel@nongnu.o

[PATCH v4 3/6] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled

Svukte extension add HUKTE bit, bit[24] in hstatus CSR. The written value will be masked when the svukte extension is not enabled. When hstatus[HUKTE] bit is set, HLV/HLVX/HSV work in the U-mode should do svukte check. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu Revie

[PATCH v4 0/6] Introduce svukte ISA extension

The Svukte ISA extension has been approved for fast-track development. https://lf-riscv.atlassian.net/browse/RVS-2977 And there are Linux patches for the Svukte that are under review. https://lore.kernel.org/kvm/20240920-dev-maxh-svukte-rebase-v1-0-7864a88a6...@sifive.com/T/#mf70fcb22cd2987ad268c0

[PATCH v4 1/6] target/riscv: Add svukte extension capability variable

Refer to the draft of svukte extension from: https://github.com/riscv/riscv-isa-manual/pull/1564 Svukte provides a means to make user-mode accesses to supervisor memory raise page faults in constant time, mitigating attacks that attempt to discover the supervisor software's address-space layout.

[PATCH v4 4/6] target/riscv: Check memory access to meet svukte rule

Follow the Svukte spec, do the memory access address checking 1. Include instruction fetches or explicit memory accesses 2. System run in effective privilege U or VU 3. Check senvcfg[UKTE] being set, or hstatus[HUKTE] being set if instruction is HLV, HLVX, HSV and execute from U mode to VU mode 4.

[RFC PATCH v6 0/2] Support RISC-V CSR read/write in Qtest environment

These patches add functionality for unit testing RISC-V-specific registers. The first patch adds a Qtest backend, and the second implements a simple test. --- v7: - Fix build errors, add Reviewed-by, Acked-by. --- Ivan Klokov (2): target/riscv: Add RISC-V CSR qtest support tests/qtest: QTe

[PATCH v4 6/6] target/riscv: Check svukte is not enabled in RV32

Based on the spec, svukte depends on SV39, so it should not be enabled in RV32. Signed-off-by: Fea.Wang --- target/riscv/tcg/tcg-cpu.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index c62c221696..4273f1f472 100644 --- a/target

[PATCH v4 2/6] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled

Svukte extension add UKTE bit, bit[8] in senvcfg CSR. The bit will be supported when the svukte extension is enabled. When senvcfg[UKTE] bit is set, the memory access from U-mode should do the svukte check only except HLV/HLVX/HSV H-mode instructions which depend on hstatus[HUKTE]. Signed-off-by:

[PATCH] hw/i386/amd_iommu: Allow migration

Add migration support for AMD IOMMU model by saving necessary AMDVIState parameters for MMIO registers, device table, command buffer, and event buffers. Signed-off-by: Suravee Suthikulpanit --- hw/i386/amd_iommu.c | 36 +++- 1 file changed, 35 insertions(+), 1 del

[PATCH v4 5/6] target/riscv: Expose svukte ISA extension

Add "svukte" in the ISA string when svukte extension is enabled. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f219f

Re: [PATCH v3 5/5] target/riscv: Expose svukte ISA extension

OK, I will add a new commit for checking the extension in RV32. Thank you. Sincerely, Fea On Tue, Nov 19, 2024 at 11:34 AM Alistair Francis wrote: > On Tue, Nov 12, 2024 at 7:14 PM Fea.Wang wrote: > > > > Add "svukte" in the ISA string when svukte extension is enabled. > > > > Signed-off-by: F

Re: [PATCH v3 4/5] target/riscv: Check memory access to meet svukte rule

Thanks for the advice. I will fix them in the next patch version. Sincerely, Fea On Tue, Nov 19, 2024 at 11:33 AM Alistair Francis wrote: > On Tue, Nov 12, 2024 at 7:13 PM Fea.Wang wrote: > > > > Follow the Svukte spec, do the memory access address checking > > > > 1. Include instruction fetch

[RFC PATCH v7 1/2] target/riscv: Add RISC-V CSR qtest support

The RISC-V architecture supports the creation of custom CSR-mapped devices. It would be convenient to test them in the same way as MMIO-mapped devices. To do this, a new call has been added to read/write CSR registers. Signed-off-by: Ivan Klokov Acked-by: Fabiano Rosas --- hw/riscv/riscv_hart.c

[PULL 3/5] hw/core/machine-smp: Initialize caches_bitmap before reading

From: Zhao Liu The caches_bitmap is defined in machine_parse_smp_cache(), but it was not initialized. Initialize caches_bitmap by clearing all its bits to zero. Resolves: Coverity CID 1565389 Fixes: 4e88e7e3403d ("qapi/qom: Define cache enumeration and properties for machine") Reported-by: Pet

[RFC PATCH v7 2/2] tests/qtest: QTest example for RISC-V CSR register

Added demo for reading CSR register from qtest environment. Signed-off-by: Ivan Klokov Reviewed-by: Fabiano Rosas --- tests/qtest/meson.build | 2 +- tests/qtest/riscv-csr-test.c | 56 2 files changed, 57 insertions(+), 1 deletion(-) create mode 10064

[PULL 0/5] More changes for QEMU 9.2 rc

The following changes since commit e6459afb1ff4d86b361b14f4a2fc43f0d2b4d679: Merge tag 'pull-target-arm-20241119' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-11-19 14:23:34 +) are available in the Git repository at: https://gitlab.com/bonzini/qem

[PULL 2/5] hvf: remove unused but set variable

From: Pierrick Bouvier fixes associated warning when building on MacOS. Signed-off-by: Pierrick Bouvier Link: https://lore.kernel.org/r/20241023182922.1040964-1-pierrick.bouv...@linaro.org Signed-off-by: Paolo Bonzini --- target/i386/hvf/x86_task.c | 10 +- 1 file changed, 5 insertio

[PULL 5/5] scsi: fix allocation for s390x loadparm

Coverity reports a possible buffer overrun due to a non-NUL-terminated string in scsi_property_set_loadparm(). While things are not so easy, because qdev_prop_sanitize_s390x_loadparm is designed to operate on a buffer that is not NUL-terminated, in this case the string *does* have to be NUL-termin

[PULL 1/5] hw/i386/pc: Remove vmport value assertion

From: Kamil Szczęk There is no need for this assertion here, as we only use vmport value for equality/inequality checks. This was originally prompted by the following Coverity report: >>> CID 1559533: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "pcms->vmport >= 0" is always true r

[PATCH 06/15] tests/functional: remove obsolete reference to avocado bug

Historical bugs in avocado related to zstd support are not relevant to the code now that it uses QEMU's native test harness. Signed-off-by: Daniel P. Berrangé --- tests/functional/qemu_test/tuxruntest.py | 1 - 1 file changed, 1 deletion(-) diff --git a/tests/functional/qemu_test/tuxruntest.py

[PATCH v4] hw/riscv: Add Microblaze V generic board

Add a basic board with interrupt controller (intc), timer, serial (uartlite), small memory called LMB@0 (128kB) and DDR@0x8000 (configured via command line eg. -m 2g). This is basic configuration which matches HW generated out of AMD Vivado (design tools). But initial configuration is going bey

Re: [PATCH] scsi: fix allocation for s390x loadparm

On 19/11/2024 22.31, Paolo Bonzini wrote: Coverity reports a possible buffer overrun due to a non-NUL-terminated string in scsi_property_set_loadparm(). While things are not so easy, because qdev_prop_sanitize_s390x_loadparm is designed to operate on a buffer that is not NUL-terminated, in this

[PULL 1/1] docs: aspeed: Reorganize the "Boot options" section

Add subsubsections for possible boot methods and introduce a new section on eMMC boot support for the ast2600-evb and rainier-emmc machines, boot partitions assumptions and limitations. Acked-by: Philippe Mathieu-Daudé Reviewed-by: Jan Luebbe Reviewed-by: Andrew Jeffery Signed-off-by: Cédric Le

Re: [PATCH 2/7] docs/devel: add git-publish for patch submitting

On 11/19/24 01:12, Daniel P. Berrangé wrote: On Tue, Nov 19, 2024 at 09:41:40AM +0100, Marcin Juszkiewicz wrote: W dniu 18.11.2024 o 18:23, Pierrick Bouvier pisze: Signed-off-by: Pierrick Bouvier --- docs/devel/submitting-a-patch.rst | 14 ++ 1 file changed, 14 insertions(+)

Re: [PATCH 2/7] docs/devel: add git-publish for patch submitting

On 11/19/24 00:41, Marcin Juszkiewicz wrote: W dniu 18.11.2024 o 18:23, Pierrick Bouvier pisze: Signed-off-by: Pierrick Bouvier --- docs/devel/submitting-a-patch.rst | 14 ++ 1 file changed, 14 insertions(+) diff --git a/docs/devel/submitting-a-patch.rst b/docs/devel/submitti

Re: [PATCH v5 18/20] intel_iommu: Introduce a property x-flts for scalable modern mode

ok, feel free to add my RB if this is the only change Thanks cmd On 19/11/2024 10:25, Duan, Zhenzhong wrote: Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe. Clear, will use "x-flts is only availabl

Re: [PATCH v5 15/20] tests/acpi: q35: allow DMAR acpi table changes

Hi, @Michael, are this patch and patch 17/20 ok for you? Thanks, cmd On 11/11/2024 09:34, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > Signed-off-by: Zhenzhong Duan

Re: [PATCH for-10.0 v2 0/8] riscv: AIA userspace irqchip_split support

On Wed, Nov 20, 2024 at 5:20 AM Daniel Henrique Barboza wrote: > > Hi, > > This second version was rebased with 'master'. Alistair's acks were > included. > > No other changes were made. All patches acked/reviewed. > > Changes from v1: > - rebased with master @ af4c4fd128 > - v1 link: > https://l

[PATCH 14/15] tests/functional: remove time.sleep usage from tuxrun tests

The tuxrun tests send a series of strings to the guest to login and then run commands. Since we have been unable to match on console output that isn't followed by a newline, the test used many time.sleep() statements to pretend to synchronize with the guest. This has proved to be unreliable for th

[PULL 08/15] arm/ptw: Make get_S1prot accept decoded AP

From: Pavel Skripkin AP in armv7 short descriptor mode has 3 bits and also domain, which makes it incompatible with other arm schemas. To make it possible to share get_S1prot between armv8, armv7 long format, armv7 short format and armv6 it's easier to make caller decode AP. Signed-off-by: Pave

Re: [PATCH v5 1/9] target/riscv: fix henvcfg potentially containing stale bits

On Tue, Nov 19, 2024 at 9:27 PM Clément Léger wrote: > > > > On 19/11/2024 05:16, Alistair Francis wrote: > > On Thu, Nov 14, 2024 at 7:14 PM Clément Léger wrote: > >> > >> With the current implementation, if we had the current scenario: > >> - set bit x in menvcfg > >> - set bit x in henvcfg > >

Re: [PATCH v8 2/5] target/riscv: Handle Smrnmi interrupt and exception

On Mon, Nov 18, 2024 at 11:13 AM Alistair Francis wrote: > On Mon, Oct 21, 2024 at 1:06 PM wrote: > > > > From: Tommy Wu > > > > Because the RNMI interrupt trap handler address is implementation > defined. > > We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the > property > >

[PULL 11/15] hw/intc/arm_gicv3: Use bitops.h uint32_t bit array functions

Now we have official uint32_t bit array functions in bitops.h, use them instead of the hand-rolled local versions. We retain gic_bmp_replace_bit() because bitops doesn't provide that specific functionality. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20241108135

Re: [PATCH V3 11/16] migration: cpr-transfer mode

On Tue, Nov 19, 2024 at 03:32:55PM -0500, Steven Sistare wrote: > This begs the question, should we allow channels to be specified in hmp > migrate > commands and for -incoming, in a very simple way? Like with a prefix naming > the channel. And eliminate the -cpr-uri argument. Examples: > > (qe

Re: [PATCH 13/15] tests/functional: rewrite console handling to be bytewise

On 11/19/24 19:54, Daniel P. Berrangé wrote: +if success is None or success in msg: As an optimization, you could use msg.endswith(success) and msg.endswith(failure), which would avoid the most blatant cases of O(n^2) behavior. More important, I think "if success is None" should not be

[PATCH for-10.0 v2 4/8] target/riscv/kvm: consider irqchip_split() in aia_create()

Before adding support to kernel-irqchip=split when using KVM AIA we need to change how we create the in-kernel AIA device. In the use case we have so far, i.e. in-kernel irqchip without split mode, both the s-mode APLIC and IMSIC controllers are provided by the irqchip. In irqchip_split() mode we'

[PULL 15/15] trace: Don't include trace-root.h in control.c or control-target.c

The trace-root.h file has the definitions of trace events for the top-level trace-events file (i.e. for those events which are used in source files in the root of the source tree). There's no particular need for trace/control.c or trace/control-target.c to include this. Signed-off-by: Peter Maydel

Re: [PATCH] scsi: fix allocation for s390x loadparm

On 11/19/24 4:31 PM, Paolo Bonzini wrote: Coverity reports a possible buffer overrun due to a non-NUL-terminated string in scsi_property_set_loadparm(). While things are not so easy, because qdev_prop_sanitize_s390x_loadparm is designed to operate on a buffer that is not NUL-terminated, in thi

Re: [PATCH 3/5] qdev: Make device_set_realized() always safe in tests

On Tue, Nov 19, 2024 at 09:46:35AM +, Daniel P. Berrangé wrote: > On Mon, Nov 18, 2024 at 05:13:28PM -0500, Peter Xu wrote: > > Currently, a device can be realized even before machine is created, but > > only in one of QEMU's qtest, test-global-qdev-props.c. > > > > Right now, the test_static_

[PULL 14/15] target/arm/hvf: Add trace.h header

The documentation for trace events says that every subdirectory which has trace events should have a trace.h header, whose only content is an include of the trace/trace-.h file. When we added the trace events in target/arm/hvf/ we forgot to create this file and instead hvf.c directly includes trac

[PULL 01/15] hw/timer/exynos4210_mct: fix possible int overflow

From: Dmitry Frolov The product "icnto * s->tcntb" may overflow uint32_t. Found by Linux Verification Center (linuxtesting.org) with SVACE. Signed-off-by: Dmitry Frolov Message-id: 20241106083801.219578-2-fro...@swemel.ru Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/timer/

[PATCH] Added support for WACOM 2.x/ArtZ/Digitizer II compatibility. It does require the driver (easily available via many of the classic macos archives), but it allows a simple way to have an absolut

From: Patrick Eads init Promising polling initiated and data moving cursor now Reverted delete of dev handler for wacom tablet got the y-axis! getting closer more progress. it appears to not quite be WACOM II/IV, but x-axis is controlled by the first 2-3 bytes really? 12-bits is the key? o

Re: [PATCH 09/15] tests/functional: put QEMUMachine logs in testcase log directory

Daniel P. Berrangé writes: > We are not passing the 'log_dir' parameter to QEMUMachine, so the > QEMU stdout/err logs are being placed in a temp directory and thus > deleted after execution. This makes them inaccessible as gitlab > CI artifacts. > > Pass the testcase log directory path into QEMUM

Re: [PATCH V3 11/16] migration: cpr-transfer mode

On 11/19/2024 4:48 PM, Peter Xu wrote: On Tue, Nov 19, 2024 at 04:41:07PM -0500, Steven Sistare wrote: On 11/19/2024 4:29 PM, Peter Xu wrote: On Tue, Nov 19, 2024 at 04:03:08PM -0500, Steven Sistare wrote: On 11/19/2024 3:51 PM, Peter Xu wrote: On Tue, Nov 19, 2024 at 03:32:55PM -0500, Steven

Re: [PATCH V3 11/16] migration: cpr-transfer mode

On Tue, Nov 19, 2024 at 04:41:07PM -0500, Steven Sistare wrote: > On 11/19/2024 4:29 PM, Peter Xu wrote: > > On Tue, Nov 19, 2024 at 04:03:08PM -0500, Steven Sistare wrote: > > > On 11/19/2024 3:51 PM, Peter Xu wrote: > > > > On Tue, Nov 19, 2024 at 03:32:55PM -0500, Steven Sistare wrote: > > > > >

[PATCH for-10.0 v2 2/8] hw/riscv/virt.c: reduce virt_use_kvm_aia() usage

In create_fdt_sockets() we have the following pattern: if (kvm_enabled() && virt_use_kvm_aia(s)) { (... do stuff ...) } else { (... do other stuff ...) } if (kvm_enabled() && virt_use_kvm_aia(s)) { (... do more stuff ...) } else { (... do more ot

Re: [PATCH 5/5] qom: Make container_get() strict to always walk or return container

On Tue, Nov 19, 2024 at 09:30:09PM +0100, Paolo Bonzini wrote: > > > > Do we have known places that we care a lot on object[_class]_dynamic_cast() > > performance? > > The easiest way to check is probably to print the type of every successful > object_dynamic_cast and object_class_dynamic_cast. I

Re: [PATCH V3 11/16] migration: cpr-transfer mode

On 11/19/2024 4:29 PM, Peter Xu wrote: On Tue, Nov 19, 2024 at 04:03:08PM -0500, Steven Sistare wrote: On 11/19/2024 3:51 PM, Peter Xu wrote: On Tue, Nov 19, 2024 at 03:32:55PM -0500, Steven Sistare wrote: This begs the question, should we allow channels to be specified in hmp migrate commands

[PATCH] linux-user: Fix strace output for s390x mmap()

print_mmap() assumes that mmap() receives arguments via memory if mmap2() is present. s390x (as opposed to s390) does not fit this pattern: it does not have mmap2(), but mmap() still receives arguments via memory. Fix by special-casing s390x. Cc: qemu-sta...@nongnu.org Fixes: d971040c2d16 ("linux

[PATCH] scsi: fix allocation for s390x loadparm

Coverity reports a possible buffer overrun due to a non-NUL-terminated string in scsi_property_set_loadparm(). While things are not so easy, because qdev_prop_sanitize_s390x_loadparm is designed to operate on a buffer that is not NUL-terminated, in this case the string *does* have to be NUL-termin

Re: [PATCH v7 00/12] Use Intel DSA accelerator to offload zero page checking in multifd live migration.

Yichen Wang writes: > v7 > * Rebase on top of f0a5a31c33a8109061c2493e475c8a2f4d022432; > * Fix a bug that will crash QEMU when DSA initialization failed; > * Use a more generalized accel-path to support other accelerators; > * Remove multifd-packet-size in the parameter list; > > v6 > * Rebase o

Re: [PATCH V3 11/16] migration: cpr-transfer mode

On Tue, Nov 19, 2024 at 04:03:08PM -0500, Steven Sistare wrote: > On 11/19/2024 3:51 PM, Peter Xu wrote: > > On Tue, Nov 19, 2024 at 03:32:55PM -0500, Steven Sistare wrote: > > > This begs the question, should we allow channels to be specified in hmp > > > migrate > > > commands and for -incoming,

Re: [PATCH V3 11/16] migration: cpr-transfer mode

On 11/19/2024 3:51 PM, Peter Xu wrote: On Tue, Nov 19, 2024 at 03:32:55PM -0500, Steven Sistare wrote: This begs the question, should we allow channels to be specified in hmp migrate commands and for -incoming, in a very simple way? Like with a prefix naming the channel. And eliminate the -cpr

Re: [PATCH V3 11/16] migration: cpr-transfer mode

On Tue, Nov 19, 2024 at 02:50:40PM -0500, Steven Sistare wrote: > On 11/14/2024 2:04 PM, Peter Xu wrote: > > On Thu, Nov 14, 2024 at 01:36:00PM -0500, Steven Sistare wrote: > > > On 11/13/2024 4:58 PM, Peter Xu wrote: > > > > On Fri, Nov 01, 2024 at 06:47:50AM -0700, Steve Sistare wrote: > > > > >

Re: [PATCH 5/5] qom: Make container_get() strict to always walk or return container

Il mar 19 nov 2024, 21:07 Peter Xu ha scritto: > > Ah, that was supposed to be the difference between type_register() and > > type_register_static(). > > Ah... looks like they're the same now? As type_register_static() looks like > a wrapper of type_register(). > And pretty much have always been

Re: [PATCH 5/5] qom: Make container_get() strict to always walk or return container

On Tue, Nov 19, 2024 at 10:03:22AM +, Daniel P. Berrangé wrote: > The docs are a welcome addition, but at the same time the docs won't get > read most of the time. > > With this in mind, IMHO, it is a conceptually *terrible* design for us to > have a method called "get" which magically *create

Re: [PATCH 1/5] qom: Add TYPE_CONTAINER macro

On Tue, Nov 19, 2024 at 09:42:45AM +, Daniel P. Berrangé wrote: > > -#define TYPE_OBJECT "object" > > +#define TYPE_OBJECT "object" > > +#define TYPE_CONTAINER "container" > > nitpick - 1 space too many before "TYPE_", and it is not worth > trying to vertically a

Re: [PATCH 5/5] qom: Make container_get() strict to always walk or return container

On Tue, Nov 19, 2024 at 09:09:16AM +0100, Paolo Bonzini wrote: > Il mar 19 nov 2024, 00:06 Peter Xu ha scritto: > > > On Mon, Nov 18, 2024 at 05:13:30PM -0500, Peter Xu wrote: > > > When used incorrectly, container_get() can silently create containers > > even > > > if the caller may not intend t

Re: [PATCH V3 11/16] migration: cpr-transfer mode

On 11/14/2024 2:04 PM, Peter Xu wrote: On Thu, Nov 14, 2024 at 01:36:00PM -0500, Steven Sistare wrote: On 11/13/2024 4:58 PM, Peter Xu wrote: On Fri, Nov 01, 2024 at 06:47:50AM -0700, Steve Sistare wrote: Add the cpr-transfer migration mode. Usage: qemu-system-$arch -machine anon-alloc=me

Re: [PULL v2 0/8] Block layer patches

On Tue, 19 Nov 2024 at 17:28, Kevin Wolf wrote: > > The following changes since commit e6459afb1ff4d86b361b14f4a2fc43f0d2b4d679: > > Merge tag 'pull-target-arm-20241119' of > https://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-11-19 > 14:23:34 +00

[PATCH for-10.0 v2 7/8] target/riscv/kvm: remove irqchip_split() restriction

Remove the 'irqchip_split()' restriction in kvm_arch_init() now that we have support for "-accel kvm,kernel-irqchip=split". Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/kvm/kvm-cpu.c | 5 - 1 file changed, 5 deletions(-) diff --git a/target/riscv/kv

[PATCH for-10.0 v2 0/8] riscv: AIA userspace irqchip_split support

Hi, This second version was rebased with 'master'. Alistair's acks were included. No other changes were made. All patches acked/reviewed. Changes from v1: - rebased with master @ af4c4fd128 - v1 link: https://lore.kernel.org/qemu-riscv/20241010190337.376987-1-dbarb...@ventanamicro.com/ Daniel

Re: [PATCH 0/8] riscv: AIA userspace irqchip_split support

On 11/17/24 11:05 PM, Alistair Francis wrote: On Fri, Oct 11, 2024 at 5:04 AM Daniel Henrique Barboza wrote: Hi, This series adds AIA irqchip_split support, effective when using AIA with aia=aplic-imsic and -accel kvm,kernel-irqchip=split. The main difference between what we currently hav

[PATCH for-10.0 v2 3/8] hw/riscv/virt.c: rename helper to virt_use_kvm_aia_aplic_imsic()

Similar to the riscv_is_kvm_aia_aplic_imsic() helper from riscv_aplic.c, the existing virt_use_kvm_aia() is testing for KVM aia=aplic-imsic with in-kernel irqchip enabled. It is not checking for a generic AIA support. Rename the helper to virt_use_kvm_aia_aplic_imsic() to reflect what the helper i

[PATCH for-10.0 v2 8/8] docs: update riscv/virt.rst with kernel-irqchip=split support

Also add a new page, docs/specs/riscv-aia.rst, where we're documenting the state of AIA support in QEMU w.r.t the controllers being emulated or not depending on the AIA and accelerator settings. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- docs/specs/index.rst

[PATCH for-10.0 v2 1/8] hw/intc/riscv_aplic: rename is_kvm_aia()

The helper is_kvm_aia() is checking not only for AIA, but for aplic-imsic (i.e. "aia=aplic-imsic" in 'virt' RISC-V machine) with an in-kernel chip present. Rename it to be a bit clear what the helper is doing since we'll add more AIA helpers in the next patches. Make the helper public because the

[PATCH for-10.0 v2 6/8] hw/intc/riscv_aplic: add kvm_msicfgaddr for split mode aplic-imsic

The last step to enable KVM AIA aplic-imsic with irqchip in split mode is to deal with how MSIs are going to be sent. In our current design we don't allow an APLIC controller to send MSIs unless it's on m-mode. And we also do not allow Supervisor MSI address configuration via the 'smsiaddrcfg' and

[PATCH for-10.0 v2 5/8] hw/riscv/virt.c, riscv_aplic.c: add 'emulated_aplic' helpers

The current logic to determine if we don't need an emulated APLIC controller, i.e. KVM will provide for us, is to determine if we're running KVM, with in-kernel irqchip support, and running aia=aplic-imsic. This is modelled by riscv_is_kvm_aia_aplic_imsic() and virt_use_kvm_aia_aplic_imsic(). This

Re: [PATCH 13/15] tests/functional: rewrite console handling to be bytewise

On Tue, Nov 19, 2024 at 06:11:10PM +0100, Paolo Bonzini wrote: > On 11/19/24 16:05, Daniel P. Berrangé wrote: > > The console interaction that waits for predicted strings uses > > readline(), and thus is only capable of waiting for strings > > that are followed by a newline. > > > > This is inconv

Re: [PATCH 00/15] test/functional: improve functional test debugging & fix tuxrun

On 11/19/24 16:05, Daniel P. Berrangé wrote: This started out as a series to get rid of the many GBs of temp files the functional tests leave behind. Then it expanded into improving the functional test debugging by ensuring we preserve the QEMU stdout/stderr log file created by the QEMUMachine cl

Re: [PATCH 01/15] tests/functional: fix mips64el test to honour workdir

On 19/11/24 16:05, Daniel P. Berrangé wrote: The missing directory separator resulted in the kernel file being created 1 level higher than expected. Signed-off-by: Daniel P. Berrangé --- tests/functional/test_mips64el_malta.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

Re: [PATCH 02/15] tests/functional: automatically clean up scratch files after tests

On 19/11/2024 17.21, Alex Bennée wrote: Daniel P. Berrangé writes: The build/tests/functional subdirectories are consuming huge amounts of disk space. Split the location for scratch files into a 'scratch' sub-directory, separate from log files, and delete it upon completion of each test. The

Re: [PATCH 03/15] tests/functional: remove "AVOCADO" from env variable name

Daniel P. Berrangé writes: > This env variable is a debugging flag to save screendumps in the > mips64el malta tests. > > Signed-off-by: Daniel P. Berrangé Reviewed-by: Alex Bennée -- Alex Bennée Virtualisation Tech Lead @ Linaro

Re: [PATCH 10/15] tests/functional: honour requested test VM name in QEMUMachine

On 19/11/2024 16.05, Daniel P. Berrangé wrote: The functional test case class is going to the trouble of passing around a machine name, but then fails to give this QEMUMachine. As a result, QEMUMachine will create a completely random name. Since log file names match the machine name, this results

Re: [PATCH] hvf: remove unused but set variable

Queued, thanks. Paolo

Re: [PATCH 07/15] tests/functional: remove comments talking about avocado

On 19/11/2024 16.05, Daniel P. Berrangé wrote: The first comment is still relevant but should talk about our own test harness instead. The second comment adds no value over reading the code and can be removed. Signed-off-by: Daniel P. Berrangé --- tests/functional/test_acpi_bits.py | 12 +

Re: Status of some Arm features

On Tue, 19 Nov 2024 at 16:52, Pierrick Bouvier wrote: > > On 11/19/24 02:09, Peter Maydell wrote: > > On Mon, 18 Nov 2024 at 23:33, Pierrick Bouvier > > wrote: > >> I'm currently reviewing the QEMU Arm documentation, and I have a > >> question about the status of following features: > >> > >> 8.0

Re: [PATCH 08/15] tests/functional: honour self.workdir in ACPI bits tests

Daniel P. Berrangé writes: > The ACPI bits test sets up its own private temporary directory into it > creates scratch files. This is justified by a suggestion that we need > to be able to preserve the scratch files. We have the ability to > preserve the scratch dir with our functional harness, so

Re: [PATCH 03/15] tests/functional: remove "AVOCADO" from env variable name

On 19/11/24 16:05, Daniel P. Berrangé wrote: This env variable is a debugging flag to save screendumps in the mips64el malta tests. Signed-off-by: Daniel P. Berrangé --- tests/functional/test_mips64el_malta.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Philippe Math

Re: [PATCH v4 0/3] plugins: generate list of symbols automatically

On 11/19/24 06:13, Alex Bennée wrote: Pierrick Bouvier writes: Now that meson build for plugins was merged, we can cleanup another part with the symbols file. It has to be kept in sync between the header (qemu-plugin.h) and the symbols file. This has proved to be error prone and tedious. We s

Re: [PATCH] docs: aspeed: Reorganize the "Boot options" section

On 11/18/24 10:06, Cédric Le Goater wrote: Add subsubsections for possible boot methods and introduce a new section on eMMC boot support for the ast2600-evb and rainier-emmc machines, boot partitions assumptions and limitations. Signed-off-by: Cédric Le Goater --- docs/system/arm/aspeed.rst |

Re: Status of some Arm features

On 11/19/24 02:09, Peter Maydell wrote: On Mon, 18 Nov 2024 at 23:33, Pierrick Bouvier wrote: I'm currently reviewing the QEMU Arm documentation, and I have a question about the status of following features: 8.0: - FEAT_DoubleLock, Double Lock This is actually an "anti-feature" :-) It is op

Re: [PATCH 05/15] tests/functional: remove leftover :avocado: tags

Daniel P. Berrangé writes: > These tags are not honoured under the new functional test harness. > > Signed-off-by: Daniel P. Berrangé Reviewed-by: Alex Bennée -- Alex Bennée Virtualisation Tech Lead @ Linaro

Re: [PATCH 04/15] tests/functional: remove todo wrt avocado.utils.wait_for

Daniel P. Berrangé writes: > We're not using avocado anymore, so while the TODO item is still > relevant, suggesting use of avocado.utils is not. > > Signed-off-by: Daniel P. Berrangé Reviewed-by: Alex Bennée -- Alex Bennée Virtualisation Tech Lead @ Linaro

Re: [PATCH 02/15] tests/functional: automatically clean up scratch files after tests

Daniel P. Berrangé writes: > The build/tests/functional subdirectories are consuming huge amounts > of disk space. > > Split the location for scratch files into a 'scratch' sub-directory, > separate from log files, and delete it upon completion of each test. > The new env variable QEMU_TEST_KEEP_

[PATCH v2 1/3] scripts: mandate that new files have SPDX-License-Identifier

Going forward we want all newly created source files to have an SPDX-License-Identifier tag present. Initially mandate this for C, Python, Perl, Shell source files, as well as JSON (QAPI) and Makefiles, while encouraging users to consider it for other file types. Reviewed-by: Brian Cain Reviewed

[RFC PATCH] docs: Add roadmap for heterogeneous emulation

This document tries to document the steps required to: - Have a single binary to run system emulations - Emulate different architectures in the same process - Have QEMU assemble dynamic machines at runtime Signed-off-by: Philippe Mathieu-Daudé --- This is the document that was discussed at th

Re: [PULL for 9.2 0/4] updates (virtio-gpu, gdbstub testing, MAINTAINERS)

On Mon, 18 Nov 2024 at 20:42, Alex Bennée wrote: > > The following changes since commit 0fbc798e4f51d6d2bc05f4965b0eae74ba204471: > > Merge tag 'pull-vfio-20241118' of https://github.com/legoater/qemu into > staging (2024-11-18 10:04:04 +) > > are available in the Git repository at: > > h

[PATCH 02/15] tests/functional: automatically clean up scratch files after tests

The build/tests/functional subdirectories are consuming huge amounts of disk space. Split the location for scratch files into a 'scratch' sub-directory, separate from log files, and delete it upon completion of each test. The new env variable QEMU_TEST_KEEP_SCRATCH can be set to preserve this scra

[PULL 12/15] hw/intc/loongarch_extioi: Use set_bit32() and clear_bit32() for s->isr

In extioi_setirq() we try to operate on a bit array stored as an array of uint32_t using the set_bit() and clear_bit() functions by casting the pointer to 'unsigned long *'. This has two problems: * the alignment of 'uint32_t' is less than that of 'unsigned long' so we pass an insufficiently al

[PULL 07/15] tests/qtest/cmsdk-apb-watchdog-test: Test INTEN as counter enable

From: Roque Arcudia Hernandez The following tests focus on making sure the counter is not running out of reset and the proper use of INTEN as the counter enable. As described in: https://developer.arm.com/documentation/ddi0479/d/apb-components/apb-watchdog/programmers-model The new tests have t

Re: [PULL 00/15] target-arm queue

Merge tag 'pull-nbd-2024-11-18' of https://repo.or.cz/qemu/ericb into > staging (2024-11-18 20:24:05 +) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git > tags/pull-target-arm-20241119 > > for you

[PULL 13/15] system/dma-helpers.c: Move trace events to system/trace-events

The dma-helpers.c file is in the system/ subdirectory, but it defines its trace events in the root trace-events file. Move them to the system/trace-events file where they more naturally belong. Fixes: 800d4deda0 ("softmmu: move more files to softmmu/") Signed-off-by: Peter Maydell Reviewed-by: Ri

Re: [PATCH for 9.2 2/2] hw/core/machine-smp: Fix error message parameter

On 10/11/24 16:09, Zhao Liu wrote: In the loop checking smp cache support, the error message should report the current cache level and type. Fix the parameter of error_setg() to ensure it reports the correct cache level and type. Resolves: Coverity CID 1565391 Fixes: f35c0221fef8 ("hw/core: Che

[PATCH 12/15] tests/functional: logs details of console interaction operations

When functional tests go wrong, it will often be related to the console interaction wait state. By logging the messages that we're looking for, and data we're about to be sending, it'll be easier to diagnose where tests are getting stuck. Signed-off-by: Daniel P. Berrangé --- tests/functional/qe

Re: [PATCH-for-10.0] arm: Remove tacoma-bmc machine

On 19/11/24 08:13, Cédric Le Goater wrote: Removal was scheduled for 10.0. Use the rainier-bmc machine or the ast2600-evb as a replacement. Signed-off-by: Cédric Le Goater --- docs/about/deprecated.rst | 8 docs/about/removed-features.rst | 10 ++ docs/system/arm/asp

Re: [PATCH for 9.2 1/2] hw/core/machine-smp: Initialize caches_bitmap before reading

On 10/11/24 16:09, Zhao Liu wrote: The caches_bitmap is defined in machine_parse_smp_cache(), but it was not initialized. Initialize caches_bitmap by clearing all its bits to zero. Resolves: Coverity CID 1565389 Fixes: 4e88e7e3403d ("qapi/qom: Define cache enumeration and properties for machin

[PATCH 13/15] tests/functional: rewrite console handling to be bytewise

The console interaction that waits for predicted strings uses readline(), and thus is only capable of waiting for strings that are followed by a newline. This is inconvenient when needing to match on some things, particularly login prompts, or shell prompts, causing tests to use time.sleep(...) in

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