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Song Gao is will be sick leave for a long time, I apply for maintainer
for LoongArch VirtMachien during this period, LoongArch TCG keeps unchanged
since I am not familiar with it. The maintainer duty will transfer to him
after he comes back to work.
Signed-off-by: Bibo Mao
---
MAINTAINERS | 1 +
On 12/11/2024 07.28, Cédric Le Goater wrote:
These were introduced in the avocado tests to workaround read issues
when interacting with console. They are no longer necessary.
Signed-off-by: Cédric Le Goater
---
tests/functional/test_arm_aspeed.py | 7 ++-
1 file changed, 2 insertions(+),
On 12/11/2024 07.28, Cédric Le Goater wrote:
Interaction with the console has been a problem in our avocado
tests. In some cases, the expected string does not match in the
output, causing the test to fail with a timeout. These were worked
around by sleeping before reading the console and even wit
On Tue, 12 Nov 2024 at 12:08, Dmitry Frolov wrote:
> "int main(int argc, char **argv, char** envp)" is non-standart
standart -> standard
> Microsoft`s extention of the C language and it`s not portable.
* But it looks widely supported.
> In my particular case (Debian 13, clang-16) this raises w
Hi,
On Mon, 11 Nov 2024 at 22:51, Alexey Khoroshilov wrote:
> On 11.11.2024 16:35, Дмитрий Фролов wrote:
> Not allowed to read the exact memory area, because it is marked as freed.
>
> As far as I understand, heap-use-after-free means a situation when code
> allocates memory then frees it and th
On 12/11/2024 07.28, Cédric Le Goater wrote:
Drop the SSH connection which was introduced in the avocado tests to
workaround read issues when interacting with console.
Signed-off-by: Cédric Le Goater
---
tests/avocado/machine_aspeed.py | 78
tests/functional/meso
"int main(int argc, char **argv, char** envp)" is non-standart
Microsoft`s extention of the C language and it`s not portable.
In my particular case (Debian 13, clang-16) this raises wild-pointer
dereference with ASAN message "heap-use-after-free".
v2: changed confusing commit header
Signed-off-by
On 06/09/2024 14.25, Guenter Roeck wrote:
Some machines (like Aspeed ARM) only have a sysbus UHCI controller.
The current UHCI implementation only supports PCI based UHCI controllers.
Move the UHCI-PCI device code into a separate file so that it is possible
to create a sysbus UHCI device without
Interaction with the console has been a problem in our avocado
tests. In some cases, the expected string does not match in the
output, causing the test to fail with a timeout. These were worked
around by sleeping before reading the console and even with SSH
connections in some places.
To fix, proc
Hello,
The first patch is a proposal to fix a long-standing issue when
capturing the console output. In some cases, the expected string does
not match in the output, causing the test to fail with a timeout. The
change introduces a _console_read() routine that processes the console
output character
Drop the SSH connection which was introduced in the avocado tests to
workaround read issues when interacting with console.
Signed-off-by: Cédric Le Goater
---
tests/avocado/machine_aspeed.py | 78
tests/functional/meson.build| 2 +
tests/functional/test_
These were introduced in the avocado tests to workaround read issues
when interacting with console. They are no longer necessary.
Signed-off-by: Cédric Le Goater
---
tests/functional/test_arm_aspeed.py | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/tests/functional/te
Drop the SSH connection which was introduced in the avocado tests to
workaround read issues when interacting with console.
Signed-off-by: Cédric Le Goater
---
tests/avocado/machine_aspeed.py | 124
tests/functional/test_arm_aspeed.py | 67 +++
2 file
Paolo Bonzini writes:
> Il mar 12 nov 2024, 04:17 Junjie Mao ha scritto:
>
> Making a universal unexpected_cfgs apply to the whole workspace may lead
> to a lengthy cfg list when more devices in Rust are added. As cargo does
> not allow overriding workspace-defined lints once inherited, I t
Il mar 12 nov 2024, 03:47 Junjie Mao ha scritto:
> I agree that storing generated stuff in the source directory should not
> be encouraged.
>
> Just want to mention that such changes can lead to trouble to
> rust-analyzer. Today there are two ways to inform rust-analyzer of the
> project structur
Reviewed-by: Pavel Dovgalyuk
On 12.11.2024 01:29, Philippe Mathieu-Daudé wrote:
Use Octeon decodetree to call gen_lx() for the LX instructions.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/octeon.decode | 8
target/mips/tcg/octeon_translate.c | 12
Il mar 12 nov 2024, 04:17 Junjie Mao ha scritto:
> Making a universal unexpected_cfgs apply to the whole workspace may lead
> to a lengthy cfg list when more devices in Rust are added. As cargo does
> not allow overriding workspace-defined lints once inherited, I think it
> better to keep unexpec
On 2024/11/8 下午9:55, Peter Maydell wrote:
In extioi_setirq() we try to operate on a bit array stored as an
array of uint32_t using the set_bit() and clear_bit() functions
by casting the pointer to 'unsigned long *'.
This has two problems:
* the alignment of 'uint32_t' is less than that of 'u
Got it, thank you.
Sincerely,
Fea
On Tue, Nov 12, 2024 at 2:33 AM Daniel Henrique Barboza <
dbarb...@ventanamicro.com> wrote:
>
>
> On 11/8/24 5:52 AM, Fea.Wang wrote:
> > Add "svukte" in the ISA string when svukte extension is enabled.
> >
> > Signed-off-by: Fea.Wang
> > Reviewed-by: Frank Cha
Paolo Bonzini writes:
> An extra benefit of workspaces is that they allow to place lint level
> settings in a single Cargo.toml; the settings are then inherited by
> packages in the workspace.
>
> Correspondingly, teach rustc_build_args.py to get the unexpected_cfgs
> configuration from the wor
Paolo Bonzini writes:
> Only qemu-api needs access to the symbols in config-host.h.
This may no longer be the case when more complex, build-time
configurable devices are added in the future.
Moving rustc_args.py calls to each crate is still helpful because of the
changes in patches 3-6 in thi
Paolo Bonzini writes:
> rust/qemu-api/src/lib.rs is disabling lints that cause problems
> with code generated by bindgen.
The commit title is misleading. Today the lint-disabling attributes are
outer ones which apply only to the bindings module. Those lints already
apply to the others in the q
On LoongArch virt machine, ACPI GED hardware is used for CPU hotplug
handler, here CPU hotplug support feature is added based on GED handler,
also CPU scan and reject method is added about CPU device in DSDT table.
Co-developed-by: Xianglai Li
Signed-off-by: Bibo Mao
---
hw/loongarch/Kconfig
Add topological relationships for Loongarch VCPU and initialize
topology member variables. Also physical cpu id calculation
method comes from its topo information.
Co-developed-by: Xianglai Li
Signed-off-by: Bibo Mao
---
docs/system/loongarch/virt.rst | 31 +++
hw/loongarch/virt.c
On virt machine, enable CPU hotplug feature has_hotpluggable_cpus. For
hot-added CPUs, there is socket-id/core-id/thread-id property set,
arch_id can be caculated from these properties. So that cpu slot can be
searched from its arch_id.
Also change num-cpu property of extioi and ipi from smp.cpus
Here generic function virt_init_cpu_irq() is added to init interrupt
pin of CPU object, IPI and extioi interrupt controllers are connected
to interrupt pin of CPU object.
The generic function can be used to both cold-plug and hot-plug CPUs.
Signed-off-by: Bibo Mao
---
hw/loongarch/virt.c
LoongArch cpu hotplug is based on ACPI GED device, there is a little
change about ipi and extioi device, the value of num-cpu property is
maximum cpu number rather than present cpu number.
It can be verified with qemu command:
qemu-system-loongarch64 -smp 2,maxcpus=16,sockets=4,cores=4,threads=1
Add cpu hotplug interface, however cpu hotplug feature is still
disabled for the machine. When machine is on, all created vCPUs
go through hotplug interface, and there is no remaining vCPU which
can be hot-added after power on.
Co-developed-by: Xianglai Li
Signed-off-by: Bibo Mao
---
hw/loongar
Move CPU object creation after interrupt controller ipi and extioi,
and init interrupt pin of CPU in plug interface virt_cpu_plug().
So interrupt pin initialization of the cold-plug CPUs is the same
with that of hot-plug CPUs.
Signed-off-by: Bibo Mao
---
hw/loongarch/virt.c | 84 +++
On Mon, 11 Nov 2024, Phil Dennis-Jordan wrote:
On Mon, 11 Nov 2024 at 13:41, BALATON Zoltan wrote:
On Mon, 11 Nov 2024, Phil Dennis-Jordan wrote:
On Mon, 11 Nov 2024 at 10:08, Daniel P. Berrangé
wrote:
On Sun, Nov 10, 2024 at 08:08:16AM +0100, Phil Dennis-Jordan wrote:
On Sun 10. Nov 2024
of_dpa_cmd_add_acl_ip() is called from a single place, and despite the
fact that it always returns ROCKER_OK, its return value is still checked
by the caller.
Change of_dpa_cmd_add_acl_ip() to return void and remove the superfluous
check from of_dpa_cmd_add_acl().
Resolves: https://gitlab.com/qemu-
v2,
Fixes after Dimitry's review.
Alex.
Alex Bennée (2):
hw/display: factor out the scanout blob to fb conversion
hw/display: check frame buffer can hold blob
include/hw/virtio/virtio-gpu.h | 15 +
hw/display/virtio-gpu-virgl.c | 22 +
hw/display/virtio-gpu.c|
There are two identical sequences of a code doing the same thing that
raise warnings with Coverity. Before fixing those issues lets factor
out the common code into a helper function we can share.
Signed-off-by: Alex Bennée
Cc: Dmitry Osipenko
---
v2
- fix compile of virtio-gpu-virgl
- tweak
Coverity reports (CID 1564769, 1564770) that we potentially overflow
by doing some 32x32 multiplies for something that ends up in a 64 bit
value. Fix this by first using stride for all lines and casting input
to uint64_t to ensure a 64 bit multiply is used.
Signed-off-by: Alex Bennée
Cc: Dmitry O
From: Philippe Mathieu-Daudé
Simply call the generic gen_lsa() helper, taking care
to substract 1 to the shift field.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/nanomips32.decode| 8
target/mips/tcg/nanomips_translate.c
From: Philippe Mathieu-Daudé
Introduce the nanoMIPS decodetree configs for the 16-bit
and 32-bit instructions.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/translate.h | 2 ++
target/mips/tcg/nanomips16.decode| 8 ++
Yet another 2 patches extracted from an old branch
I'm rebasing. Trivial decodetree conversion of LSA,
however this introduce the basis to convert nanoMIPS
opcodes.
Philippe Mathieu-Daudé (2):
target/mips: Introduce decode tree bindings for nanoMIPS ISA
target/mips: Convert nanoMIPS LSA opcode
On Fri, Nov 08, 2024 at 05:58:14PM +, Jonathan Cameron wrote:
> Zero length data for features doesn't make any sense so exclude that case
> early. This fixes the undefined behavior reported by coverity for a zero
> length memcpy().
>
> Resolves CID 1564900 and 1564901
>
> Reported-by: Peter M
Extract gen_lx() from gen_mips_lx(); inline the Octeon
check in decode_opc_special3_legacy().
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/translate.h | 1 +
target/mips/tcg/translate.c | 55 +
2 files changed, 20 insertions(+), 36 deletions(-)
Use Octeon decodetree to call gen_lx() for the LX instructions.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/octeon.decode | 8
target/mips/tcg/octeon_translate.c | 12
target/mips/tcg/translate.c| 4 +---
3 files changed, 21 insertions(+), 3 del
Factor out gen_base_index_addr() which is used twice
but we'll use it more.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/translate.h | 1 +
target/mips/tcg/translate.c | 27 +--
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/target/mips/tcg
Hi,
Few old patches lingering on an old branch I'm trying to rebase...
Extract gen_lx() and call it via decodetree. Trivial IMHO.
Philippe Mathieu-Daudé (3):
target/mips: Extract gen_base_index_addr() helper
target/mips: Extract generic gen_lx() helper
target/mips: Convert Octeon LX instru
On 11/8/24 4:04 AM, Jim Shu wrote:
DTB is placed to the end of memory, so we will check if the start
address of DTB overlaps to the address of kernel/initrd.
Signed-off-by: Jim Shu
---
Reviewed-by: Daniel Henrique Barboza
hw/riscv/boot.c | 25 -
inclu
On 11/8/24 4:04 AM, Jim Shu wrote:
Add a new struct RISCVBootInfo to sync boot information between multiple
boot functions.
Signed-off-by: Jim Shu
---
hw/riscv/boot.c| 65 +-
hw/riscv/microchip_pfsoc.c | 12 +++---
hw/riscv/opentita
Reviewed-by: Glenn Miles
On Thu, 2024-11-07 at 19:54 +, Titus Rwantare wrote:
> Makes it more explicit that 16 bit values are being used
>
> Signed-off-by: Titus Rwantare
> ---
> include/qemu/bitops.h | 26 ++
> 1 file changed, 26 insertions(+)
>
> diff --git a/inc
On 11/8/24 4:04 AM, Jim Shu wrote:
Larger initrd image will overlap the DTB at 3GB address. Since 64-bit
system doesn't have 32-bit addressable issue, we just load DTB to the end
of dram in 64-bit system.
Signed-off-by: Jim Shu
---
hw/riscv/boot.c| 8 ++--
hw/riscv/microch
On 09/11/2024 08:25, Thomas Huth wrote:
Am Wed, 23 Oct 2024 09:58:49 +0100
schrieb Mark Cave-Ayland :
Move these functions in next-cube.c so that they are with the rest of the
next-rtc functions.
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/next-cube.c | 172 ++--
On 09/11/2024 08:24, Thomas Huth wrote:
Am Wed, 23 Oct 2024 09:58:47 +0100
schrieb Mark Cave-Ayland :
This allows us to decouple the next-pc and next-rtc devices from each
other in next_scr2_rtc_update().
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/next-cube.c | 23 +++
On 09/11/2024 08:14, Thomas Huth wrote:
Am Wed, 23 Oct 2024 09:58:43 +0100
schrieb Mark Cave-Ayland :
This is to allow the RTC functionality to be maintained within its own separate
device.
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/next-cube.c | 66 ---
On 11/6/24 01:14, Jiqian Chen wrote:
> In PVH dom0, when passthrough a device to domU, QEMU code
> xen_pt_realize->xc_physdev_map_pirq wants to use gsi, but in current codes
> the gsi number is got from file /sys/bus/pci/devices//irq, that is
> wrong, because irq is not equal with gsi, they are in
On 11/8/24 5:52 AM, Fea.Wang wrote:
Add "svukte" in the ISA string when svukte extension is enabled.
Signed-off-by: Fea.Wang
Reviewed-by: Frank Chang
Reviewed-by: Jim Shu
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
On 11/8/24 5:52 AM, Fea.Wang wrote:
Follow the Svukte spec, do the memory access address checking
1. Include instruction fetches or explicit memory accesses
2. System run in effective privilege U or VU
3. Check senvcfg[UKTE] being set, or hstatus[HUKTE] being set if
instruction is HLV, HL
On 11/8/24 5:52 AM, Fea.Wang wrote:
Refer to the draft of svukte extension from:
https://github.com/riscv/riscv-isa-manual/pull/1564
Svukte provides a means to make user-mode accesses to supervisor memory
raise page faults in constant time, mitigating attacks that attempt to
discover the supe
On 11/8/24 5:52 AM, Fea.Wang wrote:
Svukte extension add UKTE bit, bit[8] in senvcfg CSR. The bit will be
supported when the svukte extension is enabled.
When senvcfg[UKTE] bit is set, the memory access from U-mode should do
the svukte check only except HLV/HLVX/HSV H-mode instructions which
On 11/8/24 5:52 AM, Fea.Wang wrote:
Svukte extension add HUKTE bit, bit[24] in hstatus CSR. The written
value will be masked when the svukte extension is not enabled.
When hstatus[HUKTE] bit is set, HLV/HLVX/HSV work in the U-mode should
do svukte check.
Signed-off-by: Fea.Wang
Reviewed-by:
On 11/8/24 3:01 AM, baturo.ale...@gmail.com wrote:
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4e80dcd2e6..13b2c56a72 100644
--- a/target/riscv/cpu.c
+++ b/
On 11.11.2024 16:35, Дмитрий Фролов wrote:
>
>
> On 11.11.2024 15:51, Prasad Pandit wrote:
>> On Mon, 11 Nov 2024 at 17:41, Дмитрий Фролов wrote:
>>> Above loop dereferences the pointer env, which is pointing to
>>> the memory area, which is not allowed to read.
>> * Not allowed to read environmen
Philippe Mathieu-Daudé writes:
> On 11/11/24 14:52, Fabiano Rosas wrote:
>> ASAN detected a leak when running the ahci-test
>> /ahci/io/dma/lba28/retry:
>>
>> Direct leak of 35 byte(s) in 1 object(s) allocated from:
>> #0 in malloc
>> #1 in __vasprintf_internal
>> #2 in vasprintf
Expose the method docstring in the header, and mention
returned value must be free'd by caller.
Reported-by: Fabiano Rosas
Signed-off-by: Philippe Mathieu-Daudé
---
include/sysemu/block-backend-io.h | 7 +++
block/block-backend.c | 12
2 files changed, 15 insertion
From: Fabiano Rosas
ASAN detected a leak when running the ahci-test
/ahci/io/dma/lba28/retry:
Direct leak of 35 byte(s) in 1 object(s) allocated from:
#0 in malloc
#1 in __vasprintf_internal
#2 in vasprintf
#3 in g_vasprintf
#4 in g_strdup_vprintf
#5 in g_strdup_printf
Respin of Fabiano patch using g_autofree,
and clarifying method docstrings.
Fabiano Rosas (1):
block: Fix leak in send_qmp_error_event
Philippe Mathieu-Daudé (1):
block: Improve blk_get_attached_dev_id() docstring
include/sysemu/block-backend-io.h | 7 +++
block/block-backend.c
On 11/11/24 14:52, Fabiano Rosas wrote:
ASAN detected a leak when running the ahci-test
/ahci/io/dma/lba28/retry:
Direct leak of 35 byte(s) in 1 object(s) allocated from:
#0 in malloc
#1 in __vasprintf_internal
#2 in vasprintf
#3 in g_vasprintf
#4 in g_strdup_vprintf
Hi Richard, Daniel,
This might be a silly question, but why do we need to ensure atomicity
when emulating these guest instructions? I might be wrong but I didn't
see an explicit requirement for the vector instructions to be atomic in
the documentation of the RISC-V V extension.
Anyway the pa
In cases where object_new() is not being passed a static, const
string, the caller cannot be sure what type they are instantiating.
There is a risk that instantiation could fail, if it is an abstract
type.
Convert such cases over to use object_new_dynamic() such that they
are forced to expect fail
NB, this series is targetting 10.0, NOT for 9.2 freeze.
With code like
Object *obj = object_new(TYPE_BLAH)
the caller can be pretty confident that they will successfully create
an object instance of TYPE_BLAH. They know exactly what type has been
requested, so it passing an abstract type for
Since object_new() will assert(), it should only be used in scenarios
where the caller knows exactly what type it is asking to be created,
and can thus be confident in avoiding abstract types.
Enforce this by using a macro wrapper which types to paste "" to the
type name. This will generate a comp
Since qdev_new() will assert(), it should only be used in scenarios
where the caller knows exactly what type it is asking to be created,
and can thus be confident in avoiding abstract types.
Enforce this by using a macro wrapper which types to paste "" to the
type name. This will generate a compil
object_new() has a failure scenario where it will assert() if given
an abstract type. Callers which are creating objects based on user
input, or unknown/untrusted type names, must manually check the
result of object_class_is_abstract() before calling object_new()
to propagate an Error, instead of a
Since object_new_with_class() accepts a non-const parameter for
the class, callers should be prepared for failures from unexpected
input. Add an Error parameter for this and make callers check.
If the caller does not already have an Error parameter, it is
satisfactory to use &error_abort if the cla
In cases where qdev_new() is not being passed a static, const
string, the caller cannot be sure what type they are instantiating.
There is a risk that instantiation could fail, if it is an abstract
type.
Convert such cases over to use qdev_new_dynamic() such that they
are forced to expect failure.
Push an Error object into object_initialize_with_type, so that
reporting of attempts to create an abstract type is handled at
the lowest level.
Signed-off-by: Daniel P. Berrangé
---
qom/object.c | 30 --
1 file changed, 20 insertions(+), 10 deletions(-)
diff --git a/
qdev_new() has a failure scenario where it will assert() if given
an abstract type. Callers which are creating qdevs based on user
input, or unknown/untrusted type names, must manually check the
result of qdev_class_is_abstract() before calling qdev_new()
to propagate an Error, instead of asserting
On 11/11/24 06:59, Richard Henderson wrote:
On 10/23/24 16:47, J. Neuschäfer wrote:
This aligns with strace, and is very useful when tracing multi-threaded
programs. The result is the same in single-threaded programs.
See also "-D log.%d -d tid -strace" which will split the output into per-tid
On 11/7/24 22:01, baturo.ale...@gmail.com wrote:
@@ -2424,6 +2433,12 @@ static RISCVException write_senvcfg(CPURISCVState *env,
int csrno,
target_ulong val)
{
uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE |
SENVCFG_CBZE;
+/* Update
On 10/23/24 16:47, J. Neuschäfer wrote:
This aligns with strace, and is very useful when tracing multi-threaded
programs. The result is the same in single-threaded programs.
See also "-D log.%d -d tid -strace" which will split the output into per-tid
files.
gettid() requires the _GNU_SOURCE
Richard Henderson writes:
> The acc_flag check for write should have been against PAGE_WRITE_ORG,
> not PAGE_WRITE. But it is better to combine two acc_flag checks
> to a single check against access_type. This matches the system code
> in cputlb.c.
>
> Resolves: https://gitlab.com/qemu-project/
On Sat, 9 Nov 2024 00:07:27 +
Salil Mehta wrote:
> Checking `is_present` first can break x86 migration from new Qemu
> version to old Qemu. This is because CPRS Bit is not defined in the
> older Qemu register block and will always be 0 resulting in check always
> failing. Remove CPU_PRESENT B
On Sun, Nov 10, 2024 at 1:10 PM Yan Vugenfirer wrote:
> Please take a look is this is host\guest common struct
>
> -- Forwarded message -
> From: Peter Maydell
> Date: Thu, Nov 7, 2024 at 6:33 PM
> Subject: [PATCH 1/2] hw/net/virtio-net.c: Don't assume IP length field is
> aligne
On 10/22/24 17:24, Ilya Leoshkevich wrote:
Running qemu-i386 on a system running with SELinux in enforcing mode
(more precisely: s390x trixie container on Fedora 40) fails with:
qemu-i386: tests/tcg/i386-linux-user/sigreturn-sigmask: Unable to find a
guest_base to satisfy all guest address
ASAN detected a leak when running the ahci-test
/ahci/io/dma/lba28/retry:
Direct leak of 35 byte(s) in 1 object(s) allocated from:
#0 in malloc
#1 in __vasprintf_internal
#2 in vasprintf
#3 in g_vasprintf
#4 in g_strdup_vprintf
#5 in g_strdup_printf
#6 in object_get_can
The acc_flag check for write should have been against PAGE_WRITE_ORG,
not PAGE_WRITE. But it is better to combine two acc_flag checks
to a single check against access_type. This matches the system code
in cputlb.c.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2647
Signed-off-by: Richa
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Nicholas Piggin writes:
> Add tests which init the host controller registers to the point
> where command and event rings, irqs are operational. Enumerate
> ports and set up an attached device context that enables device
> transfer ring to be set up and tested.
>
> This test does a bunch of thing
On Mon, Nov 04 2024, Eric Auger wrote:
> Hi Daniel,
>
> On 10/28/24 18:04, Daniel P. Berrangé wrote:
>> On Mon, Oct 28, 2024 at 04:48:18PM +, Peter Maydell wrote:
>>> On Mon, 28 Oct 2024 at 16:35, Daniel P. Berrangé
>>> wrote:
On Mon, Oct 28, 2024 at 04:16:31PM +, Peter Maydell wro
On Mon, 11 Nov 2024 at 05:45, Akihiko Odaki wrote:
>
> On 2024/11/11 6:55, Phil Dennis-Jordan wrote:
> > macOS's Cocoa event handling must be done on the initial (main) thread
> > of the process. Furthermore, if library or application code uses
> > libdispatch, the main dispatch queue must be hand
Nicholas Piggin writes:
> Add assertions to ensure a BAR is not mapped twice, and only
> previously mapped BARs are unmapped. This can help catch some
> bugs.
>
> Signed-off-by: Nicholas Piggin
Reviewed-by: Fabiano Rosas
In x86_load_linux(), we were using a stack-allocated array as data for
fw_cfg_add_bytes(). Since the latter just takes a reference to the
pointer instead of copying the data, it can happen that the contents
have been overridden by the time the guest attempts to access them.
Instead of using the st
On 11/11/24 8:11 AM, Thomas Huth wrote:
Now that we can boot from multiple boot devices, we have to make sure
to reinitialize static variables like rx_last_idx to avoid that they
contain garbage data during the second boot attempt (which can lead to
crashes when the code tries to access the wr
On 11.11.2024 15:51, Prasad Pandit wrote:
On Mon, 11 Nov 2024 at 17:41, Дмитрий Фролов wrote:
Above loop dereferences the pointer env, which is pointing to
the memory area, which is not allowed to read.
* Not allowed to read environment variables? Is it because
Debian/clang does not support
On Mon, 11 Nov 2024 at 13:41, BALATON Zoltan wrote:
> On Mon, 11 Nov 2024, Phil Dennis-Jordan wrote:
> > On Mon, 11 Nov 2024 at 10:08, Daniel P. Berrangé
> > wrote:
> >
> >> On Sun, Nov 10, 2024 at 08:08:16AM +0100, Phil Dennis-Jordan wrote:
> >>> On Sun 10. Nov 2024 at 08:01, Akihiko Odaki
> >
Now that we can boot from multiple boot devices, we have to make sure
to reinitialize static variables like rx_last_idx to avoid that they
contain garbage data during the second boot attempt (which can lead to
crashes when the code tries to access the wrong ring data).
Signed-off-by: Thomas Huth
The version 5 of the patch set splits the patches into independent submissions
so to simplify the review process.
Previous versions:
- v1:
https://lore.kernel.org/all/20240717153040.11073-1-paolo.sav...@embecosm.com/
- v2:
https://lore.kernel.org/all/20241002135708.99146-1-paolo.sav...@embecosm.
This patch improves the performance of the emulation of the RVV unit-stride
loads and stores in the following cases:
- when the data being loaded/stored per iteration amounts to 8 bytes or less.
- when the vector length is 16 bytes (VLEN=128) and there's no grouping of the
vector registers (LMUL
On Mon, 11 Nov 2024 at 17:41, Дмитрий Фролов wrote:
> Above loop dereferences the pointer env, which is pointing to
> the memory area, which is not allowed to read.
* Not allowed to read environment variables? Is it because
Debian/clang does not support the '**envp' parameter? Is '**envp' set
to
On Mon, 11 Nov 2024, Phil Dennis-Jordan wrote:
On Mon, 11 Nov 2024 at 10:08, Daniel P. Berrangé
wrote:
On Sun, Nov 10, 2024 at 08:08:16AM +0100, Phil Dennis-Jordan wrote:
On Sun 10. Nov 2024 at 08:01, Akihiko Odaki
wrote:
On 2024/11/08 23:46, Phil Dennis-Jordan wrote:
macOS's Cocoa event
On Mon, 11 Nov 2024, Sebastian Ott wrote:
PCI hotplug for downstream endpoints on arm fails because Linux'
PCIe hotplug driver doesn't like the QEMU provided LNKSTA:
pcieport :08:01.0: pciehp: Slot(2): Card present
pcieport :08:01.0: pciehp: Slot(2): Link Up
pcieport :08:01.0: pci
PCI hotplug for downstream endpoints on arm fails because Linux'
PCIe hotplug driver doesn't like the QEMU provided LNKSTA:
pcieport :08:01.0: pciehp: Slot(2): Card present
pcieport :08:01.0: pciehp: Slot(2): Link Up
pcieport :08:01.0: pciehp: Slot(2): Cannot train link: status 0
On 11/11/24 11:55, Thomas Huth wrote:
Let's make it clear that s390x can also boot from virtio-net, to avoid
that people think that s390x can only boot from disk devices.
Reported-by: Boris Fiuczynski
Signed-off-by: Thomas Huth
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docs/system/bootindex.rst | 2 +-
1 file changed, 1 inserti
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