Re: [PATCH 0/2] chardev/char-mux: tweak mux bitset operations

Hi Roman, Reviewed-by Clément Mathieu--Drif Thanks! On 02/11/2024 12:07, Roman Penyaev wrote: Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe. Patchset twe

Re: [PATCH] UI/GTK: full-screen after wait for hiding of tabs and menu_bar

Hi On Sat, Nov 2, 2024 at 8:05 AM Edmund Raile via wrote: > Wait for hiding of GTK notebook tabs and GTK menu_bar before entering > full-screen due to asynchronous nature of GTK. > > prevent: > * full-screen window overlap onto monitor below > * black bar on top of full-screen guest display >

Re: [PATCH 0/2] chardev/char-mux: tweak mux bitset operations

Hi On Sat, Nov 2, 2024 at 3:11 PM Roman Penyaev wrote: > Patchset tweaks bitset operations by changing a constant to unsigned > long, introduces a static compile check and simplifies bitset operations. > > Roman Penyaev (2): > chardev/char-mux: shift unsigned long to avoid 32-bit overflow >

Re: [PATCH] hw/usb: Use __attribute__((packed)) vs __packed

On 01/11/2024 22.17, Roque Arcudia Hernandez wrote: __packed is non standard and is not present in clang-cl. __attribute__((packed)) has the same semantics. Signed-off-by: Erwin Jansen Signed-off-by: Roque Arcudia Hernandez --- include/hw/usb/dwc2-regs.h | 2 +- 1 file changed, 1 insertion(

Re: [PATCH v4 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation

On 04/11/2024 03:49, Yi Liu wrote: > Caution: External email. Do not open attachments or click links, unless > this email comes from a known sender and you know the content is safe. > > > On 2024/9/30 17:26, Zhenzhong Duan wrote: >> Per spec 6.5.2.4, PADID-selective PASID-based iotlb invalidat

Re: [PATCH v4 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation

On 2024/11/4 11:38, Duan, Zhenzhong wrote: -Original Message- From: Liu, Yi L Sent: Monday, November 4, 2024 10:51 AM Subject: Re: [PATCH v4 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation On 2024/9/30 17:26, Zhenzhong Duan wrote: According to spec, Page-Selective-with

Re: [PATCH v4 14/17] intel_iommu: Set default aw_bits to 48 in scalable modern mode

On 2024/11/4 11:19, Duan, Zhenzhong wrote: -Original Message- From: Liu, Yi L Sent: Monday, November 4, 2024 11:16 AM Subject: Re: [PATCH v4 14/17] intel_iommu: Set default aw_bits to 48 in scalable modern mode On 2024/9/30 17:26, Zhenzhong Duan wrote: According to VTD spec, stage-1

Re: [PATCH v4 15/17] intel_iommu: Introduce a property x-fls for scalable modern mode

On 2024/11/4 14:25, Duan, Zhenzhong wrote: -Original Message- From: Liu, Yi L Sent: Monday, November 4, 2024 12:25 PM Subject: Re: [PATCH v4 15/17] intel_iommu: Introduce a property x-fls for scalable modern mode On 2024/9/30 17:26, Zhenzhong Duan wrote: Intel VT-d 3.0 introduces sc

Re: [PATCH v3 15/17] intel_iommu: Modify x-scalable-mode to be string option to expose scalable modern mode

On 04/11/2024 04:24, Yi Liu wrote: > Caution: External email. Do not open attachments or click links, > unless this email comes from a known sender and you know the content > is safe. > > > On 2024/9/29 10:44, Duan, Zhenzhong wrote >>> >>> A question here: >>> >>> Are there any other major featu

Re: [PATCH v4 10/17] intel_iommu: Process PASID-based iotlb invalidation

On 2024/11/4 13:40, Duan, Zhenzhong wrote: -Original Message- From: Liu, Yi L Sent: Monday, November 4, 2024 10:51 AM Subject: Re: [PATCH v4 10/17] intel_iommu: Process PASID-based iotlb invalidation On 2024/9/30 17:26, Zhenzhong Duan wrote: PASID-based iotlb (piotlb) is used during

Re: [PATCH v4 06/17] intel_iommu: Implement stage-1 translation

On 2024/11/4 11:05, Duan, Zhenzhong wrote: -Original Message- From: Liu, Yi L Sent: Sunday, November 3, 2024 10:22 PM Subject: Re: [PATCH v4 06/17] intel_iommu: Implement stage-1 translation On 2024/9/30 17:26, Zhenzhong Duan wrote: From: Yi Liu This adds stage-1 page table walkin

Re: [PATCH v4 16/17] intel_iommu: Introduce a property to control FS1GP cap bit setting

On 2024/9/30 17:26, Zhenzhong Duan wrote: This gives user flexibility to turn off FS1GP for debug purpose. It is also useful for future nesting feature. When host IOMMU doesn't support FS1GP but vIOMMU does, nested page table on host side works after turn FS1GP off in vIOMMU. s/turn/turning R

[PATCH v5 0/3] TPM TIS SPI Support

*** BLURB HERE *** Version 5 summary: 1/3 tpm/tpm_tis_spi: Support TPM for SPI - removed DEFINE_PROP_UINT32("irq", TPMStateSPI, tpm_state.irq_num, 0) from tpm_tis_spi_properties - In tpm.rst document, under section 'The QEMU TPM emulator device', moved the 'P

[PATCH v5 1/3] tpm/tpm_tis_spi: Support TPM for SPI (Serial Peripheral Interface)

Implement support for TPM via SPI interface. The SPI bus master is provided by PowerNV SPI device which is an SSI peripheral. It can uses the tpm_emulator driver backend with the external swtpm. Although the implementation is endian neutral, the SPI bus master provider, pnv_spi.c is only supported

[PATCH v5 3/3] tests/qtest/tpm: add unit test to tis-spi

Add qtest cases to exercise main TPM functionality The TPM device emulation is provided by swtpm, which is TCG TPM 2.0, and TCG TPM TIS compliant. See https://trustedcomputinggroup.org/wp-content/uploads/TCG_PC_Client_Platform_TPM_Profile_PTP_2.0_r1.03_v22.pdf https://trustedcomputinggroup.org/wp-c

[PATCH v5 2/3] tpm/tpm_tis_spi: activation for the PowerNV machines

The addition to ppc/Kconfig is for building this into the qemu-system-ppc64 binary. The enablement requires the following command line argument: -device tpm-tis-spi,tpmdev=tpm0,bus=pnv-spi-bus.4 Signed-off-by: dan tan --- hw/ppc/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/pp

[PATCH v3 4/5] hw/loongarch/virt: Update the ACPI table for hotplug cpu

On LoongArch virt machine, ACPI GED hardware is used for CPU hotplug handler, here CPU hotplug support feature is added based on GED handler, also CPU scan and reject method is added about CPU device in DSDT table. Co-developed-by: Xianglai Li Signed-off-by: Bibo Mao --- hw/loongarch/Kconfig

[PATCH v3 1/5] hw/loongarch/virt: Add CPU topology support

Add topological relationship for Loongarch VCPU and initialize topology member variables, the topo information includes socket-id, core-id and thread-id. For cold-plug CPUs, its topo information is calculated from physical cpuid, and for hot-cpu CPUs its physical cpuid is calculated from topo infor

[PATCH v3 3/5] hw/loongarch/virt: Add generic function to init interrupt pin of CPU

Here generic function virt_init_cpu_irq() is added to init interrupt pin of CPU object, IPI and extioi interrupt controllers are connected to interrupt pin of CPU object. The generic function can be used to both cold-plug and hot-plug CPUs. Signed-off-by: Bibo Mao --- hw/loongarch/virt.c | 76 +

[PATCH v3 2/5] hw/loongarch/virt: Implement cpu plug interface

Add cpu hotplug interface, however cpu hotplug feature is still disabled for the machine. When machine is on, all created vCPUs go through hotplug interface, and there is no remaining vCPU which can be hot-added after power on. Co-developed-by: Xianglai Li Signed-off-by: Bibo Mao --- hw/loongar

[PATCH v3 0/5] hw/loongarch/virt: Add cpu hotplug support

LoongArch cpu hotplug is based on ACPI GED device, there is a little change about ipi and extioi device, the value of num-cpu property is maximum cpu number rather than present cpu number. It can be verified with qemu command: qemu-system-loongarch64 -smp 2,maxcpus=16,sockets=4,cores=4,threads=1

[PATCH v3 5/5] hw/loongarch/virt: Enable cpu hotplug feature on virt machine

On virt machine, enable CPU hotplug feature has_hotpluggable_cpus. For hot-added CPUs after power on, interrupt pin of extioi and ipi interrupt controller need connect to pins of new CPU. Also change num-cpu property of extioi and ipi from smp.cpus to smp.max_cpus Co-developed-by: Xianglai Li Si

RE: [PATCH v4 15/17] intel_iommu: Introduce a property x-fls for scalable modern mode

>-Original Message- >From: Liu, Yi L >Sent: Monday, November 4, 2024 12:25 PM >Subject: Re: [PATCH v4 15/17] intel_iommu: Introduce a property x-fls for >scalable modern mode > >On 2024/9/30 17:26, Zhenzhong Duan wrote: >> Intel VT-d 3.0 introduces scalable mode, and it has a bunch of ca

Re: [QEMU PATCH v9] xen/passthrough: use gsi to map pirq when dom0 is PVH

On 2024/11/1 21:09, Stewart Hildebrand wrote: > On 10/24/24 05:06, Jiqian Chen wrote: >> diff --git a/hw/xen/xen_pt.c b/hw/xen/xen_pt.c >> index 3635d1b39f79..5b10d501d566 100644 >> --- a/hw/xen/xen_pt.c >> +++ b/hw/xen/xen_pt.c >> @@ -766,6 +766,50 @@ static void xen_pt_destroy(PCIDevice *d) { >>

Re: [PATCH-for-9.1 v2 0/4] hw/ssi/pnv_spi: Fixes Coverity CID 1558831

On Thu Aug 8, 2024 at 6:28 AM AEST, Philippe Mathieu-Daudé wrote: > v2: > - Cover PowerNV SSI in MAINTAINERS > - Use GLib API in pnv_spi_xfer_buffer_free() > - Simplify returning early > > Supersedes: <20240806134829.351703-3-chalapath...@linux.ibm.com> > > Chalapathi V (1): > hw/ssi/pnv_spi: Fix

Re: [PATCH v4] hw/ppc: Implement -dtb support for PowerNV

On 03/11/24 17:04, Nicholas Piggin wrote: On Tue Aug 20, 2024 at 8:30 PM AEST, Aditya Gupta wrote: Currently any device tree passed with -dtb option in QEMU, was ignored by the PowerNV code. Read and pass the passed -dtb to the kernel, thus enabling easier debugging with custom DTBs. The exis

RE: [PATCH v4 11/17] intel_iommu: Add an internal API to find an address space with PASID

>-Original Message- >From: Liu, Yi L >Sent: Monday, November 4, 2024 10:51 AM >Subject: Re: [PATCH v4 11/17] intel_iommu: Add an internal API to find an >address >space with PASID > >On 2024/9/30 17:26, Zhenzhong Duan wrote: >> From: Clément Mathieu--Drif >> >> This will be used to imp

RE: [PATCH v4 10/17] intel_iommu: Process PASID-based iotlb invalidation

>-Original Message- >From: Liu, Yi L >Sent: Monday, November 4, 2024 10:51 AM >Subject: Re: [PATCH v4 10/17] intel_iommu: Process PASID-based iotlb >invalidation > >On 2024/9/30 17:26, Zhenzhong Duan wrote: >> PASID-based iotlb (piotlb) is used during walking Intel >> VT-d stage-1 page

Re: [PATCH v17 02/14] hw/ppc/spapr_pci: Do not create DT for disabled PCI device

On 10/28/24 11:28 AM, Akihiko Odaki wrote: On 2024/10/28 12:08, Shivaprasad G Bhat wrote: On 10/22/24 2:06 PM, Akihiko Odaki wrote: Disabled means it is a disabled SR-IOV VF and hidden from the guest. Do not create DT when starting the system and also keep the disabled PCI device not linke

Re: [PATCH v4 15/17] intel_iommu: Introduce a property x-fls for scalable modern mode

On 2024/9/30 17:26, Zhenzhong Duan wrote: Intel VT-d 3.0 introduces scalable mode, and it has a bunch of capabilities related to scalable mode translation, thus there are multiple combinations. This vIOMMU implementation wants to simplify it with a new property "x-fls". When enabled in scalable

RE: [PATCH v4 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation

>-Original Message- >From: Liu, Yi L >Sent: Monday, November 4, 2024 10:51 AM >Subject: Re: [PATCH v4 09/17] intel_iommu: Flush stage-1 cache in iotlb >invalidation > >On 2024/9/30 17:26, Zhenzhong Duan wrote: >> According to spec, Page-Selective-within-Domain Invalidation (11b): >> >> 1

[PATCH v2 0/3] Introduce a new Write Protected pin inverted property

change from v1: 1. Support RTC for AST2700. 2. Support SDHCI write protected pin inverted for AST2500 and AST2600. 3. Introduce Capabilities Register 2 for SD slot 0 and 1. 4. Support create flash devices via command line for AST1030. change from v2: replace wp-invert with wp-inverted and fix revi

[PATCH v2 3/3] hw/arm/aspeed: Invert sdhci write protected pin for AST2600 and AST2500 EVBs

The Write Protect pin of SDHCI model is default active low to match the SDHCI spec. So, write enable the bit 19 should be 1 and write protected the bit 19 should be 0 at the Present State Register (0x24). According to the design of AST2500 and AST2600 EVBs, the Write Protected pin is active high b

[PATCH v2 1/3] hw/sd/sdhci: Fix coding style

Fix coding style issues from checkpatch.pl Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- hw/sd/sdhci.c | 64 +-- 1 file changed, 42 insertions(+), 22 deletions(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index ed01499391..db7d54715

[PATCH v2 2/3] hw/sd/sdhci: Introduce a new Write Protected pin inverted property

The Write Protect pin of SDHCI model is default active low to match the SDHCI spec. So, write enable the bit 19 should be 1 and write protected the bit 19 should be 0 at the Present State Register (0x24). However, some boards are design Write Protected pin active high. In other words, write enable

Re: [PATCH v3 15/17] intel_iommu: Modify x-scalable-mode to be string option to expose scalable modern mode

On 2024/9/29 10:44, Duan, Zhenzhong wrote A question here: Are there any other major features that are still lacking for scalable mode? If not, maybe we can get rid of the "x" prefix? We don't support stage-1 and stage-2 coexist emulation and nested translation emulation through stage-1 and

RE: [PATCH v4 14/17] intel_iommu: Set default aw_bits to 48 in scalable modern mode

>-Original Message- >From: Liu, Yi L >Sent: Monday, November 4, 2024 11:16 AM >Subject: Re: [PATCH v4 14/17] intel_iommu: Set default aw_bits to 48 in >scalable >modern mode > >On 2024/9/30 17:26, Zhenzhong Duan wrote: >> According to VTD spec, stage-1 page table could support 4-level a

Re: [PATCH v4 14/17] intel_iommu: Set default aw_bits to 48 in scalable modern mode

On 2024/9/30 17:26, Zhenzhong Duan wrote: According to VTD spec, stage-1 page table could support 4-level and 5-level paging. However, 5-level paging translation emulation is unsupported yet. That means the only supported value for aw_bits is 48. So default aw_bits to 48 in scalable modern mode

RE: [PATCH v4 06/17] intel_iommu: Implement stage-1 translation

>-Original Message- >From: Liu, Yi L >Sent: Sunday, November 3, 2024 10:22 PM >Subject: Re: [PATCH v4 06/17] intel_iommu: Implement stage-1 translation > >On 2024/9/30 17:26, Zhenzhong Duan wrote: >> From: Yi Liu >> >> This adds stage-1 page table walking to support stage-1 only >> tran

Re: [PATCH v4 13/17] intel_iommu: piotlb invalidation should notify unmap

On 2024/9/30 17:26, Zhenzhong Duan wrote: This is used by some emulated devices which caches address translation result. When piotlb invalidation issued in guest, those caches should be refreshed. For device that does not implement ATS capability or disable it but still caches the translation re

Re: [PATCH v4 11/17] intel_iommu: Add an internal API to find an address space with PASID

On 2024/9/30 17:26, Zhenzhong Duan wrote: From: Clément Mathieu--Drif This will be used to implement the device IOTLB invalidation Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan Acked-by: Jason Wang --- hw/i386/intel_iommu.c | 39 ---

Re: [PATCH v4 12/17] intel_iommu: Add support for PASID-based device IOTLB invalidation

On 2024/9/30 17:26, Zhenzhong Duan wrote: From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 11 hw/i386/intel_iommu.c | 50 ++ 2 files changed, 61 insertions

Re: [PATCH v4 10/17] intel_iommu: Process PASID-based iotlb invalidation

On 2024/9/30 17:26, Zhenzhong Duan wrote: PASID-based iotlb (piotlb) is used during walking Intel VT-d stage-1 page table. This emulates the stage-1 page table iotlb invalidation requested by a PASID-based IOTLB Invalidate Descriptor (P_IOTLB). Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Du

Re: [PATCH v4 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation

On 2024/9/30 17:26, Zhenzhong Duan wrote: According to spec, Page-Selective-within-Domain Invalidation (11b): 1. IOTLB entries caching second-stage mappings (PGTT=010b) or pass-through (PGTT=100b) mappings associated with the specified domain-id and the input-address range are invalidated. 2. IO

Re: [PATCH v4 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation

On 2024/9/30 17:26, Zhenzhong Duan wrote: Per spec 6.5.2.4, PADID-selective PASID-based iotlb invalidation will flush stage-2 iotlb entries with matching domain id and pasid. Also, call out it's per table Table 21. PASID-based-IOTLB Invalidation of VT-d spec 4.1. With scalable modern mode int

Re: [PATCH v4 08/17] intel_iommu: Set accessed and dirty bits during first stage translation

On 2024/9/30 17:26, Zhenzhong Duan wrote: From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 3 +++ hw/i386/intel_iommu.c | 25 - 2 files changed, 27 insertions(+), 1 deletio

Re: [PATCH v4 1/3] tpm/tpm_tis_spi: Support TPM for SPI (Serial Peripheral Interface)

On 2024-11-02 09:19, Stefan Berger wrote: On 11/1/24 4:27 PM, dan tan wrote: Implement support for TPM via SPI interface. The SPI bus master is provided by PowerNV SPI device which is an SSI peripheral. It can uses the tpm_emulator driver backend with the external swtpm. Although the implementa

RE: [SPAM] [PATCH v1 0/8] Support RTC for AST2700

Hi Cedric, > Subject: Re: [SPAM] [PATCH v1 0/8] Support RTC for AST2700 > > On 10/29/24 10:17, Jamin Lin wrote: > > change from v1: > > 1. Support RTC for AST2700. > > 2. Support SDHCI write protected pin inverted for AST2500 and AST2600. > > 3. Introduce Capabilities Register 2 for SD slot 0 and

[PULL 25/67] ppc/spapr: remove deprecated machine pseries-2.9

From: Harsh Prateek Bora Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.9 specific code with this patch for now. While at it, also remove the pre-2.10 migration hacks which now become obsolete. Suggested

[PULL 64/67] hw/ppc: Consolidate ppc440 initial mapping creation functions

From: BALATON Zoltan Add a utility function and use it to replace very similar create_initial_mapping functions in 440 based machines. Signed-off-by: BALATON Zoltan Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Signed-off-by: Nicholas Piggin --- hw/ppc/ppc440_bamboo.c | 28 +++

[PULL 21/67] ppc/spapr: remove deprecated machine pseries-2.5

From: Harsh Prateek Bora Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.5 specific code with this patch for now. Also drop sPAPRMachineClass::use_ohci_by_default which is now useless. Suggested-by: Cédri

[PULL 24/67] ppc/spapr: remove deprecated machine pseries-2.8

From: Harsh Prateek Bora Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.8 specific code with this patch for now. Suggested-by: Cédric Le Goater Reviewed-by: Cédric Le Goater Signed-off-by: Harsh Prateek

[PULL 35/67] target/ppc: use locally stored msr and avoid indirect access

From: Harsh Prateek Bora hreg_compute_hflags_value already stores msr locally to be used in most of the logic in the routine however some instances are still using env->msr which is unnecessary. Use locally stored value as available. Reviewed-by: Nicholas Piggin Reviewed-by: BALATON Zoltan Sig

[PULL 44/67] spapr: nested: Add support for DPDES SPR in GSB for TCG L0

From: Amit Machhiwal The DPDES support for doorbell emulation and handling for KVM on PAPR guests was added in Linux via [1]. Subsequently, a new GSB (Guest State Buffer) element for DPDES was added in Linux; the same has been missing in TCG L0 implementation. Add support for DPDES register's API

[PULL 60/67] pnv/xive2: TIMA support for 8-byte OS context push for PHYP

From: Glenn Miles PHYP uses 8-byte writes to the 2nd doubleword of the OS context line when dispatching an OS level virtual processor. This support was not used by OPAL/Linux and so was never added. Without this support, the XIVE code doesn't notice that a new context is being pushed and fails

[PULL 65/67] MAINTAINERS: Remove myself from the PowerNV machines

From: Cédric Le Goater It's been an amazing experience working on PowerNV systems all these years. Now it's time for IBM to take the lead on the QEMU machine and shape its future. I'm stepping back as the maintainer of PowerNV. Cc: Nicholas Piggin Cc: Frédéric Barrat Signed-off-by: Cédric Le G

[PULL 46/67] hw/ppc: Implement -dtb support for PowerNV

From: Aditya Gupta Currently any device tree passed with -dtb option in QEMU, was ignored by the PowerNV code. Read and pass the passed -dtb to the kernel, thus enabling easier debugging with custom DTBs. The existing behaviour when -dtb is 'not' passed, is preserved as-is. But when a '-dtb' i

[PULL 12/67] hw/ssi/pnv_spi: Match _xfer_buffer_free() with _xfer_buffer_new()

From: Philippe Mathieu-Daudé pnv_spi_xfer_buffer_new() allocates %payload using g_malloc0(), and pnv_spi_xfer_buffer_write_ptr() allocates %payload->data using g_realloc(). Use the API equivalent g_free() to release the buffers. Cc: qemu-sta...@nongnu.org Signed-off-by: Philippe Mathieu-Daudé R

[PULL 58/67] pnv/xive: Add special handling for pool targets

From: Glenn Miles Hypervisor "pool" targets do not get their own interrupt line and instead must share an interrupt line with the hypervisor "physical" targets. This also means that the pool ring must use some of the registers from the physical ring in the TIMA. Specifically, the NSR, PIPR and C

[PULL 09/67] target/ppc: Fix VRMA to not check virtual page class key protection

Hash virtual real mode addressing is defined by the architecture to not perform virtual page class key protection checks. Reviewed-by: Richard Henderson Signed-off-by: Nicholas Piggin --- target/ppc/mmu-hash64.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/

[PULL 39/67] target/ppc: optimize p8 exception handling routines

From: Harsh Prateek Bora Most of the p8 exception handling accesses env->pending_interrupts and env->spr[SPR_LPCR] at multiple places. Passing it directly as local variables simplifies the code and avoids multiple indirect accesses. Reviewed-by: Nicholas Piggin Signed-off-by: Harsh Prateek Bora

[PULL 16/67] hw/ppc: fix decrementer with BookE timers

From: Clément Chigot The BookE decrementer stops at 0, meaning that it won't decremented towards "negative" values. However, the current logic is inverted: decr is updated solely when the resulting value would be negative. Signed-off-by: Clément Chigot Fixes: 8e0a5ac87800 ("hw/ppc: Avoid decrem

[PULL 56/67] ppc/xive2: Change context/ring specific functions to be generic

From: Michael Kowal Some the functions that have been created are specific to a ring or context. Some of these same functions are being changed to operate on any ring/context. This will simplify the next patch sets that are adding additional ring/context operations. Signed-off-by: Michael Kow

[PULL 55/67] ppc/xive2: Support "Pull Thread Context to Register" operation

From: Glenn Miles Adds support for single byte read of offset 0x838 of the TIMA address space. According to the XIVE2 Specification, this causes the hardware to atomically: 1. Read the number of bytes requested (lbz or lhz are supported). 2. Reset the valid bit of the thread context. 3. Re

[PULL 52/67] ppc/xive2: Dump more NVP state with 'info pic'

From: Frederic Barrat The 'PGoFirst' field of a Notify Virtual Processor tells if the NVP belongs to a VP group. Also, print the Reporting Cache Line address, if defined. Signed-off-by: Frederic Barrat Signed-off-by: Michael Kowal Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin

[PULL 33/67] target/ppc: Add Power11 DD2.0 processor

From: Aditya Gupta Add CPU target code to add support for new Power11 Processor. Power11 core is same as Power10, hence reuse functions defined for Power10. Reviewed-by: Nicholas Piggin Signed-off-by: Aditya Gupta Tested-by: Amit Machhiwal Signed-off-by: Nicholas Piggin --- target/ppc/comp

[PULL 67/67] MAINTAINERS: Remove myself as reviewer

From: David Gibson I've now well and truly moved on from ppc and qemu maintenance. I'm occupied with other things and am pretty much just ignoring mails on these topics I'm CCed on. Time to remove myself. I'm still listed as a reviewer for Device Tree, I'll keep this for now, since I do have s

[PULL 62/67] tests/qtest: Add XIVE tests for the powernv10 machine

From: Frederic Barrat These XIVE tests include: - General interrupt IRQ tests that: - enable and trigger an interrupt - acknowledge the interrupt - end of interrupt processing - Test the Pull Thread Context to Odd Thread Reporting Line - Test the different cache flush inject and queue sync

[PULL 03/67] ppc/pnv: Fix LPC serirq routing calculation

The serirq routing table is split over two registers, the calculation for the high irqs in the second register did not subtract the irq offset. This was spotted by Coverity as a shift-by-negative. Fix this and change the open-coded shifting and masking to use extract32() function so it's less error

[PULL 57/67] ppc/xive2: Support "Pull Thread Context to Odd Thread Reporting Line"

From: Glenn Miles Adds support for single byte writes to offset 0xC38 of the TIMA address space. When this offset is written to, the hardware disables the thread context and copies the current state information to the odd cache line of the pair specified by the NVT structure indexed by the THREA

[PULL 23/67] ppc/spapr: remove deprecated machine pseries-2.7

From: Harsh Prateek Bora Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.7 specific code with this patch for now. While at it, also remove pre-2.8-migration and pci/mmio hacks introduced for backward compa

[PULL 20/67] ppc/spapr: remove deprecated machine pseries-2.4

From: Harsh Prateek Bora Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.4 specific code with this patch for now. While at it, also remove SpaprMachineClass::dr_lmb_enabled which is now turned useless. Su

[PULL 30/67] target/ppc: Reduce code duplication across Power9/10 init code

From: Harsh Prateek Bora Power9/10 initialization code consists of a lot of logical OR of various flag bits as supported by respective Power platform during its initialization, most of which is duplicated and only selected bits are added or removed as needed with each new platform support being a

[PULL 28/67] ppc/spapr: remove deprecated machine pseries-2.12-sxxm

From: Harsh Prateek Bora Commit 0cac0f1b964 marked pseries-2.12 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.12-sxxm specific code with this patch. Suggested-by: Cédric Le Goater Signed-off-by: Harsh Prateek Bora Reviewed-by: Cédric Le Goater Signed-off-

[PULL 66/67] MAINTAINERS: Remove myself from XIVE

From: Cédric Le Goater Working on XIVE has been one of the most complex and fascinating experiences for me. It's been a real journey, and now it's time for IBM to take over and guide its future. I'm stepping back as the maintainer of XIVE. Cc: Michael Kowal Cc: Nicholas Piggin Cc: Frédéric Bar

[PULL 63/67] hw/ppc: Consolidate e500 initial mapping creation functions

From: BALATON Zoltan Add booke206_set_tlb() utility function and use it to replace very similar create_initial_mapping functions in e500 machines. Signed-off-by: BALATON Zoltan Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Signed-off-by: Nicholas Piggin --- hw/ppc/e500.c

[PULL 32/67] target/ppc: Fix regression due to Power10 and Power11 having same PCR

From: Aditya Gupta Power11 has the same PCR (Processor Compatibility Register) value, as Power10. Due to this, QEMU considers Power11 as a valid compat-mode for Power10, ie. earlier it was possible to run QEMU with '-M pseries,max-compat-mode=power11 --cpu power10' Same PCR also introduced a re

[PULL 26/67] ppc/spapr: remove deprecated machine pseries-2.10

From: Harsh Prateek Bora Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.10 specific code with this patch for now. Suggested-by: Cédric Le Goater Reviewed-by: Cédric Le Goater Signed-off-by: Harsh Pratee

[PULL 40/67] target/ppc: optimize p7 exception handling routines

From: Harsh Prateek Bora Like p8 and p9, simplifying p7 exception handling rotuines to avoid un-necessary multiple indirect accesses to env->pending_interrupts and env->spr[SPR_LPCR]. Reviewed-by: Nicholas Piggin Signed-off-by: Harsh Prateek Bora Signed-off-by: Nicholas Piggin --- target/ppc

[PULL 48/67] pnv/xive: TIMA patch sets pre-req alignment and formatting changes

From: Michael Kowal Making some pre-requisite alignment changes ahead of the following patch sets. Making these changes now will ease the review of the patch sets. Checkpatch wants the closing comment '*/' on a separate line, unless it is on the same line as the starting comment '/*'. There ar

[PULL 53/67] ppc/xive2: Dump the VP-group and crowd tables with 'info pic'

From: Frederic Barrat The 'info pic' HMP command dumps the state of the interrupt controller. Add the dump of the NVG and NVC tables to its output to ease debug. Signed-off-by: Frederic Barrat Signed-off-by: Michael Kowal Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- hw/i

[PULL 34/67] ppc/pseries: Add Power11 cpu type

From: Aditya Gupta Add sPAPR CPU Core definition for Power11 Reviewed-by: Harsh Prateek Bora Reviewed-by: Nicholas Piggin Signed-off-by: Aditya Gupta Tested-by: Amit Machhiwal Signed-off-by: Nicholas Piggin --- docs/system/ppc/pseries.rst | 17 + hw/ppc/spapr_cpu_core.c

[PULL 54/67] ppc/xive2: Allow 1-byte write of Target field in TIMA

From: Glenn Miles When running PowerVM, the console is littered with XIVE traces regarding invalid writes to TIMA address 0x100b6 due to a lack of support for writes to the "TARGET" field which was added for XIVE GEN2. To fix this, we add special op support for 1-byte writes to this field. Sign

[PULL 07/67] target/ppc: Fix doorbell delivery to threads in powersave

Doorbell exceptions are not not cleared when they cause a wake from powersave state, only when they take the corresponding interrupt. The sreset-on-wake logic must avoid clearing the interrupt in this case. Reviewed-by: Richard Henderson Signed-off-by: Nicholas Piggin --- target/ppc/excp_helper

[PULL 47/67] ppc/xive: Fix ESB length overflow on 32-bit hosts

The length of this region can be > 32-bits, which overflows size_t on 32-bit hosts. Change to uint64_t. Signed-off-by: Nicholas Piggin --- hw/intc/spapr_xive_kvm.c | 4 ++-- hw/intc/xive.c | 2 +- include/hw/ppc/xive.h| 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff -

[PULL 49/67] pnv/xive2: Define OGEN field in the TIMA

From: Frederic Barrat The OGEN field at offset 0x1F is a new field for Gen2 TIMA. This patch defines it. Signed-off-by: Frederic Barrat Signed-off-by: Michael Kowal Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- hw/intc/xive.c | 4 include/hw/ppc/xive_regs

[PULL 45/67] spapr: nested: Add Power11 capability support for Nested PAPR guests in TCG L0

From: Amit Machhiwal The Power11 architected and raw mode support in Linux was merged via [1] and the corresponding support in QEMU is waiting to be added by [2] which in V6 currently. Add the Power11 capabilities and the required handling in TCG L0 implementation of the "Nested PAPR API". Note

[PULL 59/67] pnv/xive: Update PIPR when updating CPPR

From: Glenn Miles Current code was updating the PIPR inside the xive_tctx_accept() function instead of the xive_tctx_set_cppr function, which is where the HW would have it updated. Moved the update to the xive_tctx_set_cppr function which required additional support for pool interrupts. Fixes:

[PULL 31/67] target/ppc: Introduce 'PowerPCCPUClass::spapr_logical_pvr'

From: Aditya Gupta Introduce 'PnvChipClass::spapr_logical_pvr' to know corresponding logical PVR of a PowerPC CPU. This helps to have a one-to-one mapping between PVR and logical PVR for a CPU, and used in a later commit to handle cases where PCR of two generations of Power chip is same, which ca

[PULL 61/67] pnv/xive2: TIMA CI ops using alternative offsets or byte lengths

From: Michael Kowal Some of the TIMA Special CI operations perform the same operation at alternative byte offsets and lengths. The following xive2_tm_opertions[] table entries are missing when they exist for other offsets/sizes and have been added: - lwz@0x810 Pull/Invalidate O/S Context to regi

[PULL 10/67] ppc/pnv: ADU fix possible buffer overrun with invalid size

The ADU LPC transfer-size field is 7 bits, but the supported sizes for LPC access via ADU appear to be 1, 2, 4, 8. The data buffer could overrun if firmware set an invalid size field, so add checks to reject them with a message. Cc: qemu-sta...@nongnu.org Reported-by: Cédric Le Goater Resolves: C

[PULL 41/67] target/ppc: simplify var usage in ppc_next_unmasked_interrupt

From: Harsh Prateek Bora As previously done for arch specific handlers, simplify var usage in ppc_next_unmasked_interrupt by caching the env->pending_interrupts and env->spr[SPR_LPCR] in local vars and using it later at multiple places. Reviewed-by: Nicholas Piggin Signed-off-by: Harsh Prateek

[PULL 43/67] target/ppc: reduce duplicate code between init_proc_POWER{9, 10}

From: Harsh Prateek Bora Historically, the registration of sprs have been inherited alongwith every new Power arch support being added leading to a lot of code duplication. It's time to do necessary cleanups now to avoid further duplication with newer arch support being added. Signed-off-by: Har

[PULL 50/67] ppc/xive2: Support TIMA "Pull OS Context to Odd Thread Reporting Line"

From: Frederic Barrat Adds support for single byte writes to offset 0xC18 of the TIMA address space. When this offset is written to, the hardware disables the OS context and copies the current state information to the odd cache line of the pair specified by the NVT structure indexed by the OS CA

[PULL 38/67] target/ppc: optimize p9 exception handling routines

From: Harsh Prateek Bora Currently, p9 exception handling has multiple if-condition checks where it does an indirect access to pending_interrupts and LPCR via env. Pass the values during entry to avoid multiple indirect accesses. Reviewed-by: Nicholas Piggin Signed-off-by: Harsh Prateek Bora S

[PULL 42/67] target/ppc: combine multiple ail checks into one

From: Harsh Prateek Bora ppc_excp_apply_ail has multiple if-checks for ail which is un-necessary. Combine them as appropriate. Reviewed-by: Nicholas Piggin Signed-off-by: Harsh Prateek Bora Signed-off-by: Nicholas Piggin --- target/ppc/excp_helper.c | 10 ++ 1 file changed, 2 inserti

[PULL 37/67] target/ppc: optimize hreg_compute_pmu_hflags_value

From: Harsh Prateek Bora The second if-condition can be true only if the first one above is true. Enclose the latter into the former to avoid un-necessary check if first condition fails. Reviewed-by: BALATON Zoltan Reviewed-by: Nicholas Piggin Signed-off-by: Harsh Prateek Bora Signed-off-by:

[PULL 22/67] ppc/spapr: remove deprecated machine pseries-2.6

From: Harsh Prateek Bora Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.6 specific code with this patch for now. Suggested-by: Cédric Le Goater Reviewed-by: Cédric Le Goater Signed-off-by: Harsh Prateek

[PULL 36/67] target/ppc: optimize hreg_compute_pmu_hflags_value

From: Harsh Prateek Bora Cache env->spr[SPR_POWER_MMCR0] in a local variable as used in multiple conditions to avoid multiple indirect accesses. Reviewed-by: Nicholas Piggin Signed-off-by: Harsh Prateek Bora Signed-off-by: Nicholas Piggin --- target/ppc/helper_regs.c | 9 + 1 file ch

[PULL 51/67] pnv/xive2: Support for "OS LGS Push" TIMA operation

From: Glenn Miles Adds support for single byte writes to offset 0x15 of the TIMA address space. This offset holds the Logical Server Group Size (LGS) field. The field is used to evenly distribute the interrupt load among the members of a group, but is unused in the current implementation so we j

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