Hi,
Many benchmarks have their own build and run system, such as specint, we don’t
want to change their code.
Actually the log maybe structural data such as in json format and may be output
multiple log files with different statistics dimention for one run.
-D can’t satisfy this.
Regard,
Deni
Wait for hiding of GTK notebook tabs and GTK menu_bar before entering
full-screen due to asynchronous nature of GTK.
prevent:
* full-screen window overlap onto monitor below
* black bar on top of full-screen guest display
* misallignment of host-drawn guest cursor and invisible guest cursor
Si
Paolo Bonzini writes:
> Il ven 1 nov 2024, 11:21 Junjie Mao ha scritto:
>
> How about specifying also the exact version in Cargo.toml, e.g.:
>
> [dependencies]
> -proc-macro2 = "1"
> -quote = "1"
> -syn = { version = "2", features = ["extra-traits"] }
> +proc-macro2 = "=1.0.84"
> +quot
If an ESP command is issued in an incorrect mode then an illegal command
interrupt should be generated. Add a new esp_cmd_is_valid() function to
indicate whether the ESP command is valid for the current mode, and if not
then raise the illegal command interrupt.
This fixes WinNT MIPS which issues I
This series contains a few minor tidy-ups along with an implementation of the
logic to only allow ESP commands permitted in the current mode. The motivation
is to fix GitLab issue #2464 which causes Windows NT MIPS to bluescreen on
boot.
Patches 1 to 3 are simple tidy-ups from investigating the is
Whilst working on the previous patch, the existing comment was not enough to
document when the TI command codepath was being used. Update and improve the
comment accordingly.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
This is not needed as it is now handled by the OBJECT_DECLARE_SIMPLE_TYPE()
macro.
Signed-off-by: Mark Cave-Ayland
---
include/hw/scsi/esp.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/hw/scsi/esp.h b/include/hw/scsi/esp.h
index 533d856aa3..c9afcb7cac 100644
--- a/include/hw/sc
Add a new asc_mode property to ESPState which indicates the current mode of
the ESP and update the ESP state machine accordingly.
Bump the vmstate version and include migration logic to ensure that asc_mode
is set to initiator mode such that any commands in progress will always
continue.
Signed-o
Clarify the logic in esp_transfer_data() to ensure that the deferred interrupt
code
can only be triggered for CMD_SEL, CMD_SELATN and CMD_TI commands. This should
already
be the case, but make it explicit to ensure the logic isn't triggered
unexpectedly.
Signed-off-by: Mark Cave-Ayland
---
hw
The bus parameter in the macro PCI_BUILD_BDF is not surrounded by
parenthesis. This can create a compile error when warnings are
treated as errors or can potentially create runtime errors due to the
operator precedence.
For instance:
file.c:x:32: error: suggest parentheses around '-' inside '<<'
This contains a series of small compiler fixes to enable the compilation
of qemu using clang-cl.
It mainly involves adding some missing header files and updating #ifdefs
to handle clang-cl specific things.
Signed-off-by: Erwin Jansen
Signed-off-by: Roque Arcudia Hernandez
---
include/qemu/comp
On 11/1/24 14:17, Roque Arcudia Hernandez wrote:
__packed is non standard and is not present in clang-cl.
__attribute__((packed)) has the same semantics.
Signed-off-by: Erwin Jansen
Signed-off-by: Roque Arcudia Hernandez
---
include/hw/usb/dwc2-regs.h | 2 +-
1 file changed, 1 insertion(+),
__packed is non standard and is not present in clang-cl.
__attribute__((packed)) has the same semantics.
Signed-off-by: Erwin Jansen
Signed-off-by: Roque Arcudia Hernandez
---
include/hw/usb/dwc2-regs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/usb/dwc2-regs
On windows machines the path seperator is '\\' (backslash) which causes
the tracetool generator to output line information in the source code
with the '\\' character. This in turn confuses the compiler, causing
build breaks.
We now will always use posix paths, so the paths will use a '/'
(forward)
On 11/1/24 13:46, Daniel Henrique Barboza wrote:
On 11/1/24 4:23 PM, Tomasz Jeznach wrote:
On Fri, Nov 1, 2024 at 11:49 AM Peter Maydell wrote:
On Fri, 1 Nov 2024 at 18:13, Daniel Henrique Barboza
wrote:
(Ccing Tomasz)
On 11/1/24 2:48 PM, Peter Maydell wrote:
On Fri, 1 Nov 2024 at 17:3
On 11/1/24 4:23 PM, Tomasz Jeznach wrote:
On Fri, Nov 1, 2024 at 11:49 AM Peter Maydell wrote:
On Fri, 1 Nov 2024 at 18:13, Daniel Henrique Barboza
wrote:
(Ccing Tomasz)
On 11/1/24 2:48 PM, Peter Maydell wrote:
On Fri, 1 Nov 2024 at 17:36, Daniel Henrique Barboza
wrote:
On 11/1/24
Convert the next-kbd device from the legacy UI qemu_add_kbd_event_handler()
function to use qemu_input_handler_register().
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/next-kbd.c | 166 ++---
1 file changed, 111 insertions(+), 55 deletions(-)
diff --git a/
The addition to ppc/Kconfig is for building this into the
qemu-system-ppc64 binary. The enablement requires the
following command line argument:
-device tpm-tis-spi,tpmdev=tpm0,bus=pnv-spi-bus.4
Signed-off-by: dan tan
---
hw/ppc/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/pp
*** BLURB HERE ***
Revision 4 summary:
- fold v3 commit 4/5 into 1/5
- fold v3 commit 5/5 into 3/5
Revision 3 summary:
device support:
- moved variable tis_addr from TPMStateSPI struct to local
- added the VM suspend/resume support:
- added vmstate_tpm_tis_spi declaration
Add qtest cases to exercise main TPM locality functionality
The TPM device emulation is provided by swtpm, which is TCG
TPM 2.0, and TCG TPM TIS compliant. See
https://trustedcomputinggroup.org/wp-content/uploads/TCG_PC_Client_Platform_TPM_Profile_PTP_2.0_r1.03_v22.pdf
https://trustedcomputinggroup
Implement support for TPM via SPI interface. The SPI bus master
is provided by PowerNV SPI device which is an SSI peripheral.
It can uses the tpm_emulator driver backend with the external
swtpm.
Although the implementation is endian neutral, the SPI
bus master provider, pnv_spi.c is only supported
Since the last keyboard device has now been converted over to use
qemu_input_handler_register(), the legacy qemu_add_kbd_event_handler() function
is now unused and can be removed.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Alex Bennée
---
include/ui/console.h | 2 --
ui/input-legacy.c| 3
This series converts the next-kbd device to use
qemu_input_handler_register(), and then removes the now-unused legacy
qemu_add_kbd_event_handler() function.
Signed-off-by: Mark Cave-Ayland
v3:
- Rebase onto master
- Use Q_KEY_CODE__MAX for the size of qcode_to_nextkbd_keycode() array
- Fix shi
On Fri, Nov 01, 2024 at 06:35:23PM +, Shameerali Kolothum Thodi wrote:
> > @Shameer,
> > Do you have some update on the pluggable smmuv3 module?
>
> I have a bare minimum prototype code that works with a pluggable smmuv3.
>
> ...
> -device pxb-pcie,id=pcie.1,bus_nr=2,bus=pcie.0 \
> -device pc
On 11/1/24 2:57 PM, dan tan wrote:
*** BLURB HERE ***
Support TPM for SPI (Serial Peripheral Interface)
Revision 3 summary:
device support:
- moved variable tis_addr from TPMStateSPI struct to local
- added the VM suspend/resume support:
- added vmstate_tpm_tis_spi declar
On Fri, Nov 1, 2024 at 11:49 AM Peter Maydell wrote:
>
> On Fri, 1 Nov 2024 at 18:13, Daniel Henrique Barboza
> wrote:
> >
> > (Ccing Tomasz)
> >
> > On 11/1/24 2:48 PM, Peter Maydell wrote:
> > > On Fri, 1 Nov 2024 at 17:36, Daniel Henrique Barboza
> > > wrote:
> > >>
> > >>
> > >>
> > >> On 11
On Thu, 31 Oct 2024 at 17:49, Thomas Huth wrote:
>
> Move the BananaPi tests from tests/avocado/boot_linux_console.py into
> a new file dedicated for Banana Pi tests in the functional framework.
> Update the hash sums of the assets to sha256 along the way and fix the
> broken link for the buildroo
On Fri, 1 Nov 2024 at 18:13, Daniel Henrique Barboza
wrote:
>
> (Ccing Tomasz)
>
> On 11/1/24 2:48 PM, Peter Maydell wrote:
> > On Fri, 1 Nov 2024 at 17:36, Daniel Henrique Barboza
> > wrote:
> >>
> >>
> >>
> >> On 11/1/24 2:08 PM, Pierrick Bouvier wrote:
> >>> Introduced in 0c54ac, "hw/riscv: ad
On 11/1/24 20:13, Dmitry Osipenko wrote:
>> As an aside can mesa build the intel drivers on non-x86 systems as now I
>> could potentially pass my native intel context to my emulated aarch64
>> guests?
> In general it should work. Don't know for sure how well Intel Mesa
> driver works on ARM, suppos
On 01/11/2024 09:26, Thomas Huth wrote:
Am Wed, 30 Oct 2024 09:18:03 +
schrieb Mark Cave-Ayland :
Convert the next-kbd device from the legacy UI qemu_add_kbd_event_handler()
function to use qemu_input_handler_register().
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/next-kbd.c | 158
- removed the function prototypes declaration
- fixed code format to comply with convention
- changed function names and variable names to be the same
as the tpm-tis-i2c test.
- change hard coded numbers to #define's with meaningful
names that are identifiable with spec documentation
Signed-of
The addition to ppc/Kconfig is for building this into the
qemu-system-ppc64 binary. The enablement requires the
following command line argument:
-device tpm-tis-spi,tpmdev=tpm0,bus=pnv-spi-bus.4
Signed-off-by: dan tan
---
hw/ppc/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/pp
- moved variable tis_addr from TPMStateSPI struct to local
- added the VM suspend/resume support:
- added vmstate_tpm_tis_spi declaration
- added tpm_tis_spi_pre_save() function
- fixed trace formatting string
Signed-off-by: dan tan
---
hw/tpm/tpm_tis_spi.c | 50 +
Add qtest cases to exercise main TPM locality functionality
The TPM device emulation is provided by swtpm, which is TCG
TPM 2.0, and TCG TPM TIS compliant. See
https://trustedcomputinggroup.org/wp-content/uploads/TCG_PC_Client_Platform_TPM_Profile_PTP_2.0_r1.03_v22.pdf
https://trustedcomputinggroup
Implement support for TPM via SPI interface. The SPI bus master
is provided by PowerNV SPI device which is an SSI peripheral.
It can uses the tpm_emulator driver backend with the external
swtpm.
Although the implementation is endian neutral, the SPI
bus master provider, pnv_spi.c is only supported
*** BLURB HERE ***
Support TPM for SPI (Serial Peripheral Interface)
Revision 3 summary:
device support:
- moved variable tis_addr from TPMStateSPI struct to local
- added the VM suspend/resume support:
- added vmstate_tpm_tis_spi declaration
- added tpm_tis_spi_pre_save() f
Our implementation of the indexed version of SVE SDOT/UDOT/USDOT got
the calculation of the inner loop terminator wrong. Although we
correctly account for the element size when we calculate the
terminator for the first iteration:
intptr_t segend = MIN(16 / sizeof(TYPED), opr_sz_n);
we don't do
Hi Nicolin,
> -Original Message-
> From: Nicolin Chen
> Sent: Friday, November 1, 2024 4:09 AM
> To: Shameerali Kolothum Thodi
> Cc: Eric Auger ; Mostafa Saleh
> ; qemu-...@nongnu.org; qemu-
> de...@nongnu.org; Peter Maydell ; Jason
> Gunthorpe ; Jean-Philippe Brucker phili...@linaro.
On 11/1/24 20:16, Alex Bennée wrote:
> Also what is the subtlety behind using both stride and bytes_pp in the
> calculation. My naive thought would be:
>
> fb.bytes_pp * ss.r.width == fb.stride
>
> Can anyone enlighten me?
GPUs want image line size to be aligned to a power of 2 value, like 64
On 11/1/24 09:11, Peter Maydell wrote:
When calculating the index into the GIC's GPIO array for per-CPU
interrupts, we have to start with the number of SPIs. The code
currently hard-codes this to 'NUM_IRQS = 256'. However the number of
SPIs is set separately and implicitly by the value of
AS
On 11/1/24 09:11, Peter Maydell wrote:
Use the private peripheral interrupt definitions from bsa.h instead
of defining them locally.
Note that bsa.h defines these values as INTID values, which are all
16 greater than the PPI values that we were previously using. So we
refactor the code to us
Hi Demin,
thanks for your contribution.
On 11/1/24 02:00, demin.han wrote:
Why we need args?
When plugin outputs log files, only binary path can't distinguish multiple
runs if the binary passed with different args.
This is bad for CI using plugin.
Can it be solved simply by encoding this in
(Ccing Tomasz)
On 11/1/24 2:48 PM, Peter Maydell wrote:
On Fri, 1 Nov 2024 at 17:36, Daniel Henrique Barboza
wrote:
On 11/1/24 2:08 PM, Pierrick Bouvier wrote:
Introduced in 0c54ac, "hw/riscv: add RISC-V IOMMU base emulation"
../hw/riscv/riscv-iommu.c:187:17: error: redefinition of '_pext
On 11/1/24 10:35, Daniel Henrique Barboza wrote:
On 11/1/24 2:08 PM, Pierrick Bouvier wrote:
Introduced in 0c54ac, "hw/riscv: add RISC-V IOMMU base emulation"
../hw/riscv/riscv-iommu.c:187:17: error: redefinition of '_pext_u64'
187 | static uint64_t _pext_u64(uint64_t val, uint64_t ext)
On 11/1/24 10:48, Peter Maydell wrote:
On Fri, 1 Nov 2024 at 17:36, Daniel Henrique Barboza
wrote:
On 11/1/24 2:08 PM, Pierrick Bouvier wrote:
Introduced in 0c54ac, "hw/riscv: add RISC-V IOMMU base emulation"
../hw/riscv/riscv-iommu.c:187:17: error: redefinition of '_pext_u64'
187 | s
On Fri, 1 Nov 2024 at 17:36, Daniel Henrique Barboza
wrote:
>
>
>
> On 11/1/24 2:08 PM, Pierrick Bouvier wrote:
> > Introduced in 0c54ac, "hw/riscv: add RISC-V IOMMU base emulation"
> >
> > ../hw/riscv/riscv-iommu.c:187:17: error: redefinition of '_pext_u64'
> >
> >187 | static uint64_t _pext_
Trivial reflow to let the type names breathe.
(I need to add a longer type name.)
Signed-off-by: John Snow
---
tests/qemu-iotests/iotests.py | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/tests/qemu-iotests/iotests.py b/tests/qemu-iotests/iotests.py
index ea48af
On 11/1/24 2:35 PM, Daniel Henrique Barboza wrote:
On 11/1/24 2:08 PM, Pierrick Bouvier wrote:
Introduced in 0c54ac, "hw/riscv: add RISC-V IOMMU base emulation"
../hw/riscv/riscv-iommu.c:187:17: error: redefinition of '_pext_u64'
187 | static uint64_t _pext_u64(uint64_t val, uint64_t e
I have a vague memory that I suggested this base class to Vladimir and
said "Maybe someday it will break, and I'll just fix it then." Guess
that's today.
Fixes various mypy errors in the "make check-tox" python test for at
least Python3.8; seemingly requires a fairly modern mypy and/or Python
base
As of (at least) pylint 3.3.1, this code trips pylint up into believing
we are raising something other than an Exception. We are not: the first
two values may indeed be "None", but the last and final value must by
definition be a SystemExit exception.
Signed-off-by: John Snow
---
python/scripts/
Various python tests in the "check-python-tox" test case on GitLab have
begun failing due to newer package versions. This patch set corrects
those issues and also improves the reliability of local developer tests
which may be using these tooling versions outside of GitLab pinned
version tests.
The
Newest versions of pylint complain about specifically positional
arguments in addition to too many in general. We already disable the
general case, so silence this new warning too.
Signed-off-by: John Snow
---
python/setup.cfg| 1 +
tests/qemu-iotests/pylintrc | 1 +
2 files changed,
On 11/1/24 2:08 PM, Pierrick Bouvier wrote:
Introduced in 0c54ac, "hw/riscv: add RISC-V IOMMU base emulation"
../hw/riscv/riscv-iommu.c:187:17: error: redefinition of '_pext_u64'
187 | static uint64_t _pext_u64(uint64_t val, uint64_t ext)
| ^
D:/a/_temp/msys64/cla
On 10/31/24 10:44, Akihiko Odaki wrote:
> On 2024/10/25 8:33, Dmitry Osipenko wrote:
>> Support asynchronous fencing feature of virglrenderer. It allows Qemu to
>> handle fence as soon as it's signalled instead of periodically polling
>> the fence status. This feature is required for enabling DRM c
Dmitry Osipenko writes:
> On 11/1/24 18:35, Peter Maydell wrote:
>> On Tue, 29 Oct 2024 at 12:11, Alex Bennée wrote:
>>>
>>> From: Robert Beckett
>>>
>>> Support BLOB resources creation, mapping, unmapping and set-scanout by
>>> calling the new stable virglrenderer 0.10 interface. Only enabled
Peter Maydell writes:
> On Tue, 29 Oct 2024 at 12:11, Alex Bennée wrote:
>>
>> From: Robert Beckett
>>
>> Support BLOB resources creation, mapping, unmapping and set-scanout by
>> calling the new stable virglrenderer 0.10 interface. Only enabled when
>> available and via the blob config. E.g. -
On 10/31/24 13:21, Alex Bennée wrote:
> Dmitry Osipenko writes:
>
>> Print out error messages when virgl fence creation fails to aid debugging
>> of the fence-related bugs.
>>
>> Signed-off-by: Dmitry Osipenko
>> ---
>> hw/display/virtio-gpu-virgl.c | 12 +++-
>> 1 file changed, 11 inse
On 10/31/24 13:26, Alex Bennée wrote:
> Dmitry Osipenko writes:
>
>> Add support for DRM native contexts to VirtIO-GPU. DRM context is enabled
>> using a new virtio-gpu-gl device option "drm=on".
>
> I feel like using "drm" is confusing in this context because drm exists
> for the host and guest
Introduced in 0c54ac, "hw/riscv: add RISC-V IOMMU base emulation"
../hw/riscv/riscv-iommu.c:187:17: error: redefinition of '_pext_u64'
187 | static uint64_t _pext_u64(uint64_t val, uint64_t ext)
| ^
D:/a/_temp/msys64/clang64/lib/clang/18/include/bmi2intrin.h:217:1: note:
On 31.10.2024 23:17, Maciej S. Szmigiero wrote:
Hi Avihai,
On 31.10.2024 15:21, Avihai Horon wrote:
Hi Maciej,
On 29/10/2024 16:58, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
From: "Maciej S. Szmigiero"
This way both the start and end points of mig
Am Wed, 23 Oct 2024 09:58:30 +0100
schrieb Mark Cave-Ayland :
> Move the timer MMIO accesses to a separate memory region on the next-pc device
> instead of being part of the next.scr MMIO memory region.
>
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/m68k/next-cube.c | 63 +++
On Thu, 31 Oct 2024 at 04:22, Philippe Mathieu-Daudé wrote:
>
> The following changes since commit 58d49b5895f2e0b5cfe4b2901bf24f3320b74f29:
>
> Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into
> staging (2024-10-29 14:00:43 +)
>
> are available in the Git repository at
Am Mon, 28 Oct 2024 22:21:20 +
schrieb Mark Cave-Ayland :
> On 28/10/2024 16:21, Thomas Huth wrote:
>
> > Am Wed, 23 Oct 2024 09:58:25 +0100
> > schrieb Mark Cave-Ayland :
> >
> >> The SCSI CSRs are located within the SCSI subsystem of the NeXT PC
> >> (Peripheral
> >> Contoller) which is
Am Mon, 28 Oct 2024 22:28:58 +
schrieb Mark Cave-Ayland :
> On 28/10/2024 16:39, Thomas Huth wrote:
> > Am Wed, 23 Oct 2024 09:58:29 +0100
> > schrieb Mark Cave-Ayland :
> >
> >> Since the ESCC is part of the next-pc device, move the ESCC to be a QOM
> >> child
> >> of the next-pc device.
When calculating the index into the GIC's GPIO array for per-CPU
interrupts, we have to start with the number of SPIs. The code
currently hard-codes this to 'NUM_IRQS = 256'. However the number of
SPIs is set separately and implicitly by the value of
AST2700_MAX_IRQ, which is the number of SPIs p
In the course of a conversation on IRC with somebody who was using
the ast27x0 code as a model for a new board, I noticed that the
code currently defines a local ARCH_GIC_MAINT_IRQ with a different
value from the constant of the same name that we define in the
include/hw/arm/bsa.h header. This patc
Use the private peripheral interrupt definitions from bsa.h instead
of defining them locally.
Note that bsa.h defines these values as INTID values, which are all
16 greater than the PPI values that we were previously using. So we
refactor the code to use INTID-based values to match that.
This is
On 11/1/24 18:35, Peter Maydell wrote:
> On Tue, 29 Oct 2024 at 12:11, Alex Bennée wrote:
>>
>> From: Robert Beckett
>>
>> Support BLOB resources creation, mapping, unmapping and set-scanout by
>> calling the new stable virglrenderer 0.10 interface. Only enabled when
>> available and via the blob
On Tue, 29 Oct 2024 at 12:11, Alex Bennée wrote:
>
> From: Robert Beckett
>
> Support BLOB resources creation, mapping, unmapping and set-scanout by
> calling the new stable virglrenderer 0.10 interface. Only enabled when
> available and via the blob config. E.g. -device virtio-vga-gl,blob=true
>
On Tue, 15 Oct 2024 at 09:52, wrote:
>
> From: Roman Penyaev
>
> With bitset management now it becomes feasible to implement
> the logic of detaching frontends from multiplexer.
>
> Signed-off-by: Roman Penyaev
> Cc: "Marc-André Lureau"
> Cc: qemu-devel@nongnu.org
> Reviewed-by: Marc-André Lure
Il ven 1 nov 2024, 11:21 Junjie Mao ha scritto:
> How about specifying also the exact version in Cargo.toml, e.g.:
>
> [dependencies]
> -proc-macro2 = "1"
> -quote = "1"
> -syn = { version = "2", features = ["extra-traits"] }
> +proc-macro2 = "=1.0.84"
> +quote = "=1.0.36"
> +syn = { version = "
Dear QEMU Community,
I hope this message finds everyone well. My name is Zhigang, and I am currently
engaged in a project that requires virtualization capabilities provided by
QEMU. I am reaching out to the community for guidance on a specific
configuration that I need to implement.
I am looki
On Fri, Nov 01, 2024 at 08:45:13AM -0300, Daniel Henrique Barboza wrote:
>
>
> On 11/1/24 5:36 AM, Yong-Xuan Wang wrote:
> > Currently QEMU will continue to emulate the AIA MSI devices and enable the
> > AIA extension for guest OS when the host kernel doesn't support the
> > in-kernel AIA irqchip
On Tue, 22 Oct 2024 16:16:36 +0200
"Anthony Harivel" wrote:
> Daniel P. Berrangé, Oct 22, 2024 at 15:15:
> > On Tue, Oct 22, 2024 at 02:46:15PM +0200, Igor Mammedov wrote:
> >> On Fri, 18 Oct 2024 13:59:34 +0100
> >> Daniel P. Berrangé wrote:
> >>
> >> > On Fri, Oct 18, 2024 at 02:25:26PM +
Paolo,
I've just manually tested this, also including some debug output, and
that looks good to me. I've got some concerns about edge cases though,
see comments inline.
On Thu, 31 Oct 2024 at 11:57, Paolo Bonzini wrote:
>
> The call to xgetbv() is passing the ecx value for cpuid function 0xD,
>
This reverts commit 4c2c0474693229c1f533239bb983495c5427784d.
This commit tried to fix a problem with our usage of MMU indexes when
EL3 is AArch32, using what it described as a "more complicated
approach" where we share the same MMU index values for Secure PL1&0
and NonSecure PL1&0. In theory this
On Tue, Oct 29, 2024 at 08:39:07PM +0530, Prasad Pandit wrote:
> From: Prasad Pandit
>
> Refactor ram_save_target_page legacy and multifd
> functions into one. Other than simplifying it,
> it avoids reinitialization of the 'migration_ops'
> object, when migration moves from multifd to postcopy
>
On Tue, Oct 29, 2024 at 08:39:06PM +0530, Prasad Pandit wrote:
> From: Prasad Pandit
>
> Remove multifd capability check with Postcopy mode.
> This helps to enable both multifd and postcopy together.
>
> Update migrate_multifd() to return false when migration
> reaches Postcopy phase. In Postcop
Prasad,
On Tue, Oct 29, 2024 at 08:39:05PM +0530, Prasad Pandit wrote:
> @@ -1612,6 +1615,10 @@ postcopy_preempt_send_channel_done(MigrationState *s,
> * postcopy_qemufile_src to know whether it failed or not.
> */
> qemu_sem_post(&s->postcopy_qemufile_src_sem);
> +
> +/* Send
Preserve memory-backend-memfd memory objects during cpr-transfer.
Signed-off-by: Steve Sistare
Acked-by: Peter Xu
---
backends/hostmem-memfd.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/backends/hostmem-memfd.c b/backends/hostmem-memfd.c
index 6a3c89a..2740
In commit 4c2c0474693229 I tried to fix a problem with our
usage of MMU indexes when EL3 is AArch32. The problem we're
trying to fix is:
Architecturally, when EL3 is AArch32, all Secure code runs under the
Secure PL1&0 translation regime:
* code at EL3, which might be Mon, or SVC, or
Our current usage of MMU indexes when EL3 is AArch32 is confused.
Architecturally, when EL3 is AArch32, all Secure code runs under the
Secure PL1&0 translation regime:
* code at EL3, which might be Mon, or SVC, or any of the
other privileged modes (PL1)
* code at EL0 (Secure PL0)
This is diff
Define the cpr-uri QEMU command-line option to specify the URI from
which CPR vmstate is loaded for cpr-transfer mode.
Signed-off-by: Steve Sistare
Acked-by: Peter Xu
---
include/migration/cpr.h | 3 +++
migration/cpr.c | 12
qemu-options.hx | 8
system/v
Add a check that the requested offset + length does not go beyond the end
of the cel_log.
Whilst the cci->cel_log is large enough to include all possible CEL
entries, the guest might still ask for entries beyond the end of it.
Move the comment to this new check rather than before the check on the
In cmd_features_set_feature() the an offset + data size schemed
is used to allow for large features. Ensure this does not write
beyond the end fo the buffers used to accumulate the full feature
attribute set.
Reported-by: Esifiel
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c |
On Tue, 2024-10-29 at 07:40 -0700, Guenter Roeck wrote:
> On 10/28/24 01:41, Jan Lübbe wrote:
> > On Sun, 2024-10-27 at 20:32 -0700, Guenter Roeck wrote:
> > > On 10/27/24 15:26, Cédric Le Goater wrote:
> > > > On 10/27/24 23:11, Guenter Roeck wrote:
> > > > > On 10/27/24 14:13, Cédric Le Goater wr
What?
This patch series adds the live migration cpr-transfer mode, which
allows the user to transfer a guest to a new QEMU instance on the same
host with minimal guest pause time, by preserving guest RAM in place,
albeit with new virtual addresses in new QEMU, and by preserving device
file descrip
Add a migration test for cpr-transfer mode. Defer the connection to the
target monitor, else the test hangs because in cpr-transfer mode QEMU does
not listen for monitor connections until we send the migrate command to
source QEMU.
To test -incoming defer, send a migrate incoming command to the t
Define VMSTATE_FD for declaring a file descriptor field in a
VMStateDescription.
Signed-off-by: Steve Sistare
---
include/migration/vmstate.h | 9 +
migration/vmstate-types.c | 23 +++
2 files changed, 32 insertions(+)
diff --git a/include/migration/vmstate.h b/in
Add the cpr-transfer migration mode. Usage:
qemu-system-$arch -machine anon-alloc=memfd ...
start new QEMU with "-incoming -cpr-uri "
Issue commands to old QEMU:
migrate_set_parameter mode cpr-transfer
migrate_set_parameter cpr-uri
migrate -d
The migrate command stops the VM, sav
On Fri, Nov 01, 2024 at 06:47:40AM -0700, Steve Sistare wrote:
> @@ -1849,6 +1852,35 @@ static void ram_block_add(RAMBlock *new_block, Error
> **errp)
> qemu_mutex_unlock_ramlist();
> return;
> }
> +
> +} else if (current_machine->anon_alloc =
Define the cpr-uri migration parameter to specify the URI to which
CPR vmstate is saved for cpr-transfer mode.
Signed-off-by: Steve Sistare
Acked-by: Peter Xu
---
migration/migration-hmp-cmds.c | 10 ++
migration/options.c| 28
migration/options.
Define functions to put/get file descriptors to/from a QEMUFile, for qio
channels that support SCM_RIGHTS. Maintain ordering such that
put(A), put(fd), put(B)
followed by
get(A), get(fd), get(B)
always succeeds. Other get orderings may succeed but are not guaranteed.
Signed-off-by: Steve Sis
Add an option to defer connection to the target monitor, needed by the
cpr-transfer test.
Signed-off-by: Steve Sistare
---
tests/qtest/migration-test.c | 26 +++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/tests/qtest/migration-test.c b/tests/qtest/migra
Add an option to defer making the connecting to the monitor and qtest
sockets when calling qtest_init_with_env. The client makes the connection
later by calling qtest_connect_deferred and qtest_qmp_handshake.
Signed-off-by: Steve Sistare
---
tests/qtest/libqtest.c | 69 +++
From: Hyman Huang
Move cpu-throttle.c from system to migration since it's
only used for migration; this makes us avoid exporting the
util functions and variables in misc.h but export them in
migration.h when implementing the periodic ramblock dirty
sync feature in the upcoming commits.
Since CPU
Save the memfd for anonymous ramblocks in CPR state, along with a name
that uniquely identifies it. The block's idstr is not yet set, so it
cannot be used for this purpose. Find the saved memfd in new QEMU when
creating a block. QEMU hard-codes the length of some internally-created
blocks, so to
Allow each migration test to define its own memory backend, replacing
the standard "-m " specification.
Signed-off-by: Steve Sistare
---
tests/qtest/migration-test.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/tests/qtest/migration-test.c b/tests/qte
Signed-off-by: Steve Sistare
---
docs/devel/migration/CPR.rst | 144 ++-
1 file changed, 142 insertions(+), 2 deletions(-)
diff --git a/docs/devel/migration/CPR.rst b/docs/devel/migration/CPR.rst
index 63c3647..732d5a6 100644
--- a/docs/devel/migration/CPR
Add functions to create a QEMUFile based on a unix URI, for saving or
loading, for use by cpr-transfer mode to preserve CPR state.
Signed-off-by: Steve Sistare
Reviewed-by: Peter Xu
---
include/migration/cpr.h | 3 ++
migration/cpr-transfer.c | 81 +
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