Re: [PATCH 4/8] target/i386: add AVX10 feature and AVX10 version property

On Thu, Oct 31, 2024 at 01:52:24PM +0800, Xiaoyao Li wrote: > Date: Thu, 31 Oct 2024 13:52:24 +0800 > From: Xiaoyao Li > Subject: Re: [PATCH 4/8] target/i386: add AVX10 feature and AVX10 version > property > > On 10/31/2024 12:39 PM, Tao Su wrote: > > On Wed, Oct 30, 2024 at 11:55:34PM +0800, Zh

Re: [PATCH v4 02/15] hw/display/apple-gfx: Introduce ParavirtualizedGraphics.Framework support

On 2024/10/30 6:16, Phil Dennis-Jordan wrote: On Tue, 29 Oct 2024 at 08:42, Akihiko Odaki > wrote: On 2024/10/29 6:06, Phil Dennis-Jordan wrote: > > > On Mon, 28 Oct 2024 at 17:06, Akihiko Odaki mailto:akihiko.od...@daynix.com> >

Re: [PATCH 4/8] target/i386: add AVX10 feature and AVX10 version property

On Thu, Oct 31, 2024 at 01:52:24PM +0800, Xiaoyao Li wrote: [ ... ] > > I mainly want to let avx10_version be assigned only when -cpu host or max, > > so that it can be distinguished from the cpu model. This should also be > > Paolo's original intention in v2. > > avx10_version needs to be assig

Re: [PATCH 4/8] target/i386: add AVX10 feature and AVX10 version property

On 10/31/2024 12:39 PM, Tao Su wrote: On Wed, Oct 30, 2024 at 11:55:34PM +0800, Zhao Liu wrote: On Wed, Oct 30, 2024 at 10:05:51PM +0800, Tao Su wrote: Date: Wed, 30 Oct 2024 22:05:51 +0800 From: Tao Su Subject: Re: [PATCH 4/8] target/i386: add AVX10 feature and AVX10 version property On We

Re: [RFC v3 3/3] vhost: Allocate memory for packed vring

Hi, Thank you for your reply. On 10/28/24 1:40 PM, Eugenio Perez Martin wrote: On Mon, Oct 28, 2024 at 6:38 AM Sahil Siddiq wrote: [...] I spent some time tinkering with the L0-L1-L2 test environment setup, and understanding QEMU's hw/virtio/vhost-vdpa.c [1] as well as Linux's drivers/vhost/v

[PULL 26/50] target/riscv: introduce ssp and enabling controls for zicfiss

From: Deepak Gupta zicfiss introduces a new state ssp ("shadow stack register") in cpu. ssp is expressed as a new unprivileged csr (CSR_SSP=0x11) and holds virtual address for shadow stack as programmed by software. Shadow stack (for each mode) is enabled via bit3 in *envcfg CSRs. Shadow stack c

Re: [PATCH v2] target/riscv: Fix vcompress with rvv_ta_all_1s

On Wed, Oct 30, 2024 at 2:37 PM Anton Blanchard wrote: > > vcompress packs vl or less fields into vd, so the tail starts after the > last packed field. This could be more clearly expressed in the ISA, > but for now this thread helps to explain it: > > https://github.com/riscv/riscv-v-spec/issues/7

Re: [PATCH 09/12] plugins: add missing export for qemu_plugin_num_vcpus

On 31/10/24 01:04, Pierrick Bouvier wrote: Fixes: 4a448b148ca ("plugins: add qemu_plugin_num_vcpus function") Signed-off-by: Pierrick Bouvier --- include/qemu/qemu-plugin.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/qemu/qemu-plugin.h b/include/qemu/qemu-plugin.h index 622c

Re: [PATCH 4/8] target/i386: add AVX10 feature and AVX10 version property

On Wed, Oct 30, 2024 at 11:55:34PM +0800, Zhao Liu wrote: > On Wed, Oct 30, 2024 at 10:05:51PM +0800, Tao Su wrote: > > Date: Wed, 30 Oct 2024 22:05:51 +0800 > > From: Tao Su > > Subject: Re: [PATCH 4/8] target/i386: add AVX10 feature and AVX10 version > > property > > > > On Wed, Oct 30, 2024 a

Re: [PATCH v2] hw/riscv: Add Microblaze V 32bit virt board

On Thu, Oct 31, 2024 at 2:06 PM Philippe Mathieu-Daudé wrote: > > Hi Michal, > > On 30/10/24 02:53, Michal Simek wrote: > > Hi Alistair, > > > > On 10/30/24 03:54, Alistair Francis wrote: > >> On Thu, Oct 17, 2024 at 5:26 PM Sai Pavan Boddu > >> wrote: > > > >>> diff --git a/hw/riscv/microblaze-v

[PULL 13/14] target/mips: Introduce disas_mt_available()

Similarly to commit 17c2c320f3c ("Introduce ase_mt_available helper"), introduce the disas_mt_available() one which takes a DisasContext argument to determine whether Multi-Threading is available by checking the MT bit of the CP0_Config3 register. Remove the then unused ASE_MT definition. Signed-

[PULL 14/14] target/mips: Remove unused CPUMIPSState::current_fpu field

The 'current_fpu' field is unused since commit f01be154589 ("Move the active FPU registers into env again, and use more TCG registers to access them"). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson Message-Id: <20241021151253.36443-1-phi...@l

[PULL 12/14] target/mips: Introduce ase_3d_available() helper

Determine if the MIPS-3D ASE is implemented by checking the state of the 3D bit in the FIR CP1 control register. Remove the then unused ASE_MIPS3D definition. Note, this allows using MIPS-3D on the mips64dspr2 model. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-I

[PULL 11/14] target/mips: Remove unreachable 32-bit code on 64-bit Loongson Ext

Loongson fixed-point multiplies and divisions opcodes are specific to 64-bit cores (Loongson-2 and Loongson-3 families). Simplify by removing the 32-bit checks. Reported-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Message-Id: <20241026175349.84523-1

[PULL 10/14] target/mips: Convert Loongson [D]MULT[U].G opcodes to decodetree

From: Philippe Mathieu-Daudé Convert the following opcodes to decodetree: - MULT.G - multiply 32-bit signed integers - MULTU.G - multiply 32-bit unsigned integers - DMULT.G - multiply 64-bit signed integers - DMULTU.G - multiply 64-bit unsigned integers Now that all opcodes from the extension h

[PULL 09/14] target/mips: Convert Loongson [D]MOD[U].G opcodes to decodetree

From: Philippe Mathieu-Daudé Convert the following opcodes to decodetree: - MOD.G - mod 32-bit signed integers - MODU.G - mod 32-bit unsigned integers - DMOD.G - mod 64-bit signed integers - DMODU.G - mod 64-bit unsigned integers Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-D

[PULL 08/14] target/mips: Convert Loongson [D]DIVU.G opcodes to decodetree

From: Philippe Mathieu-Daudé Convert DIVU.G (divide 32-bit unsigned integers) and DDIVU.G (divide 64-bit unsigned integers) opcodes to decodetree. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20241026175349.84523-7-phi...@linaro.org> Signed-off-by: Philippe

[PULL 06/14] target/mips: Convert Loongson DDIV.G opcodes to decodetree

From: Philippe Mathieu-Daudé Introduce decode_loongson() to decode all Loongson vendor specific opcodes. Start converting a single opcode: DDIV.G (divide 64-bit signed integers). Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20241026175349.84523-5-phi...@lin

[PULL 07/14] target/mips: Convert Loongson DIV.G opcodes to decodetree

From: Philippe Mathieu-Daudé DIV.G and DDIV.G are very similar. Provide gen_lext_DIV_G() a 'is_double' argument so it can generate DIV.G (divide 32-bit signed integers). With this commit we explicit the template used to generate opcode for 32/64-bit word variants. Next commits will be less verbo

[PULL 05/14] target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP

From: Philippe Mathieu-Daudé There is no issue having multiple enum declarations with the same value. As we are going to remove the OPC_MULT_G_2E definition in few commits, restore the OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP definitions and use them where they belong. Signed-off-by: Philippe Mathieu

[PULL 03/14] target/mips: Extract decode_64bit_enabled() helper

Extract the decode_64bit_enabled() helper which detects whether CPUs can run 64-bit instructions. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Message-Id: <20241026175349.84523-2-phi...@linaro.org> --- target/mips/tcg/translate.h | 2 ++ target/mips/tcg/translate.c | 7 ++

[PULL 04/14] target/mips: Simplify Loongson MULTU.G opcode

Since MULTU opcodes don't record the most significant bits of the infinite result, sign-extending the sources make no difference in the result. Once we remove the sign extension of source registers, MULT and MULTU are identical (as are DMULT and DMULTU). Suggested-by: Richard Henderson Signed-of

[PULL 02/14] target/mips: Enable MSA ASE for mips32r6-generic

From: Aleksandar Markovic Enable MSA ASE for mips32r6-generic CPU. Signed-off-by: Aleksandar Markovic Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic Reviewed-by: Aleksandar Rikalo Message-ID: Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu-defs.c.inc | 8 +-

[PULL 01/14] target/mips: Migrate TLB MemoryMapID register

From: Yongbok Kim Include CP0 MemoryMapID register in migration state. Fixes: 99029be1c28 ("target/mips: Add implementation of GINVT instruction") Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Aleksandar Rakic Reviewed-by: Aleksandar Rikalo Message-ID: Signed

[PULL 00/14] MIPS patches for 2024-10-31

The following changes since commit 58d49b5895f2e0b5cfe4b2901bf24f3320b74f29: Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging (2024-10-29 14:00:43 +) are available in the Git repository at: https://github.com/philmd/qemu.git tags/mips-20241031 for you to fe

[PULL 19/50] target/riscv: save and restore elp state on priv transitions

From: Deepak Gupta elp state is recorded in *status on trap entry (less privilege to higher privilege) and restored in elp from *status on trap exit (higher to less privilege). Additionally this patch introduces a forward cfi helper function to determine if current privilege has forward cfi is e

[PULL 41/50] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug

From: Tomasz Jeznach Generate device tree entry for riscv-iommu PCI device, along with mapping all PCI device identifiers to the single IOMMU device instance. Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Message-I

[PATCH 12/12] docs: add information on how to setup build environments

MacOS and Linux are straightforward, but Windows needs a bit more details. Signed-off-by: Pierrick Bouvier --- docs/about/build-platforms.rst | 4 +- docs/devel/build-system.rst| 100 + 2 files changed, 103 insertions(+), 1 deletion(-) diff --git a/docs/abo

[PULL 05/50] target/riscv: Detect sxl to set bit width for RV32 in RV64

From: TANG Tiancheng Ensure correct bit width based on sxl when running RV32 on RV64 QEMU. This is required as MMU address translations run in S-mode. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Alistair Francis Message-ID: <20240919055048.562-5-zhiwei_...@linux.alibaba

Re: [PATCH 06/12] qga: fix missing static and prototypes windows warnings

On 31/10/24 01:04, Pierrick Bouvier wrote: Reported by clang++, but not by g++. ../qga/vss-win32/provider.cpp:48:6: error: no previous prototype for function 'LockModule' [-Werror,-Wmissing-prototypes] 48 | void LockModule(BOOL lock) | ^ ../qga/vss-win32/provider.cpp:48:1: note:

[PULL 32/50] target/riscv: compressed encodings for sspush and sspopchk

From: Deepak Gupta sspush/sspopchk have compressed encodings carved out of zcmops. compressed sspush is designated as c.mop.1 while compressed sspopchk is designated as c.mop.5. Note that c.sspush x1 exists while c.sspush x5 doesn't. Similarly c.sspopchk x5 exists while c.sspopchk x1 doesn't. S

[PATCH 00/12] Enable building plugins on Windows with Clang

For now, it was only possible to build plugins using GCC on Windows. However, windows-aarch64 only supports Clang. The first patches (already posted and normally pulled) are fixes and prerequisite to build plugins with meson. They are integrated here because it's not possible to have two based-on

[PATCH 06/12] qga: fix missing static and prototypes windows warnings

Reported by clang++, but not by g++. ../qga/vss-win32/provider.cpp:48:6: error: no previous prototype for function 'LockModule' [-Werror,-Wmissing-prototypes] 48 | void LockModule(BOOL lock) | ^ ../qga/vss-win32/provider.cpp:48:1: note: declare 'static' if the function is not inten

[PATCH 09/12] plugins: add missing export for qemu_plugin_num_vcpus

Signed-off-by: Pierrick Bouvier --- include/qemu/qemu-plugin.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/qemu/qemu-plugin.h b/include/qemu/qemu-plugin.h index 622c9a02327..0fba36ae028 100644 --- a/include/qemu/qemu-plugin.h +++ b/include/qemu/qemu-plugin.h @@ -803,6 +803,7 @@ vo

[PULL 03/50] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32

From: TANG Tiancheng Ensure pmp_size is correctly determined using mxl for RV32 in RV64 QEMU. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Alistair Francis Message-ID: <20240919055048.562-3-zhiwei_...@linux.alibaba.com> Signed-off-by: Alistair Francis --- target/riscv/

[PATCH 02/12] contrib/plugins/cflow: fix warning

contrib/plugins/cflow.c: In function ‘plugin_exit’: contrib/plugins/cflow.c:167:19: error: declaration of ‘n’ shadows a previous local [-Werror=shadow=local] 167 | NodeData *n = l->data; | ^ contrib/plugins/cflow.c:139:9: note: shadowed declaration is here 139 |

Re: [PATCH v2] hw/riscv: Add Microblaze V 32bit virt board

Hi Michal, On 30/10/24 02:53, Michal Simek wrote: Hi Alistair, On 10/30/24 03:54, Alistair Francis wrote: On Thu, Oct 17, 2024 at 5:26 PM Sai Pavan Boddu wrote: diff --git a/hw/riscv/microblaze-v-virt.c b/hw/riscv/microblaze-v-virt.c new file mode 100644 index 000..6603e6d6b06 ---

[PATCH 04/12] contrib/plugins: remove Makefile for contrib/plugins

Now replaced by meson build. Reviewed-by: Alex Bennée Signed-off-by: Pierrick Bouvier --- configure| 18 - Makefile | 10 - contrib/plugins/Makefile | 87 3 files changed, 115 deletions(-) delete mode 100644 c

[PULL 29/50] target/riscv: AMO operations always raise store/AMO fault

From: Deepak Gupta This patch adds one more word for tcg compile which can be obtained during unwind time to determine fault type for original operation (example AMO). Depending on that, fault can be promoted to store/AMO fault. Signed-off-by: Deepak Gupta Suggested-by: Richard Henderson Revie

[PULL 15/50] hw/char: sifive_uart: Print uart characters async

The current approach of using qemu_chr_fe_write() and ignoring the return values results in dropped characters [1]. Let's update the SiFive UART to use a async sifive_uart_xmit() function to transmit the characters and apply back pressure to the guest with the SIFIVE_UART_TXFIFO_FULL status. This

[PULL 10/50] hw/intc: Make zeroth priority register read-only

From: Sergey Makarov According to PLIC specification chapter 4, zeroth priority register is reserved. Discard writes to this register. Signed-off-by: Sergey Makarov Reviewed-by: Alistair Francis Message-ID: <20240918140229.124329-2-s.maka...@syntacore.com> Signed-off-by: Alistair Francis ---

[PULL 33/50] disas/riscv: enable disassembly for zicfiss instructions

From: Deepak Gupta Enable disassembly for sspush, sspopchk, ssrdp & ssamoswap. Disasembly is only enabled if zimop and zicfiss ext is set to true. Signed-off-by: Deepak Gupta Acked-by: Alistair Francis Message-ID: <20241008225010.1861630-19-de...@rivosinc.com> Signed-off-by: Alistair Francis

[PULL 09/50] tests/avocado: Boot Linux for RV32 cpu on RV64 QEMU

From: LIU Zhiwei make check-avocado AVOCADO_TESTS=tests/avocado/tuxrun_baselines.py: \ TuxRunBaselineTest:test_riscv64_rv32 Signed-off-by: LIU Zhiwei Suggested-by: Daniel Henrique Barboza Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Message-ID: <20240919055048.562-9-zhiwei

[PATCH 01/12] scripts: remove erroneous file that breaks git clone on Windows

This file was created by mistake in recent ed7667188 (9p: remove 'proxy' filesystem backend driver). When cloning the repository using native git for windows, we see this: Error: error: invalid path 'scripts/meson-buildoptions.' Error: The process 'C:\Program Files\Git\bin\git.exe' failed with exi

[PATCH 05/12] qga: fix -Wsometimes-uninitialized windows warning

Reported by clang, but not gcc. [5123/5678] Compiling C object qga/qemu-ga.exe.p/commands-windows-ssh.c.obj FAILED: qga/qemu-ga.exe.p/commands-windows-ssh.c.obj "cc" "-Iqga/qemu-ga.exe.p" "-Iqga" "-I../qga" "-I." "-Iqapi" "-Itrace" "-Iui" "-Iui/shader" "-IC:/msys64/clangarm64/include/glib-2.0" "

[PATCH 10/12] plugins: detect qemu plugin API symbols from header

Instead of using a static file (error prone and hard to keep in sync), we generate it using a script. Note: if a symbol is not exported, we'll now notice it when linking for Windows/MacOS platforms. Signed-off-by: Pierrick Bouvier --- MAINTAINERS| 1 + plugins/meson.build

[PATCH 11/12] plugins: eradicate qemu-plugins.symbols static file

Signed-off-by: Pierrick Bouvier --- plugins/qemu-plugins.symbols | 59 1 file changed, 59 deletions(-) delete mode 100644 plugins/qemu-plugins.symbols diff --git a/plugins/qemu-plugins.symbols b/plugins/qemu-plugins.symbols deleted file mode 100644 index 032

[PATCH 03/12] meson: build contrib/plugins with meson

Tried to unify this meson.build with tests/tcg/plugins/meson.build but the resulting modules are not output in the right directory. Originally proposed by Anton Kochkov, thank you! Solves: https://gitlab.com/qemu-project/qemu/-/issues/1710 Reviewed-by: Alex Bennée Signed-off-by: Pierrick Bouvier

[PATCH 07/12] win32: use compiler option instead of attribute gcc_struct

This attribute is not recognized by clang, but the associated option is. Signed-off-by: Pierrick Bouvier --- meson.build | 8 include/qemu/compiler.h | 7 +-- subprojects/libvhost-user/libvhost-user.h | 6 +- 3 files changed, 6 ins

[PATCH 08/12] plugins: enable linking with clang/lld

Windows uses a special mechanism to enable plugins to work (DLL delay loading). Option for lld is different than ld. Signed-off-by: Pierrick Bouvier --- meson.build | 4 contrib/plugins/meson.build | 2 +- plugins/meson.build | 24 te

[PULL 18/50] target/riscv: Introduce elp state and enabling controls for zicfilp

From: Deepak Gupta zicfilp introduces a new state elp ("expected landing pad") in cpu. During normal execution, elp is idle (NO_LP_EXPECTED) i.e not expecting landing pad. On an indirect call, elp moves LP_EXPECTED. When elp is LP_EXPECTED, only a subsquent landing pad instruction can set state b

Re: [PATCH 2/2] crypto: perform runtime check for hash/hmac support in gcrypt

On 30/10/24 07:11, Daniel P. Berrangé wrote: gcrypto has the ability to dynamically disable hash/hmac algorithms at runtime, so QEMU must perform a runtime check. Signed-off-by: Daniel P. Berrangé --- crypto/hash-gcrypt.c | 2 +- crypto/hmac-gcrypt.c | 2 +- 2 files changed, 2 insertions(+)

[PULL 45/50] hw/riscv/riscv-iommu: add DBG support

From: Tomasz Jeznach DBG support adds three additional registers: tr_req_iova, tr_req_ctl and tr_response. The DBG cap is always enabled. No on/off toggle is provided for it. Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Reviewed-by: Frank Chang Reviewed-by: Alistair F

[PULL 28/50] target/riscv: mmu changes for zicfiss shadow stack protection

From: Deepak Gupta zicfiss protects shadow stack using new page table encodings PTE.W=1, PTE.R=0 and PTE.X=0. This encoding is reserved if zicfiss is not implemented or if shadow stack are not enabled. Loads on shadow stack memory are allowed while stores to shadow stack memory leads to access fa

[PULL 17/50] target/riscv: Add zicfilp extension

From: Deepak Gupta zicfilp [1] riscv cpu extension enables forward control flow integrity. If enabled, all indirect calls must land on a landing pad instruction. This patch sets up space for zicfilp extension in cpuconfig. zicfilp is dependend on zicsr. [1] - https://github.com/riscv/riscv-cfi

[PULL 01/50] target/riscv/csr.c: Fix an access to VXSAT

From: Evgenii Prokopiev The register VXSAT should be RW only to the first bit. The remaining bits should be 0. The RISC-V Instruction Set Manual Volume I: Unprivileged Architecture The vxsat CSR has a single read-write least-significant bit (vxsat[0]) that indicates if a fixed-point instruction

[PULL 02/50] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI

From: TANG Tiancheng RV32 OpenSBI need a fw_dynamic_info parameter with 32-bit fields instead of target_ulong. In RV64 QEMU, target_ulong is 64. So it is not right for booting RV32 OpenSBI. We create a fw_dynmaic_info32 struct for this purpose. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zh

[PULL 49/50] target/riscv/kvm: clarify how 'riscv-aia' default works

From: Daniel Henrique Barboza We do not have control in the default 'riscv-aia' default value. We can try to set it to a specific value, in this case 'auto', but there's no guarantee that the host will accept it. Couple with this we're always doing a 'qemu_log' to inform whether we're ended up u

[PULL 44/50] hw/riscv/riscv-iommu: add ATS support

From: Tomasz Jeznach Add PCIe Address Translation Services (ATS) capabilities to the IOMMU. This will add support for ATS translation requests in Fault/Event queues, Page-request queue and IOATC invalidations. Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Reviewed-by: Fr

[PULL 42/50] test/qtest: add riscv-iommu-pci tests

From: Daniel Henrique Barboza To test the RISC-V IOMMU emulation we'll use its PCI representation. Create a new 'riscv-iommu-pci' libqos device that will be present with CONFIG_RISCV_IOMMU. This config is only available for RISC-V, so this device will only be consumed by the RISC-V libqos machin

[PULL 16/50] target/riscv: expose *envcfg csr and priv to qemu-user as well

From: Deepak Gupta Execution environment config CSR controlling user env and current privilege state shouldn't be limited to qemu-system only. *envcfg CSRs control enabling of features in next lesser mode. In some cases bits *envcfg CSR can be lit up by kernel as part of kernel policy or software

[PULL 36/50] exec/memtxattr: add process identifier to the transaction attributes

From: Tomasz Jeznach Extend memory transaction attributes with process identifier to allow per-request address translation logic to use requester_id / process_id to identify memory mapping (e.g. enabling IOMMU w/ PASID translations). Signed-off-by: Tomasz Jeznach Reviewed-by: Frank Chang Revie

[PULL 47/50] docs/specs: add riscv-iommu

From: Daniel Henrique Barboza Add a simple guideline to use the existing RISC-V IOMMU support we just added. This doc will be updated once we add the riscv-iommu-sys device. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20241016204038.649340-13-dbarb...@ven

[PULL 46/50] qtest/riscv-iommu-test: add init queues test

From: Daniel Henrique Barboza Add an additional test to further exercise the IOMMU where we attempt to initialize the command, fault and page-request queues. These steps are taken from chapter 6.2 of the RISC-V IOMMU spec, "Guidelines for initialization". It emulates what we expect from the soft

[PULL 48/50] target/riscv/kvm: set 'aia_mode' to default in error path

From: Daniel Henrique Barboza When failing to set the selected AIA mode, 'aia_mode' is left untouched. This means that 'aia_mode' will not reflect the actual AIA mode, retrieved in 'default_aia_mode', This is benign for now, but it will impact QMP query commands that will expose the 'aia_mode' v

[PULL 11/50] hw/intc: Don't clear pending bits on IRQ lowering

From: Sergey Makarov According to PLIC specification (chapter 5), there is only one case, when interrupt is claimed. Fix PLIC controller to match this behavior. Signed-off-by: Sergey Makarov Reviewed-by: Alistair Francis Message-ID: <20240918140229.124329-3-s.maka...@syntacore.com> Signed-off-

[PULL 30/50] target/riscv: update `decode_save_opc` to store extra word2

From: Deepak Gupta Extra word 2 is stored during tcg compile and `decode_save_opc` needs additional argument in order to pass the value. This will be used during unwind to get extra information about instruction like how to massage exceptions. Updated all callsites as well. Resolves: https://git

[PULL 50/50] target/riscv: Fix vcompress with rvv_ta_all_1s

From: Anton Blanchard vcompress packs vl or less fields into vd, so the tail starts after the last packed field. This could be more clearly expressed in the ISA, but for now this thread helps to explain it: https://github.com/riscv/riscv-v-spec/issues/796 Signed-off-by: Anton Blanchard Reviewe

[PULL 40/50] hw/riscv: add riscv-iommu-pci reference device

From: Tomasz Jeznach The RISC-V IOMMU can be modelled as a PCIe device following the guidelines of the RISC-V IOMMU spec, chapter 7.1, "Integrating an IOMMU as a PCIe device". Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Reviewed-by: Frank Chang Reviewed-by: Alistair F

[PULL 31/50] target/riscv: implement zicfiss instructions

From: Deepak Gupta zicfiss has following instructions - sspopchk: pops a value from shadow stack and compares with x1/x5. If they dont match, reports a sw check exception with tval = 3. - sspush: pushes value in x1/x5 on shadow stack - ssrdp: reads current shadow stack - ssamoswap: swaps c

[PULL 35/50] target/riscv: Expose zicfiss extension as a cpu property

From: Deepak Gupta Signed-off-by: Deepak Gupta Reviewed-by: Alistair Francis Message-ID: <20241008225010.1861630-21-de...@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index afdb

[PULL 39/50] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device

From: Daniel Henrique Barboza The RISC-V IOMMU PCI device we're going to add next is a reference implementation of the riscv-iommu spec [1], which predicts that the IOMMU can be implemented as a PCIe device. However, RISC-V International (RVI), the entity that ratified the riscv-iommu spec, didn

[PULL 23/50] disas/riscv: enable `lpad` disassembly

From: Deepak Gupta Signed-off-by: Deepak Gupta Co-developed-by: Jim Shu Co-developed-by: Andy Chiu Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-ID: <20241008225010.1861630-9-de...@rivosinc.com> Signed-off-by: Alistair Francis --- disas/riscv.h | 2 ++ disas/riscv.c

[PULL 43/50] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)

From: Tomasz Jeznach The RISC-V IOMMU spec predicts that the IOMMU can use translation caches to hold entries from the DDT. This includes implementation for all cache commands that are marked as 'not implemented'. There are some artifacts included in the cache that predicts s-stage and g-stage e

[PULL 37/50] hw/riscv: add riscv-iommu-bits.h

From: Tomasz Jeznach This header will be used by the RISC-V IOMMU emulation to be added in the next patch. Due to its size it's being sent in separate for an easier review. One thing to notice is that this header can be replaced by the future Linux RISC-V IOMMU driver header, which would become

[PULL 22/50] target/riscv: zicfilp `lpad` impl and branch tracking

From: Deepak Gupta Implements setting lp expected when `jalr` is encountered and implements `lpad` instruction of zicfilp. `lpad` instruction is taken out of auipc x0, . This is an existing HINTNOP space. If `lpad` is target of an indirect branch, cpu checks for 20 bit value in x7 upper with 20 b

[PULL 21/50] target/riscv: tracking indirect branches (fcfi) for zicfilp

From: Deepak Gupta zicfilp protects forward control flow (if enabled) by enforcing all indirect call and jmp must land on a landing pad instruction `lpad`. If target of an indirect call or jmp is not `lpad` then cpu/hart must raise a sw check exception with tval = 2. This patch implements the me

[PULL 27/50] target/riscv: tb flag for shadow stack instructions

From: Deepak Gupta Shadow stack instructions can be decoded as zimop / zcmop or shadow stack instructions depending on whether shadow stack are enabled at current privilege. This requires a TB flag so that correct TB generation and correct TB lookup happens. `DisasContext` gets a field indicating

[PULL 38/50] hw/riscv: add RISC-V IOMMU base emulation

From: Tomasz Jeznach The RISC-V IOMMU specification is now ratified as-per the RISC-V international process. The latest frozen specifcation can be found at: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf Add the foundation of the device emulation for RISC-V

[PULL 20/50] target/riscv: additional code information for sw check

From: Deepak Gupta sw check exception support was recently added. This patch further augments sw check exception by providing support for additional code which is provided in *tval. Adds `sw_check_code` field in cpuarchstate. Whenever sw check exception is raised *tval gets the value deposited in

[PULL 34/50] disas/riscv: enable disassembly for compressed sspush/sspopchk

From: Deepak Gupta sspush and sspopchk have equivalent compressed encoding taken from zcmop. cmop.1 is sspush x1 while cmop.5 is sspopchk x5. Due to unusual encoding for both rs1 and rs2 from space bitfield, this required a new codec. Signed-off-by: Deepak Gupta Acked-by: Alistair Francis Mess

[PULL 25/50] target/riscv: Add zicfiss extension

From: Deepak Gupta zicfiss [1] riscv cpu extension enables backward control flow integrity. This patch sets up space for zicfiss extension in cpuconfig. And imple- ments dependency on A, zicsr, zimop and zcmop extensions. [1] - https://github.com/riscv/riscv-cfi Signed-off-by: Deepak Gupta Co

[PULL 08/50] target/riscv: Add max32 CPU for RV64 QEMU

From: LIU Zhiwei We may need 32-bit max for RV64 QEMU. Thus we add these two CPUs for RV64 QEMU. The reason we don't expose them to RV32 QEMU is that we already have max cpu with the same configuration. Another reason is that we want to follow the RISC-V custom where addw instruction doesn't exi

[PULL 12/50] target/riscv: Set vtype.vill on CPU reset

From: Rob Bradford The RISC-V unprivileged specification "31.3.11. State of Vector Extension at Reset" has a note that recommends vtype.vill be set on reset as part of ensuring that the vector extension have a consistent state at reset. This change now makes QEMU consistent with Spike which sets

[PULL 04/50] target/riscv: Correct SXL return value for RV32 in RV64 QEMU

From: TANG Tiancheng Ensure that riscv_cpu_sxl returns MXL_RV32 when runningRV32 in an RV64 QEMU. Signed-off-by: TANG Tiancheng Fixes: 05e6ca5e156 ("target/riscv: Ignore reserved bits in PTE for RV64") Reviewed-by: Liu Zhiwei Reviewed-by: Alistair Francis Message-ID: <20240919055048.562-4-zhi

[PULL 14/50] hw/char: riscv_htif: Use blocking qemu_chr_fe_write_all

The current approach of using qemu_chr_fe_write() and ignoring the return values results in dropped characters [1]. Ideally we want to report FIFO status to the guest, but the HTIF isn't a real UART, so we don't really have a way to do that. Instead let's just use qemu_chr_fe_write_all() so at lea

[PULL 06/50] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU

From: TANG Tiancheng Ensure mcause high bit is correctly set by using 32-bit width for RV32 mode and 64-bit width for RV64 mode. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Alistair Francis Message-ID: <20240919055048.562-6-zhiwei_...@linux.alibaba.com> Signed-off-by: A

[PULL 24/50] target/riscv: Expose zicfilp extension as a cpu property

From: Deepak Gupta Signed-off-by: Deepak Gupta Reviewed-by: Alistair Francis Message-ID: <20241008225010.1861630-10-de...@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 27fb

[PULL 13/50] hw/intc/riscv_aplic: Check and update pending when write sourcecfg

From: Yong-Xuan Wang The section 4.5.2 of the RISC-V AIA specification says that any write to a sourcecfg register of an APLIC might (or might not) cause the corresponding interrupt-pending bit to be set to one if the rectified input value is high (= 1) under the new source mode. If an interrupt

Re: [PATCH v3 0/9] target/mips: Convert Loongson LEXT opcodes to decodetree

On 26/10/24 14:53, Philippe Mathieu-Daudé wrote: Philippe Mathieu-Daudé (9): target/mips: Extract decode_64bit_enabled() helper target/mips: Simplify Loongson MULTU.G opcode target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP target/mips: Convert Loongson DDIV.G opcodes to

[PULL 00/50] riscv-to-apply queue

The following changes since commit 58d49b5895f2e0b5cfe4b2901bf24f3320b74f29: Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging (2024-10-29 14:00:43 +) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-2024

[PULL 07/50] target/riscv: Enable RV32 CPU support in RV64 QEMU

From: TANG Tiancheng Add gdb XML files and adjust CPU initialization to allow running RV32 CPUs in RV64 QEMU. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Alistair Francis Message-ID: <20240919055048.562-7-zhiwei_...@linux.alibaba.com> Signed-off-by: Alistair Francis --

Re: [PATCH v2] target/riscv: Fix vcompress with rvv_ta_all_1s

On Wed, Oct 30, 2024 at 2:37 PM Anton Blanchard wrote: > > vcompress packs vl or less fields into vd, so the tail starts after the > last packed field. This could be more clearly expressed in the ISA, > but for now this thread helps to explain it: > > https://github.com/riscv/riscv-v-spec/issues/7

Re: [PATCH RFC 2/2] migration: Avoid doing RAMBlock dirty sync in the initial iteration

On Thu, Oct 31, 2024 at 3:43 AM Peter Xu wrote: > On Wed, Oct 30, 2024 at 10:09:38AM +0800, Yong Huang wrote: > > On Wed, Oct 30, 2024 at 12:21 AM Peter Xu wrote: > > > > > On Wed, Oct 23, 2024 at 10:09:51AM +0800, yong.hu...@smartx.com wrote: > > > > From: Hyman Huang > > > > > > > > KVM alway

Re: [PATCH] monitor: fix cases in switch in memory_dump

* Phil Dennis-Jordan (li...@philjordan.eu) wrote: > On Wed 30. Oct 2024 at 15:09, Anastasia Belova > wrote: > > > default case has no condition. So if it is placed > > higher that other cases, they are unreachable. > > > > Move dafult case down. > > > > The stylistic merits might be debatable, b

Re: [PATCH v3 9/9] target/mips: Remove unreachable 32-bit code on 64-bit Loongson Ext

On 10/26/24 10:53, Philippe Mathieu-Daudé wrote: Loongson fixed-point multiplies and divisions opcodes are specific to 64-bit cores (Loongson-2 and Loongson-3 families). Simplify by removing the 32-bit checks. Reported-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mi

Re: [PATCH v3 1/9] target/mips: Extract decode_64bit_enabled() helper

On 10/26/24 10:53, Philippe Mathieu-Daudé wrote: Extract the decode_64bit_enabled() helper which detects whether CPUs can run 64-bit instructions. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.h | 2 ++ target/mips/tcg/translate.c | 7 ++- 2 files changed, 8 insert

[PULL 16/18] migration: Drop migration_is_idle()

Now with the current migration_is_running(), it will report exactly the opposite of what will be reported by migration_is_idle(). Drop migration_is_idle(), instead use "!migration_is_running()" which should be identical on functionality. In reality, most of the idle check is inverted, so it's eve

[PULL 08/18] migration: Support periodic RAMBlock dirty bitmap sync

From: Hyman Huang When VM is configured with huge memory, the current throttle logic doesn't look like to scale, because migration_trigger_throttle() is only called for each iteration, so it won't be invoked for a long time if one iteration can take a long time. The periodic dirty sync aims to f

Re: [PATCH RFC 2/2] migration: Avoid doing RAMBlock dirty sync in the initial iteration

On Wed, Oct 30, 2024 at 10:09:38AM +0800, Yong Huang wrote: > On Wed, Oct 30, 2024 at 12:21 AM Peter Xu wrote: > > > On Wed, Oct 23, 2024 at 10:09:51AM +0800, yong.hu...@smartx.com wrote: > > > From: Hyman Huang > > > > > > KVM always returns 1 when userspace retrieves a dirty bitmap for > > > t

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