Paolo Bonzini writes:
> Avoid repeated lines of the form
>
> Program scripts/rust/rust_root_crate.sh found: YES
> (/home/pbonzini/work/upstream/qemu/scripts/rust/rust_root_crate.sh)
>
> in the meson logs.
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Junjie Mao
Thanks for cleaning this up!
In PVH dom0, when passthrough a device to domU, QEMU code
xen_pt_realize->xc_physdev_map_pirq wants to use gsi, but in current codes
the gsi number is got from file /sys/bus/pci/devices//irq, that is
wrong, because irq is not equal with gsi, they are in different spaces, so
pirq mapping fails.
To
Hi Michael
On Tue, Oct 15, 2024 at 9:40 PM Michael Tokarev wrote:
> On 14.10.2024 16:39, marcandre.lur...@redhat.com wrote:
> > From: Marc-André Lureau
> >
> > The following changes since commit
> 3860a2a8de56fad71db42f4ad120eb7eff03b51f:
> >
> >Merge tag 'pull-tcg-20241013' of https://gitl
Paolo Bonzini writes:
> Cope with the old version that is provided in Debian 12 and Ubuntu 22.04.
> --size_t-is-usize is needed on bindgen <0.61.0 (Debian 12, Ubuntu 22.04),
> and it was removed in bindgen 0.65.0, so check for it in meson.build.
The bindgen 0.59.1 installed from Ubuntu 22.04 a
Paolo Bonzini writes:
> All constructs introduced by newer versions of Rust have been removed.
>
> Signed-off-by: Paolo Bonzini
> ---
> meson.build | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/meson.build b/meson.build
> index 175b8d82228..0e279d245b4 100644
On 2024/10/15 下午10:31, Salil Mehta wrote:
HI Bibo,
From: maobibo
Sent: Tuesday, October 15, 2024 4:31 AM
To: Salil Mehta ; qemu-devel@nongnu.org;
qemu-...@nongnu.org; m...@redhat.com
With cpu-add/cpu-del command tested on LoongArch system, no migration
tested. There is no ne
On Mon, Oct 14, 2024 at 8:08 PM 阎明铸 wrote:
>
> Thank you for your reply and I'm sorry that I didn't explain it clearly.
>
> - ACT is an official riscv test suite to check the riscv support of the
> DUT(device under test).
It's probably worth including this in the commit message.
> - Currently A
Hi Daniel,
On 2024/10/4 下午 11:57, Daniel Henrique Barboza wrote:
From: Tomasz Jeznach
The RISC-V IOMMU specification is now ratified as-per the RISC-V
international process. The latest frozen specifcation can be found at:
https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/ris
Paolo Bonzini writes:
> On 10/15/24 14:07, Manos Pitsidianakis wrote:
>> Add stub definition of memory_order enum in wrapper.h.
>> Creating Rust bindings from C code is done by passing the wrapper.h
>> header to `bindgen`. This fails when library dependencies that use
>> compiler headers are en
On 10/15/24 7:35 PM, Stefan Berger wrote:
On 10/15/24 6:02 PM, Fabiano Rosas wrote:
Stefan Berger writes:
Yes, I've been using that method to reproduce live migration race
conditions as well. It's quite effective.
If you don't think you'll be able to find the root cause due to the
On 10/15/24 6:02 PM, Fabiano Rosas wrote:
Stefan Berger writes:
On 10/15/24 3:57 PM, Fabiano Rosas wrote:
Stefan Berger writes:
So this here is failing for you every time?
QTEST_QEMU_BINARY=build/qemu-system-aarch64
./build/tests/qtest/tpm-tis-device-swtpm-test
Sorry, I was unclea
* Yichen Wang (yichen.w...@bytedance.com) wrote:
> On Fri, Oct 11, 2024 at 10:14 AM Dr. David Alan Gilbert
> wrote:
> >
> > * Yichen Wang (yichen.w...@bytedance.com) wrote:
> > > From: Hao Xiang
> >
> > Please split the cpuid stuff out into a separate patch; it feels like
> > it should be in some
On Fri, Oct 11, 2024 at 10:14 AM Dr. David Alan Gilbert
wrote:
>
> * Yichen Wang (yichen.w...@bytedance.com) wrote:
> > From: Hao Xiang
>
> Please split the cpuid stuff out into a separate patch; it feels like
> it should be in some x86 specific place.
DSA is an Intel feature/device, and it only
On Fri, Oct 11, 2024 at 7:14 AM Fabiano Rosas wrote:
>
> Yichen Wang writes:
>
>
> Still doesn't build without DSA:
>
> qemu/include/qemu/dsa.h: In function
> ‘buffer_is_zero_dsa_batch_sync’:
> /home/fabiano/kvm/qemu/include/qemu/dsa.h:183:16: error: ‘errp’
> undeclared (first use in this functio
Stefan Berger writes:
> On 10/15/24 3:57 PM, Fabiano Rosas wrote:
>> Stefan Berger writes:
>>
>
>>>
>>> So this here is failing for you every time?
>>>
>>> QTEST_QEMU_BINARY=build/qemu-system-aarch64
>>> ./build/tests/qtest/tpm-tis-device-swtpm-test
>>
>> Sorry, I was unclear. No, that runs fo
On Fri, Oct 11, 2024 at 9:32 AM Peter Xu wrote:
>
> On Wed, Oct 09, 2024 at 04:45:58PM -0700, Yichen Wang wrote:
>
> The doc update is still missing under docs/, we may need that for a final
> merge.
>
I will work with Intel to prepare a doc in my next patch.
> Are you using this in production?
вт, 15 окт. 2024 г., 17:06 Andrew Randrianasulu :
>
>
> пн, 14 окт. 2024 г., 17:26 Andrew Randrianasulu :
>
>>
>>
>> On Mon, Oct 14, 2024 at 12:21 PM Thomas Huth wrote:
>>
>>> On 14/10/2024 11.06, Peter Maydell wrote:
>>> > On Mon, 14 Oct 2024 at 02:13, Andrew Randrianasulu
>>> > wrote:
>>> >>
>
From: Glenn Miles
Added new test for pool interrupts.
Signed-off-by: Glenn Miles
Signed-off-by: Michael Kowal
---
tests/qtest/pnv-xive2-test.c | 77
1 file changed, 77 insertions(+)
diff --git a/tests/qtest/pnv-xive2-test.c b/tests/qtest/pnv-xive2-test.c
From: Glenn Miles
XIVE crowd sizes are encoded into a 2-bit field as follows:
0: 0b00
2: 0b01
4: 0b10
16: 0b11
A crowd size of 8 is not supported.
Signed-off-by: Glenn Miles
Signed-off-by: Michael Kowal
---
hw/intc/xive.c | 21 -
1 file changed, 20 insertions(+), 1
From: Frederic Barrat
If an END has the 'i' bit set (ignore), then it targets a group of
VPs. The size of the group depends on the VP index of the target
(first 0 found when looking at the least significant bits of the
index) so a mask is applied on the VP index of a running thread to
know if we
From: Frederic Barrat
When a group interrupt cannot be delivered, we need to:
- increment the backlog counter for the group in the NVG table
(if the END is configured to keep a backlog).
- start a broadcast operation to set the LSMFB field on matching CPUs
which can't take the interrupt now b
From: Frederic Barrat
Add support for the NVPG and NVC BARs. Access to the BAR pages will
cause backlog counter operations to either increment or decriment
the counter.
Also added qtests for the same.
Signed-off-by: Frederic Barrat
Signed-off-by: Michael Kowal
---
include/hw/ppc/xive2.h
From: Glenn Miles
When booting with PHYP, the blk/index for a NVGC was being
mistakenly treated as the blk/index for a NVP. Renamed
nvp_blk/nvp_idx throughout the code to nvx_blk/nvx_idx to prevent
confusion in the future and now we delay loading the NVP until
the point where we know that the bl
From: Frederic Barrat
Add XIVE2 tests for group interrupts and group interrupts that have
been backlogged.
Signed-off-by: Frederic Barrat
Signed-off-by: Michael Kowal
---
tests/qtest/pnv-xive2-test.c | 160 +++
1 file changed, 160 insertions(+)
diff --git a/te
From: Frederic Barrat
When processing a backlog scan for group interrupts, also take
into account crowd interrupts.
Signed-off-by: Frederic Barrat
Signed-off-by: Michael Kowal
---
include/hw/ppc/xive2_regs.h | 4 ++
hw/intc/xive2.c | 82 +
2 fi
From: Frederic Barrat
If an END is defined with the 'crowd' bit set, then a target can be
running on different blocks. It means that some bits from the block
VP are masked when looking for a match. It is similar to groups, but
on the block instead of the VP index.
Most of the changes are due to
From: Glenn Miles
END notification processing has an escalation path. The escalation is
not always an END escalation but can be an ESB escalation.
Also added a check for 'resume' processing which log a message stating it
needs to be implemented. This is not needed at the time but is part of
th
From: Frederic Barrat
The NSR has a (so far unused) grouping level field. When a interrupt
is presented, that field tells the hypervisor or OS if the interrupt
is for an individual VP or for a VP-group/crowd. This patch reworks
the presentation API to allow to set/unset the level when
raising/acc
From: Frederic Barrat
When the hypervisor or OS pushes a new value to the CPPR, if the LSMFB
value is lower than the new CPPR value, there could be a pending group
interrupt in the backlog, so it needs to be scanned.
Signed-off-by: Frederic Barrat
Signed-off-by: Michael Kowal
---
include/hw/p
Hi Cédric,
On 11.10.2024 15:58, Cédric Le Goater wrote:
Hello Maciej,
On 8/27/24 19:54, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
This is an updated v2 patch series of the v1 series located here:
https://lore.kernel.org/qemu-devel/cover.1718717584.git.maciej.szmigi...@oracle.com
From: Frederic Barrat
When pushing an OS context, we were already checking if there was a
pending interrupt in the IPB and sending a notification if needed. We
also need to check if there is a pending group interrupt stored in the
NVG table. To avoid useless backlog scans, we only scan if the NV
XIVE2 has the concepts of a Group of interrupts and a Crowd of interrupts
(where a crowd is a group of Groups). These patch sets are associated with:
- NVGC tables
- Group/Crowd level notification
- Incrementing backlog countets
- Backlog processing
- NVPG and NVC Bar MMIO operations
- Group/
From: Frederic Barrat
If the 'H' attribute is set on the NVP structure, the hardware
automatically saves and restores some attributes from the TIMA in the
NVP structure.
The group-specific attributes LSMFB, LGS and T have an extra flag to
individually control what is saved/restored.
Signed-off-b
On 10/15/24 3:57 PM, Fabiano Rosas wrote:
Stefan Berger writes:
So this here is failing for you every time?
QTEST_QEMU_BINARY=build/qemu-system-aarch64
./build/tests/qtest/tpm-tis-device-swtpm-test
Sorry, I was unclear. No, that runs for about 30 iterations before it
fails. I just ran
Hi,
The doc file included in the patch will break the build:
/home/danielhb/work/qemu/docs/system/riscv/microblaze-v-virt.rst:document isn't
included in any toctree
You'll need this extra change:
$ git diff
diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
index ba195
Stefan Berger writes:
> On 10/15/24 3:22 PM, Fabiano Rosas wrote:
>> Stefan Berger writes:
>>
>>> On 10/15/24 2:11 PM, Fabiano Rosas wrote:
Hi Stefan,
I see the tpm-tis-device-swtpm test timing out, could you take a look?
qemu:qtest+qtest-aarch64 / qtest-aarch64/tpm-tis
On 10/15/24 3:22 PM, Fabiano Rosas wrote:
Stefan Berger writes:
On 10/15/24 2:11 PM, Fabiano Rosas wrote:
Hi Stefan,
I see the tpm-tis-device-swtpm test timing out, could you take a look?
qemu:qtest+qtest-aarch64 / qtest-aarch64/tpm-tis-device-swtpm-test time out
(After 60.0 seconds)
13
Stefan Berger writes:
> On 10/15/24 2:11 PM, Fabiano Rosas wrote:
>> Hi Stefan,
>>
>> I see the tpm-tis-device-swtpm test timing out, could you take a look?
>>
>> qemu:qtest+qtest-aarch64 / qtest-aarch64/tpm-tis-device-swtpm-test time out
>> (After 60.0 seconds)
>> 135/138 qemu:qtest+qtest-aar
On Tue, Oct 15, 2024 at 07:04:37PM +0200, Hanna Czenczek wrote:
> migration/savevm.c contains some calls to vmstate_save() that are
> followed by migrate_set_error() if the integer return value indicates an
> error. migrate_set_error() requires that the `Error *` object passed to
> it is set. The
From: Fan Ni
In the function of retrieving DC extents (cmd_dcd_get_dyn_cap_ext_list),
the output buffer index was not correctly updated while iterating the
extent list on the device, leaving the extents returned incorrect except for
the first one.
Fixes: 1c9221f19e ("hw/mem/cxl_type3: Add DC ext
On 10/15/24 2:11 PM, Fabiano Rosas wrote:
Hi Stefan,
I see the tpm-tis-device-swtpm test timing out, could you take a look?
qemu:qtest+qtest-aarch64 / qtest-aarch64/tpm-tis-device-swtpm-test time out
(After 60.0 seconds)
135/138 qemu:qtest+qtest-aarch64 /
qtest-aarch64/tpm-tis-device-swtpm-
Hi Jason,
On Wed, Jun 26, 2024 at 4:49 AM Jason Chien wrote:
>
> Hi Rajnesh,
>
> On 2024/6/19 下午 11:27, Rajnesh Kanwal wrote:
> > This commit adds logic to records CTR entries of different types
> > and adds required hooks in TCG and interrupt/Exception logic to
> > record events.
> >
> > This co
Hi Salil,
I’ve ran the usual tests successfully of hotplug/unplug from the number of
cold-booted cpus up to maxcpus and migration on ARM. Please feel free to add:
Tested-by: Miguel Luis
Thanks
Miguel
> On 14 Oct 2024, at 19:22, Salil Mehta wrote:
>
> Certain CPU architecture specifications
On 10/15/24 10:35, Peter Maydell wrote:
On Tue, 15 Oct 2024 at 18:30, Guenter Roeck wrote:
On 10/15/24 10:13, Peter Maydell wrote:
On Fri, 8 Mar 2024 at 15:41, Peter Maydell wrote:
Thanks to everybody for your input on this thread. My
proposal is to drop from QEMU:
* all the PXA2xx machi
Hi Stefan,
I see the tpm-tis-device-swtpm test timing out, could you take a look?
qemu:qtest+qtest-aarch64 / qtest-aarch64/tpm-tis-device-swtpm-test time out
(After 60.0 seconds)
135/138 qemu:qtest+qtest-aarch64 /
qtest-aarch64/tpm-tis-device-swtpm-test TIMEOUT 60.01s killed by signal 11
SIGSEG
On 15.09.2024 04:06, Akihiko Odaki wrote:
Most of this series are fixes for software RSS and hash reporting, which
should have no production user.
However there is one exception; patch "virtio-net: Fix size check in
dhclient workaround" fixes an out-of-bound access that can be triggered
for anyo
On 14.10.2024 16:39, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
The following changes since commit 3860a2a8de56fad71db42f4ad120eb7eff03b51f:
Merge tag 'pull-tcg-20241013' of https://gitlab.com/rth7680/qemu into
staging (2024-10-14 11:12:34 +0100)
are available in the Git r
On 08.10.2024 15:50, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
Hi,
This series adds Listener.Unix.Map interface to -display dbus, to allow shared
memory for the display (similar to Listener.Win32.Map interface).
While working on it, I collected a few fixes. I can re-send them
On Tue, 15 Oct 2024 at 18:30, Guenter Roeck wrote:
>
> On 10/15/24 10:13, Peter Maydell wrote:
> > On Fri, 8 Mar 2024 at 15:41, Peter Maydell wrote:
> >> Thanks to everybody for your input on this thread. My
> >> proposal is to drop from QEMU:
> >> * all the PXA2xx machines
> >> * all the OMA
On 10/15/24 10:13, Peter Maydell wrote:
On Fri, 8 Mar 2024 at 15:41, Peter Maydell wrote:
Thanks to everybody for your input on this thread. My
proposal is to drop from QEMU:
* all the PXA2xx machines
* all the OMAP2 machines
* the cheetah OMAP1 machine
leaving (at least for now) sx1, sx
On Fri, 8 Mar 2024 at 15:41, Peter Maydell wrote:
> Thanks to everybody for your input on this thread. My
> proposal is to drop from QEMU:
> * all the PXA2xx machines
> * all the OMAP2 machines
> * the cheetah OMAP1 machine
>
> leaving (at least for now) sx1, sx1-v1, collie.
This has now gone
migration/savevm.c contains some calls to vmstate_save() that are
followed by migrate_set_error() if the integer return value indicates an
error. migrate_set_error() requires that the `Error *` object passed to
it is set. Therefore, vmstate_save() is assumed to always set *errp on
error.
Right n
On 10/15/24 17:48, Peter Maydell wrote:
It looks like since a few months back patchew stopped pushing patches
to git branches: eg
https://patchew.org/QEMU/20240526204551.553282-1-richard.hender...@linaro.org/
from four months ago had a git branch created for it, but more
recent patches in patche
On 15.10.24 18:06, Peter Xu wrote:
On Tue, Oct 15, 2024 at 04:15:15PM +0200, Hanna Czenczek wrote:
migration/savevm.c contains some calls to vmstate_save() that are
followed by migrate_set_error() if the integer return value indicates an
error. migrate_set_error() requires that the `Error *` ob
Hi,
On Tue, Oct 15, 2024, 10:50 Marc-André Lureau
wrote:
[cut]
> qemu_chr_fe_deinit(&chr_be1, false);
> > -qemu_chr_fe_deinit(&chr_be2, true);
> > +
> > +error = NULL;
>
> Unnecessary assignment,
>
> > +qmp_chardev_remove("mux-label", &error);
> > +g_assert_cmpstr(error_get
Am 15. Oktober 2024 09:27:40 UTC schrieb Peter Maydell
:
>On Mon, 14 Oct 2024 at 19:50, Bernhard Beschow wrote:
>>
>>
>>
>> Am 14. Oktober 2024 12:47:52 UTC schrieb Peter Maydell
>> :
>> >> +typedef struct Lan9118PhyState {
>> >> +uint32_t status;
>> >> +uint32_t control;
>> >> +u
Am 15. Oktober 2024 14:09:57 UTC schrieb Gustavo Romero
:
>Commit c461f3e382 ("Remove now unused madt_cpu virtual method") removed
>madt_cpu virtual method but didn't remove the text about it in the
>header file. Thus, remove it now.
>
>Signed-off-by: Gustavo Romero
>---
> include/hw/acpi/acpi
ge tag 'ui-pull-request' of https://gitlab.com/marcandre.lureau/qemu
> into staging (2024-10-14 17:05:25 +0100)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git
> tags/pull-target-arm-20241015-1
>
> for you to
On Tue, Oct 15, 2024 at 04:15:15PM +0200, Hanna Czenczek wrote:
> migration/savevm.c contains some calls to vmstate_save() that are
> followed by migrate_set_error() if the integer return value indicates an
> error. migrate_set_error() requires that the `Error *` object passed to
> it is set. The
Have the CPS expose a 'cpu-big-endian' property so it can
set it to the vCPUs it creates.
Note, since the number of vCPUs created is dynamic, we can
not use QOM aliases.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
Tested-by: Jiaxun Yang
Reviewed-by: Richard Henderson
Message
Add the "big-endian" property and set the CP0C0_BE bit in CP0_Config0.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
Tested-by: Jiaxun Yang
Reviewed-by: Richard Henderson
Message-Id: <20241010215015.44326-15-phi...@linaro.org>
---
target/mips/cpu.h | 3 +++
target/mips/cpu.c
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20241010215015.44326-12-phi...@linaro.org>
---
target/mips/tcg/translate.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/target/mips/tcg/translate.c
It looks like since a few months back patchew stopped pushing patches
to git branches: eg
https://patchew.org/QEMU/20240526204551.553282-1-richard.hender...@linaro.org/
from four months ago had a git branch created for it, but more
recent patches in patchew's UI don't seem to have that.
Did this
The x86 architecture uses little endianness. Directly use
the little-endian LD/ST API.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Message-Id: <20241003234211.53644-4-phi...@linaro.org>
Reviewed-by: Richard Henderson
---
linux-user/i386/signal.c | 4 ++--
1 file changed, 2 i
Introduce mo_endian() which returns the endian MemOp
corresponding to the vCPU DisasContext.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
Tested-by: Jiaxun Yang
Reviewed-by: Richard Henderson
Message-Id: <20241010215015.44326-10-phi...@linaro.org>
---
target/mips/tcg/transla
Directly use tcg_constant_tl() for constant integer, this
save a call to tcg_gen_movi_tl(), often saving a temp register.
Most of the places found using the following Coccinelle spatch script:
@@
identifier tmp;
constant val;
@@
*TCGv tmp = tcg_temp_new();
...
*tcg_gen_
mips_cpu_create_with_clock() creates a vCPU. Pass it the vCPU
endianness requested by argument. Update the board call sites.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
Tested-by: Jiaxun Yang
Reviewed-by: Richard Henderson
Message-Id: <20241010215015.44326-17-phi...@linaro.o
In order to re-use cpu_is_bigendian(), declare it on "internal.h"
after renaming it as mips_env_is_bigendian().
Reviewed-by: Jiaxun Yang
Tested-by: Jiaxun Yang
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20241010215015.44326-2-phi...@linaro.org>
---
targe
The LoongArch architecture uses little endianness. Directly
use the little-endian LD/ST API.
Mechanical change using:
$ end=le; \
for acc in uw w l q tul; do \
sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \
-e "s/st${acc}_p(/st${acc}_${end}_p(/" \
$(git grep -wlE
Replace tcg_gen_movi_tl() + gen_op_addr_add() by a single
gen_op_addr_addi() call.
gen_op_addr_addi() calls tcg_gen_addi_tl() which might
optimize if the immediate is zero.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <2024101
Move code evaluation from preprocessor to compiler so
both if() ladders are processed. Mostly style change.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Pierrick Bouvier
Message-Id: <20240930073450.33195-8-phi...@linaro.org>
---
hw/xtensa/xtfpga.c | 12 +++---
Replace compile-time MO_TE evaluation by runtime mo_endian() one,
which expand target endianness from DisasContext.
Mechanical change using:
$ sed -i -e 's/MO_TE/mo_endian(ctx)/' \
$(git grep -l MO_TE target/mips)
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
Tested-by:
Methods using the 'cpu_' prefix usually take a (Arch)CPUState
argument. Since this method takes a DisasContext argument,
rename it as disas_is_bigendian().
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20241010215015.44326-3-ph
Extract the implicit MO_TE definition in order to replace
it by runtime variable in the next commit.
Mechanical change using:
$ for n in UW UL UQ UO SW SL SQ; do \
sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \
$(git grep -l MO_TE$n target/mips); \
done
manually remove superfluous
In commit 6d0cad12594 ("target/mips: Finish conversion to
tcg_gen_qemu_{ld,st}_*") we renamed the argument of the user
definition. Rename the system part for coherency. Since the
argument is ignored, prefix with 'ignored_'.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Mes
MEMOP_IDX() is unused since commit 948f88661c6 ("target/mips:
Use cpu_*_data_ra for msa load/store"), remove it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20241014232235.51988-1-phi...@linaro.org>
---
target/mips/tcg/msa_helper.c | 8
1 file chan
Directly use tcg_constant_tl() for constant integer,
this save a call to tcg_gen_movi_tl() and a temp register.
Inspired-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20241004202621.4321-4-phi...@linaro.org>
---
target/ppc/translate.c |
Instead of swapping the reversed target endianness
using MO_BSWAP, directly return the correct endianness.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20241010215015.44326-7-phi...@linaro.org>
---
target/mips/tcg/translate.h
The Hexagon architecture uses little endianness. Directly use
the little-endian LD/ST API.
Mechanical change using:
$ end=le; \
for acc in uw w l q tul; do \
sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \
-e "s/st${acc}_p(/st${acc}_${end}_p(/" \
$(git grep -wlE '
The TriCore architecture uses little endianness. Directly use
the little-endian LD/ST API.
Mechanical change using:
$ end=le; \
for acc in uw w l q tul; do \
sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \
-e "s/st${acc}_p(/st${acc}_${end}_p(/" \
$(git grep -wlE '
Functions are easier to rework than macros. Besides,
there is no gain here in inlining these.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
Tested-by: Jiaxun Yang
Reviewed-by: Richard Henderson
Message-Id: <20241010215015.44326-6-phi...@linaro.org>
---
target/mips/tcg/mips16e
Introduce mo_endian_env() which returns the endian
MemOp corresponding to the vCPU env.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
Tested-by: Jiaxun Yang
Reviewed-by: Richard Henderson
Message-Id: <20241010215015.44326-4-phi...@linaro.org>
---
target/mips/internal.h | 5 ++
Replace compile-time MO_TE evaluation by runtime mo_endian_env()
one, which expand target endianness from vCPU env.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
Tested-by: Jiaxun Yang
Reviewed-by: Richard Henderson
Message-Id: <20241010215015.44326-5-phi...@linaro.org>
---
t
Introduce ldtul_le_p() and ldtul_be_p() to use directly
in place of ldtul_p() when a target endianness is fixed.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Acked-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-Id: <20241010175246.15779-3-phi...@linaro.org>
---
The x86 architecture uses little endianness. Directly use
the little-endian LD/ST API.
Mechanical change using:
$ end=le; \
for acc in uw w l q tul; do \
sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \
-e "s/st${acc}_p(/st${acc}_${end}_p(/" \
$(git grep -wlE '(ld|
Invert target_needs_bswap() comparison to match the
COMPILING_PER_TARGET definition (2 lines upper).
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Reviewed-by: Richard Henderson
Message-Id: <20241010175246.15779-2-phi...@linaro.org>
---
include/exec/tswap.h | 2 +-
1 file
Directly use tcg_constant_tl() for constant integer,
this save a call to tcg_gen_movi_tl().
Inspired-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20241004202621.4321-3-phi...@linaro.org>
---
target/tricore/translate.c | 3 +--
1 file c
The Alpha architecture uses little endianness. Directly use
the little-endian LD/ST API.
Mechanical change using:
$ end=le; \
for acc in uw w l q tul; do \
sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \
-e "s/st${acc}_p(/st${acc}_${end}_p(/" \
$(git grep -wlE '(l
The AVR architecture uses little endianness. Directly use
the little-endian LD/ST API.
Mechanical change using:
$ end=le; \
for acc in uw w l q tul; do \
sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \
-e "s/st${acc}_p(/st${acc}_${end}_p(/" \
$(git grep -wlE '(ld|
gle-binary-20241015
for you to fetch changes up to 3e8f019be77d1b648bca0af0121da3bb37766509:
hw/mips: Have mips_cpu_create_with_clock() take an endianness argument
(2024-10-15 12:21:06 -0300)
One checkpatch warning due to wide comment:
WARNING: line over 80 characters
#108: FILE: hw/i386/multi
The Hexagon target is only built for 32-bit.
Using ldtul_p() is pointless, replace by ldl_p().
Mechanical change doing:
$ sed -i -e 's/ldtul_p/ldl_p/' \
$(git grep -wl ldtul_p target/hexagon/)
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20241004163
The Alpha target is only built for 64-bit.
Using ldtul_p() is pointless, replace by ldq_p().
Mechanical change doing:
$ sed -i -e 's/ldtul_p/ldq_p/' $(git grep -wl ldtul_p target/alpha/)
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20241004163042.85922-4-
Last use of memop_big_endian() was removed in commit 592134617c9
("accel/tcg: Reorg system mode store helpers").
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Message-Id: <20241003234211.53644-3-phi...@linaro.org>
---
include/exec/memop.h | 6 --
1 file changed, 6 deletions
Better undefined macros once we are done with them,
like we do few lines later with DO_STN_LDN_P().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Message-Id: <20241003234211.53644-2-phi...@linaro.org>
---
include/qemu/bswap.h | 2 ++
1 file changed, 2 insertions(+)
diff --git
On 10/15/24 17:20, Daniel P. Berrangé wrote:
On Tue, Oct 15, 2024 at 05:17:26PM +0200, Cédric Le Goater wrote:
On 10/15/24 17:00, Philippe Mathieu-Daudé wrote:
On 15/10/24 10:56, Jan Luebbe wrote:
For testing eMMC-specific functionality (such as handling boot
partitions), it would be very usef
On Fri, Oct 11, 2024 at 05:47:03PM +, Dr. David Alan Gilbert wrote:
> * Peter Xu (pet...@redhat.com) wrote:
> > This reverts two commits:
> >
> > 671326201dac8fe91222ba0045709f04a8ec3af4
> > 1b1f4ab69c41279a45ccd0d3178e83471e6e4ec1
> >
> > Meanwhile it adds an entry to removed-features.rst fo
On Tue, Oct 15, 2024 at 05:17:26PM +0200, Cédric Le Goater wrote:
> On 10/15/24 17:00, Philippe Mathieu-Daudé wrote:
> > On 15/10/24 10:56, Jan Luebbe wrote:
> > > For testing eMMC-specific functionality (such as handling boot
> > > partitions), it would be very useful to attach them to generic VMs
On 10/15/24 17:00, Philippe Mathieu-Daudé wrote:
On 15/10/24 10:56, Jan Luebbe wrote:
For testing eMMC-specific functionality (such as handling boot
partitions), it would be very useful to attach them to generic VMs such
as x86_64 via the sdhci-pci device:
...
-drive if=none,id=emmc-drive,fi
On 15/10/2024 16.47, Richard Henderson wrote:
On 10/15/24 04:25, Thomas Huth wrote:
The linker on OpenBSD complains:
ld: warning: console-vc.c:824 (../src/ui/console-vc.c:824)([...]):
warning: sprintf() is often misused, please use snprintf()
Using g_strdup_printf() is certainly better her
On 15/10/24 10:56, Jan Luebbe wrote:
For testing eMMC-specific functionality (such as handling boot
partitions), it would be very useful to attach them to generic VMs such
as x86_64 via the sdhci-pci device:
...
-drive if=none,id=emmc-drive,file=emmc.img,format=raw \
-device sdhci-pci \
-
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