Hi Philippe,
On 10/8/24 01:53, Philippe Mathieu-Daudé wrote:
Hi Harsh,
On 7/10/24 12:38, Harsh Prateek Bora wrote:
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as
deprecated with reasons mentioned in its commit log.
Removing pseries-2.1 specific code with this patch for now.
Ensure the function names match.
Signed-off-by: Akihiko Odaki
---
include/sysemu/dma.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
index a1ac5bc1b543..e132ece4510d 100644
--- a/include/sysemu/dma.h
+++ b/include/sysemu/dma.
On Fri Sep 13, 2024 at 10:50 PM AEST, BALATON Zoltan wrote:
> On Fri, 13 Sep 2024, Harsh Prateek Bora wrote:
> > As previously done for arch specific handlers, simplify var usage in
> > ppc_next_unmasked_interrupt by caching the env->pending_interrupts and
> > env->spr[SPR_LPCR] in local vars and u
ipvtap and macvtap create a file for each interface unlike tuntap, which
creates one file shared by all interfaces. Try to open a file dedicated
to the interface first for ipvtap and macvtap.
Signed-off-by: Akihiko Odaki
---
net/tap-linux.c | 17 ++---
1 file changed, 14 insertions(+
On Fri Sep 13, 2024 at 2:13 PM AEST, Harsh Prateek Bora wrote:
> ppc_excp_apply_ail has multiple if-checks for ail which is un-necessary.
> Combine them as appropriate.
>
> Signed-off-by: Harsh Prateek Bora
This looks okay. I was kind of trying to make the reserved cases
separate from the non-res
On Tue, Oct 8, 2024 at 2:14 AM Si-Wei Liu wrote:
>
>
>
> On 10/7/2024 6:51 AM, Eugenio Perez Martin wrote:
> > On Fri, Oct 4, 2024 at 8:48 PM Jonah Palmer wrote:
> >>
> >>
> >> On 10/4/24 11:17 AM, Eugenio Perez Martin wrote:
> >>> On Fri, Oct 4, 2024 at 2:45 PM Jonah Palmer
> >>> wrote:
>
On Fri Sep 13, 2024 at 2:13 PM AEST, Harsh Prateek Bora wrote:
> As previously done for arch specific handlers, simplify var usage in
> ppc_next_unmasked_interrupt by caching the env->pending_interrupts and
> env->spr[SPR_LPCR] in local vars and using it later at multiple places.
>
> Signed-off-by:
We computes indirections_len by adding 1 to indirection_table_mask, but
it may overflow indirection_table_mask is UINT16_MAX. Check if
indirection_table_mask is small enough before adding 1.
Fixes: 590790297c0d ("virtio-net: implement RSS configuration command")
Signed-off-by: Akihiko Odaki
---
On Fri Sep 13, 2024 at 2:13 PM AEST, Harsh Prateek Bora wrote:
> Like p8 and p9, simplifying p7 exception handling rotuines to avoid
> un-necessary multiple indirect accesses to env->pending_interrupts and
> env->spr[SPR_LPCR].
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: Harsh Prateek Bora
On Fri Sep 13, 2024 at 2:13 PM AEST, Harsh Prateek Bora wrote:
> Most of the p8 exception handling accesses env->pending_interrupts and
> env->spr[SPR_LPCR] at multiple places. Passing it directly as local
> variables simplifies the code and avoids multiple indirect accesses.
Reviewed-by: Nicholas
On Fri Sep 13, 2024 at 2:13 PM AEST, Harsh Prateek Bora wrote:
> Historically, the registration of sprs have been inherited alongwith
> every new Power arch support being added leading to a lot of code
> duplication. It's time to do necessary cleanups now to avoid further
> duplication with newer a
On Fri Sep 13, 2024 at 2:13 PM AEST, Harsh Prateek Bora wrote:
> Like pending_interrupts, env->spr[SPR_LPCR] is being used at multiple
> places across p9 exception handlers. Pass the value during entry and
> avoid multiple indirect accesses.
Could this be merged with patch 4 to do pending_interrup
On Wed Sep 18, 2024 at 7:56 PM AEST, Ilya Leoshkevich wrote:
> On Mon, 2024-08-12 at 10:53 +0200, Ilya Leoshkevich wrote:
> > v1:
> > https://lore.kernel.org/qemu-devel/20240731100953.14950-1-...@linux.ibm.com/
> > v1 -> v2: Add R-bs and a targeted divd[u] patch.
> >
> > Hi,
> >
> > This series c
From: lxx <1733205...@qq.com>
This patch adds support for the Zilsd and Zclsd extension,
which is documented at https://github.com/riscv/riscv-zilsd/releases/tag/v0.10
Co-developed-by: SUN Dongya
Co-developed-by: LIU Xu
Co-developed-by: ZHAO Fujin
---
target/riscv/cpu.c
Hi Brian,
On 10/7/24 20:27, Brian Cain wrote:>>
Aside: Paolo, thanks for your work here!
Thanks to Manos, I am just the shepherd. :)
So far I think the focus for Rust support has been on device
models. But is there any interest in
being able to write TCG plugins in Rust
Is
On Tue, Oct 01, 2024 at 12:18:59AM +0200, Philippe Mathieu-Daudé wrote:
> Date: Tue, 1 Oct 2024 00:18:59 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH 1/2] hw/core/machine: Add missing 'units.h' and
> 'error-report.h' headers
> X-Mailer: git-send-email 2.45.2
>
> Include the missing "q
On Wed, Sep 25, 2024 8:58 PM Junjie Mao wrote:
> > As shown below, if a virtio PCI device is attached under a pci-bridge,
> > the MR of VirtIOPCIRegion does not belong to any address space. So
> > memory_region_find cannot be used to search for this MR.
> >
> > Introduce the virtio-pci and pci_br
On 10/7/2024 2:15 PM, Paolo Bonzini wrote:
Il lun 7 ott 2024, 19:56 Brian Cain ha scritto:
On 10/7/2024 6:03 AM, Paolo Bonzini wrote:
> The following changes since commit
b5ab62b3c0050612c7f9b0b4baeb44ebab42775a:
>
> Merge tag 'for-upstream' of https://gitlab.com/bonz
Ping.
> KVM commit 191c8137a939 ("x86/kvm: Implement HWCR support")
> introduced support for emulating HWCR MSR.
>
> Add support for QEMU to save/load this MSR for migration purposes.
>
> Signed-off-by: Gao Shiyuan
> ---
> target/i386/cpu.c | 1 +
> target/i386/cpu.h | 5 +
> target/i
On Fri, Oct 4, 2024 at 8:47 PM Yong-Xuan Wang wrote:
>
> The section 4.5.2 of the RISC-V AIA specification says that any write
> to a sourcecfg register of an APLIC might (or might not) cause the
> corresponding interrupt-pending bit to be set to one if the rectified
> input value is high (= 1) un
Hi Chuang.
Look fine for me, and only some minor nits:
On Mon, Oct 07, 2024 at 04:13:44PM +0800, Chuang Xu wrote:
> Date: Mon, 7 Oct 2024 16:13:44 +0800
> From: Chuang Xu
> Subject: [PATCH v4] i386/cpu: fixup number of addressable IDs for logical
> processors in the physical package
> X-Mailer
On Tue, Oct 1, 2024 at 11:37 PM Peter Xu wrote:
> On Tue, Oct 01, 2024 at 10:18:54AM +0800, Yong Huang wrote:
> > On Tue, Oct 1, 2024 at 4:47 AM Peter Xu wrote:
> >
> > > On Mon, Sep 30, 2024 at 01:14:28AM +0800, yong.hu...@smartx.com wrote:
> > > > From: Hyman Huang
> > > >
> > > > Currently,
On Tue, Oct 1, 2024 at 11:28 PM Peter Xu wrote:
> On Tue, Oct 01, 2024 at 10:02:53AM +0800, Yong Huang wrote:
> > On Tue, Oct 1, 2024 at 4:41 AM Peter Xu wrote:
> >
> > > On Mon, Sep 30, 2024 at 01:14:26AM +0800, yong.hu...@smartx.com wrote:
> > > > From: Hyman Huang
> > > >
> > > > When VM is
On Mon, Oct 07, 2024 at 02:33:39PM +0200, Igor Mammedov wrote:
> Date: Mon, 7 Oct 2024 14:33:39 +0200
> From: Igor Mammedov
> Subject: Re: [PATCH v4] i386/cpu: fixup number of addressable IDs for
> logical processors in the physical package
> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.43; x86_64-redhat
On Tue, Oct 1, 2024 at 2:53 AM Rob Bradford wrote:
>
> The RISC-V unprivileged specification "31.3.11. State of Vector
> Extension at Reset" has a note that recommends vtype.vill be set on
> reset as part of ensuring that the vector extension have a consistent
> state at reset.
>
> This change now
On Tue, Sep 3, 2024 at 12:14 AM Marc-André Lureau
wrote:
>
>
>
> On Tue, Aug 6, 2024 at 5:09 AM Octavian Purdila wrote:
>>
>> Add path option to the pty char backend which will create a symbolic
>> link to the given path that points to the allocated PTY.
>>
>> This avoids having to make QMP or HM
From: Jared Rossi
Because virtio-scsi type devices use a non-architected IPLB pbt code they cannot
be set and stored normally. Instead, the IPLB must be rebuilt during re-ipl.
As s390x does not natively support multiple boot devices, the devno field is
used to store the position in the boot orde
Add support for NXP's flexcomm usart. It supports interupts and FIFO
access but no DMA.
The patch includes an automatically generated header which contains
the register layout and helpers.
The header can be regenerated with the svd-flexcomm-usart target when
the build is configured with --enable-
From: Jared Rossi
Remove panic-on-error from virtio-scsi IPL specific functions so that error
recovery may be possible in the future.
Functions that would previously panic now provide a return code.
Signed-off-by: Jared Rossi
---
pc-bios/s390-ccw/bootmap.c | 88 +-
pc-b
Add a simple i2c peripheral to be used for testing I2C device
models. The peripheral has a fixed number of registers that can be
read and written.
Signed-off-by: Octavian Purdila
---
include/hw/misc/i2c_tester.h | 43 ++
hw/misc/i2c_tester.c | 109 +++
Add support for NXP's flexcomm i2c. It does not support slave mode or
DMA.
The patch includes an automatically generated header which contains
the register layout and helpers.
The header can be regenerated with the svd-flexcomm-i2c target when
the build is configured with --enable-mcux-soc-svd.
On Thu, Sep 19, 2024 at 3:53 PM LIU Zhiwei wrote:
>
> From: TANG Tiancheng
>
> This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus
> qemu-system-riscv64 can directly boot a RV32 Linux.
>
> This patch set has been tested with 6.9.0 Linux Image.
> And add an avocado tuxrun test in te
Add flexcomm function selection unit tests.
Signed-off-by: Octavian Purdila
---
tests/qtest/flexcomm-test.c | 82 +
tests/qtest/meson.build | 1 +
2 files changed, 83 insertions(+)
create mode 100644 tests/qtest/flexcomm-test.c
diff --git a/tests/qtest/
Add qtest APIs to check the device clock frequency.
Signed-off-by: Octavian Purdila
---
include/hw/qdev-clock.h | 10 +++
tests/qtest/libqtest-single.h | 24 +
tests/qtest/libqtest.h| 22 +++
hw/core/qdev-clock.c | 2 +-
system/qtest.c
From: Jared Rossi
Allow attempts to boot from multiple IPL devices. If the first device fails to
IPL, select the pre-built IPLB for the next device in the boot order and attempt
to IPL from it. Continue this process until IPL is successful or there are no
devices left to try.
Signed-off-by: Jare
From: Jared Rossi
Remove panic-on-error from Netboot specific functions so that error recovery
may be possible in the future.
Functions that would previously panic now provide a return code.
Signed-off-by: Jared Rossi
---
pc-bios/s390-ccw/s390-ccw.h | 2 +-
pc-bios/s390-ccw/bootmap.c|
From: Jared Rossi
Remove the information about the separate s390-netboot.img from
the documentation.
Co-authored by: Thomas Huth
Signed-off-by: Jared Rossi
---
docs/system/s390x/bootdevices.rst | 20 +++-
1 file changed, 7 insertions(+), 13 deletions(-)
diff --git a/docs/syst
Add basic support for the RT500 SoC. It supports enough peripherals to
run the NXP's microXpresso SDK hello world example.
The patch includes an automatically generated header which contains
peripheral base addreses and interrupt numbers.
The header can be regenerated with the svd-rt500 target wh
Add push/pop and peek tests for fifo32.
Signed-off-by: Octavian Purdila
---
tests/unit/test-fifo.c | 50 ++
1 file changed, 50 insertions(+)
diff --git a/tests/unit/test-fifo.c b/tests/unit/test-fifo.c
index 14153c41fa..d0e05ba95c 100644
--- a/tests/unit/
It supports system and audio PLL initialization and SYSTICK and
OSTIMER clock source selection.
The patch includes automatically generated headers which contains the
register layout and helpers.
The headers can be regenerated with the svd-rt500-clkctl0 and
svd-rt500-clkctl1 targets when the build
From: Jared Rossi
Remove panic-on-error from DASD IPL specific functions so that error recovery
may be possible in the future.
Functions that would previously panic now provide a return code.
Signed-off-by: Jared Rossi
Reviewed-by: Thomas Huth
---
pc-bios/s390-ccw/dasd-ipl.h | 2 +-
pc-bios
Add a simple SPI peripheral that echoes back received data. Useful for
testing SPI controllers.
Signed-off-by: Octavian Purdila
---
include/hw/misc/spi_tester.h | 32 +
hw/misc/spi_tester.c | 67
hw/misc/Kconfig | 5 +++
Add basic support for the RT595-EVK board, enough to be able to run
the NXP's microXpresso SDK hello world example.
Signed-off-by: Octavian Purdila
---
hw/arm/rt595-evk.c | 64 ++
hw/arm/Kconfig | 5
hw/arm/meson.build | 1 +
3 files changed
Add flexcomm usart polling and irq unit tests.
Signed-off-by: Octavian Purdila
---
tests/qtest/flexcomm-usart-test.c | 316 ++
tests/qtest/meson.build | 3 +-
2 files changed, 318 insertions(+), 1 deletion(-)
create mode 100644 tests/qtest/flexcomm-usart-
Add read*/write*_fail qtest APIs to check for memory access failures.
Signed-off-by: Octavian Purdila
---
tests/qtest/libqtest-single.h | 92 +++
tests/qtest/libqtest.h| 76 +
system/qtest.c| 44 ++---
From: Jared Rossi
Currently, structures defined in both hw/s390x/ipl.h and pc-bios/s390-ccw/iplb.h
must be kept in sync, which is prone to error. Instead, create a new directory
at include/hw/s390x/ipl/ to contain the definitions that must be shared.
Signed-off-by: Jared Rossi
Reviewed-by: Thom
Signed-off-by: Octavian Purdila
---
hw/ssi/ssi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c
index 3f357e8f16..d1f3ce7c22 100644
--- a/hw/ssi/ssi.c
+++ b/hw/ssi/ssi.c
@@ -105,7 +105,9 @@ static void ssi_peripheral_realize(DeviceState *dev, Er
The RT500 reset controller has two instances that have the same
register layout but with different fields for some registers.
The model only provides set and clear functionality for the various
reset lines which is common for both instances. Because of that only
one type is implemented for both co
Add test to exercise clocks set and clear, system PLL initialization,
audio PLL initialization, systick and ostimer clock source selection.
Signed-off-by: Octavian Purdila
---
tests/qtest/rt500-clkctl-test.c | 195
tests/qtest/meson.build | 1 +
2 files
Add utility macros for accessing register or register bit fields in
tests, e.g.:
REG32_WRITE(FLEXCOMM, PSELID, persel);
g_assert(REG32_READ_FIELD(FLEXCOMM, PSELID, PERSEL) == persel);
Signed-off-by: Octavian Purdila
---
tests/qtest/reg-utils.h | 70 +
From: Sebastian Ene
Add master and loopback tests for flexcomm spi.
Signed-off-by: Sebastian Ene
[tavip: add master mode test, convert to qtest]
Signed-off-by: Octavian Purdila
---
tests/qtest/flexcomm-spi-test.c | 145
tests/qtest/meson.build | 2 +-
Add mcux-soc-svd subproject that contains SVD files that are going to
be used to generate C header with register layout definitions and
other helpers to create device models.
Guard the subproject by a configuration option since it is rarely
going to be used - whenever new headers will be generated
Add master mode tests for flexcomm i2c.
Signed-off-by: Octavian Purdila
---
tests/qtest/flexcomm-i2c-test.c | 170
tests/qtest/meson.build | 2 +-
2 files changed, 171 insertions(+), 1 deletion(-)
create mode 100644 tests/qtest/flexcomm-i2c-test.c
dif
From: Jared Rossi
Add two new qtests to verify that a valid IPL device can successfully boot after
failed IPL attempts from one or more invalid devices.
cdrom-test/as-fallback-device: Defines the primary boot target as a device that
is invalid for IPL and a second boot target that is valid for I
From: Jared Rossi
Update docs to show that s390x PC BIOS can support more than one boot device.
Signed-off-by: Jared Rossi
---
docs/system/bootindex.rst | 7 ---
docs/system/s390x/bootdevices.rst | 9 ++---
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/docs/sy
From: Sebastian Ene
Add support for NXP's flexcomm spi. It supports FIFO access,
interrupts and master mode only. It does not support DMA.
The patch includes an automatically generated header which contains
the register layout and helpers.
The header can be regenerated with the svd-flexcomm-spi
Add support for NXP's FLEXCOMM device model.
FLEXCOMM is a generic serial communication module which support
multiple functions: UART, SPI and I2C. These are configurable at
runtime.
An abstract FlexcomFunction class is created that will be extended for
specific functions. Each function has a ded
This patch set adds support for NXP's RT500 MCU [1] and the RT595
EVK[2]. More RT500 device models will be submitted in future patch sets.
This is a minimal patch set that allows running the NXP MCU SDK hello
world example[4].
The patch set introduces a (python) tool that generates C header files
From: Jared Rossi
Remove panic-on-error from IPL functions such that a return code is propagated
back to the main IPL calling function (rather than terminating immediately),
which facilitates possible error recovery in the future.
A select few panics remain, which indicate fatal non-devices erro
FLEXCOMM SPI and USART share FIFO functionality. Add common helper
functions to avoid code duplication.
Signed-off-by: Octavian Purdila
---
include/hw/misc/flexcomm.h | 2 +
include/hw/misc/flexcomm_function.h | 8 +++
hw/misc/flexcomm.c | 83 +
This is mostly a stub which completes SPI transactions as noops
by masking out the error interrupts and never clearing the IPCMDDONE
interrupt.
Although incomplete, this allows software that uses NXP's mcuxpresso
SDK to run the SDK board initialization functions.
It also supports AHB memory acces
From: Jared Rossi
Remove panic-on-error from ECKD block device IPL specific functions so that
error recovery may be possible in the future.
Functions that would previously panic now provide a return code.
Signed-off-by: Jared Rossi
---
pc-bios/s390-ccw/s390-ccw.h | 1 +
pc-bios/s390-ccw/boo
Add fifo32_peek() that returns the first element from the queue
without popping it.
Signed-off-by: Octavian Purdila
---
include/qemu/fifo32.h | 28
1 file changed, 28 insertions(+)
diff --git a/include/qemu/fifo32.h b/include/qemu/fifo32.h
index 4e9fd1b5ef..9de18073
From: Jared Rossi
We are already using the libc from SLOF for the s390-netboot.img, and
this libc implementation is way more complete and accurate than the
simple implementation that we currently use for the s390-ccw.img binary.
Since we are now always assuming that the SLOF submodule is availabl
From: Stefan Stanacar
The CMSIS System View Description format(CMSIS-SVD) is an XML based
description of Arm Cortex-M microcontrollers provided and maintained
by sillicon vendors. It includes details such as peripherals registers
(down to bitfields), peripheral register block addresses, reset
val
From: Jared Rossi
Build an IPLB for any device with a bootindex (up to a maximum of 8 devices).
The IPLB chain is placed immediately before the BIOS in memory. Because this
is not a fixed address, the location of the next IPLB and number of remaining
boot devices is stored in the QIPL global var
From: Jared Rossi
Since the netboot code has now been merged into the main s390-ccw.img
binary, we don't need the separate s390-netboot.img anymore. Remove
it and the code that was responsible for loading it.
Co-authored by: Thomas Huth
Signed-off-by: Jared Rossi
---
hw/s390x/ipl.h
From: Jared Rossi
Version 3 fixes ISO IPL and restores the ability to probe for boot devices when
no primary b0ot device has been specified.
Two automated qtests are added, one that tests a cdrom device as the only
fallback device after the primary boot target fails and one that that defines
the
From: Jared Rossi
Now that the netboot code has been merged into the main s390-ccw.img,
it also does not make sense to keep the build rules in a separate
file. Thus let's merge netboot.mak into the main Makefile.
Co-authored by: Thomas Huth
Signed-off-by: Jared Rossi
---
pc-bios/s390-ccw/netb
From: Jared Rossi
Add a loadparm property to the VirtioCcwDevice object so that different
loadparms can be defined on a per-device basis for CCW boot devices.
The machine/global loadparm is still supported. If both a global and per-device
loadparm are defined, the per-device value will override
From: Jared Rossi
We originally built a separate binary for the netboot code since it
was considered as experimental and we could not be sure that the
necessary SLOF module had been checked out. Time passed, the code
proved its usefulness, and the build system nowadays makes sure that
the SLOF mo
From: Jared Rossi
Remove panic-on-error from IPL ISO El Torito specific functions so that error
recovery may be possible in the future.
Functions that would previously panic now provide a return code.
Signed-off-by: Jared Rossi
---
pc-bios/s390-ccw/bootmap.h | 15 +++
pc-bios/s390-ccw/s3
From: Jared Rossi
We are going to link the SLOF libc into the s390-ccw.img, and this
libc needs more memory for providing space for malloc() and friends.
Thus bump the memory size that we reserve for the bios to 3 MiB
instead of only 2 MiB. While we're at it, add a proper check that
there is real
On Thu, Sep 19, 2024 at 3:57 PM LIU Zhiwei wrote:
>
> make check-avocado AVOCADO_TESTS=tests/avocado/tuxrun_baselines.py: \
> TuxRunBaselineTest:test_riscv64_rv32
>
> Signed-off-by: LIU Zhiwei
> Suggested-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Alistair
> ---
> tests/avocado/
On Thu, Sep 19, 2024 at 3:56 PM LIU Zhiwei wrote:
>
> We may need 32-bit max for RV64 QEMU. Thus we add these two CPUs
> for RV64 QEMU.
>
> The reason we don't expose them to RV32 QEMU is that we already have
> max cpu with the same configuration. Another reason is that we want
> to follow the RIS
On Thu, Sep 19, 2024 at 1:34 AM Peter Maydell wrote:
>
> On Wed, 18 Sept 2024 at 14:49, Heinrich Schuchardt
> wrote:
> >
> > On 18.09.24 15:12, Peter Maydell wrote:
> > > On Wed, 18 Sept 2024 at 14:06, Heinrich Schuchardt
> > > wrote:
> > >> Thanks Peter for looking into this.
> > >>
> > >> QEMU
On 10/7/2024 6:51 AM, Eugenio Perez Martin wrote:
On Fri, Oct 4, 2024 at 8:48 PM Jonah Palmer wrote:
On 10/4/24 11:17 AM, Eugenio Perez Martin wrote:
On Fri, Oct 4, 2024 at 2:45 PM Jonah Palmer wrote:
Implements the IOVA->GPA tree for handling mapping, unmapping, and
translations for gu
According to include/qapi/error.h:
* Please don't error_setg(&error_fatal, ...), use error_report() and
* exit(), because that's more obvious.
Patch updates all instances of error_setg(&error_fatal, ...) with
error_report(...), adds the explicit exit(1) and removes redundant
return statements.
Si
On Mon, 7 Oct 2024, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Avoid use of uninitialized bufioreq_evtchn. It should only
> be used if buffered IOREQs are enabled.
>
> Resolves: Coverity CID 1563383
> Reported-by: Peter Maydell
> Signed-off-by: Edgar E. Iglesias
Acked-by: Stefan
On 5/10/24 12:25, Richard Henderson wrote:
Just add the argument, unused at this point.
Zero is the safe do-nothing value for all callers.
Signed-off-by: Richard Henderson
---
target/hppa/cpu.h| 2 +-
target/hppa/int_helper.c | 2 +-
target/hppa/mem_helper.c | 9 +
target/h
On 10/5/24 22:05, Richard Henderson wrote:
Fill in the tlb_fill_align hook. So far this is the same
as tlb_fill_align_first, except that we can pass memop to
get_phys_addr as well.
Signed-off-by: Richard Henderson
Reviewed-by: Helge Deller
---
target/arm/internals.h | 3 +++
ta
On 10/5/24 22:05, Richard Henderson wrote:
Determine cache attributes, and thence Device vs Normal memory,
"thence" ?
Other than that I have no arm knowledge to review the patch below
Helge
earlier in the function. We have an existing regime_is_stage2
if block into which this can be sl
On 5/10/24 12:25, Richard Henderson wrote:
Drop the 'else' so that ret is overridden with the
highest priority fault.
Signed-off-by: Richard Henderson
---
target/hppa/mem_helper.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
Fixes: d8bc1381250 ("target/hppa: Implement PSW_
On 10/5/24 22:05, Richard Henderson wrote:
Pass memop through get_phys_addr_twostage with its
recursion with get_phys_addr_nogpc.
Signed-off-by: Richard Henderson
Reviewed-by: Helge Deller
---
target/arm/ptw.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
On 10/5/24 22:05, Richard Henderson wrote:
Pass the value through from get_phys_addr_nogpc.
Signed-off-by: Richard Henderson
Reviewed-by: Helge Deller
---
target/arm/ptw.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
On 5/10/24 12:25, Richard Henderson wrote:
Pass the value through from get_phys_addr_nogpc.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 5/10/24 12:25, Richard Henderson wrote:
Pass memop through get_phys_addr_twostage with its
recursion with get_phys_addr_nogpc.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 10/5/24 22:05, Richard Henderson wrote:
Zero is the safe do-nothing value for callers to use.
Pass the value through from get_phys_addr_gpc and
get_phys_addr_with_space_nogpc.
Signed-off-by: Richard Henderson
Reviewed-by: Helge Deller
---
target/arm/ptw.c | 14 --
1 fil
On 5/10/24 12:25, Richard Henderson wrote:
Zero is the safe do-nothing value for callers to use.
Pass the value through from get_phys_addr_gpc and
get_phys_addr_with_space_nogpc.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 14 --
1 file changed, 8 insertions(+), 6 del
On 5/10/24 12:25, Richard Henderson wrote:
Zero is the safe do-nothing value for callers to use.
Pass the value through from get_phys_addr.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
Reviewed-by: Philippe Mathieu-
On 10/5/24 22:05, Richard Henderson wrote:
Zero is the safe do-nothing value for callers to use.
Signed-off-by: Richard Henderson
Reviewed-by: Helge Deller
---
target/arm/internals.h | 3 ++-
target/arm/helper.c| 4 ++--
target/arm/ptw.c | 2 +-
3 files changed, 5 insertion
On 10/5/24 22:05, Richard Henderson wrote:
Zero is the safe do-nothing value for callers to use.
Pass the value through from get_phys_addr.
Signed-off-by: Richard Henderson
Reviewed-by: Helge Deller
---
target/arm/ptw.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
On 5/10/24 12:25, Richard Henderson wrote:
Zero is the safe do-nothing value for callers to use.
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 3 ++-
target/arm/helper.c| 4 ++--
target/arm/ptw.c | 2 +-
3 files changed, 5 insertions(+), 4 deletions(-)
Reviewed-
On 5/10/24 12:25, Richard Henderson wrote:
Zero is the safe do-nothing value for callers to use.
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 3 ++-
target/arm/ptw.c| 2 +-
target/arm/tcg/m_helper.c | 8
target/arm/tcg/tlb_helper.c | 2 +-
4 fi
On 10/5/24 22:05, Richard Henderson wrote:
Zero is the safe do-nothing value for callers to use.
Signed-off-by: Richard Henderson
Reviewed-by: Helge Deller
---
target/arm/internals.h | 3 ++-
target/arm/ptw.c| 2 +-
target/arm/tcg/m_helper.c | 8
target/ar
On 10/5/24 22:05, Richard Henderson wrote:
Fill in the tlb_fill_align hook, so that we can recognize
alignment exceptions in the correct priority order.
Signed-off-by: Richard Henderson
Reviewed-by: Helge Deller
---
target/hppa/cpu.h| 3 +++
target/hppa/cpu.c| 2 +-
On 10/5/24 22:05, Richard Henderson wrote:
In Chapter 5, Interruptions, the group 3 exceptions lists
"Unaligned data reference trap" has higher priority than
"Data memory break trap".
Signed-off-by: Richard Henderson
Reviewed-by: Helge Deller
---
target/hppa/mem_helper.c | 7 ++-
1
On 5/10/24 12:25, Richard Henderson wrote:
Rename to use "memop_" prefix, like other functions
that operate on MemOp.
Signed-off-by: Richard Henderson
---
include/exec/memop.h | 4 ++--
accel/tcg/cputlb.c | 4 ++--
accel/tcg/user-exec.c | 4 ++--
target/arm/t
On 5/10/24 12:25, Richard Henderson wrote:
This function is specific to MemOp, not TCG in general.
Signed-off-by: Richard Henderson
---
include/exec/memop.h | 23 +++
include/tcg/tcg.h| 23 ---
2 files changed, 23 insertions(+), 23 deletions(-)
From: "Edgar E. Iglesias"
This has a fix for Coverity CID 1563383 reported by Peter.
Avoid use of uninitialized bufioreq_evtchn. It should only
be used if buffered IOREQs are enabled.
Cheers,
Edgar
Edgar E. Iglesias (1):
hw/xen: Avoid use of uninitialized bufioreq_evtchn
hw/xen/xen-hvm-com
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