On 24/09/2024 16.12, Peter Krempa wrote:
On Tue, Sep 24, 2024 at 15:24:51 +0200, Thomas Huth wrote:
According to https://marc.info/?l=fedora-devel-list&m=171934833215726
the GlusterFS development effectively ended. Thus mark it as deprecated
in QEMU, so we can remove it in a future release if th
The status and mstatus CSRs contain bit field FS, which control if the
floating point unit of RISC-V hart is enabled.
There seems to be no specification prescribing the value of the field when
entering S-mode from M-mode. But OpenSBI, as the leading SBI M-mode
firmware, has set a precedent by enab
Em Tue, 24 Sep 2024 15:14:29 +0200
Igor Mammedov escreveu:
> > 1) preparation patches:
...
> > 69850f550f99 acpi/generic_event_device: add an APEI error device
> this one doesn't belong to clean ups, I think.
> Lets move this to #3 part
Ok.
> > The migration logic will require some time, and
On 9/23/24 18:12, Ilya Leoshkevich wrote:
Hi,
On reporting a breakpoint in a non-non-stop mode, GDB remotes must stop
all threads. Currently qemu-user doesn't do that, breaking the
debugging session for at least two reasons: concurrent access to the
GDB socket, and an assertion within GDB [1].
Instead, produce an error and continue working
Signed-off-by: Mauro Carvalho Chehab
---
hw/acpi/ghes.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c
index 3af1cd16d4d7..209095f67e9a 100644
--- a/hw/acpi/ghes.c
+++ b/hw/acpi/ghes.c
@@ -418
Reduce the ident of the function and prepares it for
the next changes.
No functional changes.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Igor Mammedov
---
hw/acpi/ghes.c | 56 ++
1 file changed, 29 insertions(+), 27 deletions(-)
diff --gi
The hardware error firmware is where HEST error structures are
stored. Those can be GHESv2, but they can also be other types.
Better name the location of the hardware error.
No functional changes.
Signed-off-by: Mauro Carvalho Chehab
---
hw/acpi/generic_event_device.c | 4 ++--
hw/acpi/ghes.c
Currently, CPER address location is calculated as an offset of
the hardware_errors table. It is also badly named, as the
offset actually used is the address where the CPER data starts,
and not the beginning of the error source.
Move the logic which calculates such offset to a separate
function, in
GHES has two fields that are stored on HEST error source
blocks:
- notification type, which is a number defined at the ACPI spec
containing several arch-specific synchronous and assynchronous
types;
- source id, which is a HW/FW defined number, used to distinguish
between different implement
While the spec defines a CPER size of 4KiB for each record,
currently it is set to 1KiB. Fix the documentation and add
a pointer to the macro name there, as this may help to keep
it updated.
Signed-off-by: Mauro Carvalho Chehab
Acked-by: Igor Mammedov
---
docs/specs/acpi_hest_ghes.rst | 6 -
The first argument is source ID and not notification type.
Signed-off-by: Mauro Carvalho Chehab
---
Changes from v8:
- Non-rename/cleanup changes merged altogether;
- source ID is now more generic, defined per guest target.
That should make easier to add support for 86.
Signed-off-by: Mauro
Now that we have also have a file to store HEST data location,
which is part of GHES, better name the file where CPER records
are stored.
No functional changes.
Reviewed-by: Igor Mammedov
Signed-off-by: Mauro Carvalho Chehab
---
hw/acpi/ghes.c | 32 +++-
1 file chan
The current code is actually dependent on having just one
error structure with a single source.
As the number of sources should be arch-dependent, as it
will depend on what kind of synchronous/assynchronous
notifications will exist, change the logic to dynamically
build the table.
Yet, for a prop
Split the code into separate functions to allow using the
common CPER filling code by different error sources.
The generic code was moved to ghes_record_cper_errors(),
and ghes_gen_err_data_uncorrectable_recoverable() now contains
only a logic to fill GEGB part of the record.
The remaining code t
HEST source ID is actually a 16-bit value
Signed-off-by: Mauro Carvalho Chehab
---
hw/acpi/ghes-stub.c| 2 +-
hw/acpi/ghes.c | 2 +-
include/hw/acpi/ghes.h | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/acpi/ghes-stub.c b/hw/acpi/ghes-stub.c
index c315de180
The GHES driver requires not only a HEST table, but also a
separate firmware file to store Error Structure records.
It can't do one without the other.
Simplify the caller logic for it to require one function.
This prepares for further changes where the HEST table
generation will become more gener
acpi_ghes_record_errors() has an assert() at the beginning
to ensure that source_id will be lower than
ACPI_GHES_ERROR_SOURCE_COUNT. Remove a duplicated check.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Igor Mammedov
---
hw/acpi/ghes.c | 4 +---
1 file changed, 1 insertion(+), 3 deletion
The current function used to generate GHES data is specific for
memory errors. Give a better name for it, as we now have a generic
function as well.
Reviewed-by: Igor Mammedov
Signed-off-by: Mauro Carvalho Chehab
---
hw/acpi/ghes-stub.c| 2 +-
hw/acpi/ghes.c | 2 +-
include/hw/acpi/
During the development of a patch series meant to allow GHESv2 error injections,
it was requested a change on how CPER offsets are calculated, by adding a new
BIOS pointer and reworking the GHES logic. See:
https://lore.kernel.org/qemu-devel/cover.1726293808.git.mchehab+hua...@kernel.org/
Such ch
This is just duplicating ACPI_GHES_ERROR_SOURCE_COUNT, which
has a better name. So, drop the duplication.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Igor Mammedov
---
hw/acpi/ghes.c | 7 ++-
include/hw/acpi/ghes.h | 3 ++-
2 files changed, 4 insertions(+), 6 deletions(-)
dif
AST2700 integrates two set of Parallel GPIO Controller
with maximum 212 control pins, which are 27 groups.
(H, exclude pin: H7 H6 H5 H4)
In the previous design of ASPEED SOCs,
one register is used for setting one function for one set which are 32 pins
and 4 groups.
ex: GPIO000 is used for setting
According to the datasheet of ASPEED SOCs,
a GPIO controller owns 4KB of register space for AST2700,
AST2500, AST2400 and AST1030; owns 2KB of register space
for AST2600 1.8v and owns 2KB of register space for AST2600 3.3v.
It set the memory region size 2KB by default and it does not compatible
re
Add GPIO model for AST2700 GPIO support.
The GPIO controller registers base address is start at
0x14C0_B000 and its address space is 0x1000.
The AST2700 GPIO controller interrupt is connected to
GICINT130_INTC at bit 18.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 18 +++-
The interrupt status field is W1C, where a set bit on read indicates an
interrupt is pending. If the bit extracted from data is set it should
clear the corresponding bit in group_value. However, if the extracted
bit is clear then the value of the corresponding bit in group_value
should be unchanged
It set "aspeed_gpio_ops" struct which containing
read and write callbacks to be used when I/O is performed
on the GPIO region.
Besides, in the previous design of ASPEED SOCs,
one register is used for setting one function for 32 GPIO pins.
ex: GPIO000 is used for setting data value for GPIO A, B, C
Fix coding style issues from checkpatch.pl
Signed-off-by: Jamin Lin
---
hw/gpio/aspeed_gpio.c | 5 +++--
include/hw/gpio/aspeed_gpio.h | 2 +-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
index 71756664dd..a5886ffa43 100644
v1: Support GPIO for AST2700
v2: Fix clear incorrect interrupt status and adds reviewer suggestion
Jamin Lin (6):
hw/gpio/aspeed: Fix coding style
hw/gpio/aspeed: Support to set the different memory size
hw/gpio/aspeed: Support different memory region ops
hw/gpio/aspeed: Fix clear incorrec
Hi Andrew,
> Subject: Re: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support
>
> On Tue, 2024-09-24 at 03:03 +, Jamin Lin wrote:
> > Hi Andrew,
> >
> > > Subject: Re: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support
> > >
> > > Hi Jamin,
> > >
> > > On Mon, 2024-09-23 at 17:42 +0800, Jamin Lin w
Hi Andrew,
> Subject: Re: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support
>
> On Tue, 2024-09-24 at 06:48 +, Jamin Lin wrote:
> > Hi Andrew,
> >
> > > Subject: RE: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support
> > >
> > > Hi Andrew,
> > >
> > > > Subject: Re: [PATCH 4/5] hw/gpio/aspeed: Add
On Sun, Sep 22, 2024 at 09:24:33PM +0800, Chao Liu wrote:
> Signed-off-by: Chao Liu
Reviewed-by: Edgar E. Iglesias
> ---
> hw/dma/xlnx-zynq-devcfg.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c
> index b8544d0
On Tue, 2024-09-24 at 06:48 +, Jamin Lin wrote:
> Hi Andrew,
>
> > Subject: RE: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support
> >
> > Hi Andrew,
> >
> > > Subject: Re: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support
> > >
> > > Hi Jamin,
> > >
> > >
> > > > +}
> > > > +set->int_
On Tue, 2024-09-24 at 03:03 +, Jamin Lin wrote:
> Hi Andrew,
>
> > Subject: Re: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support
> >
> > Hi Jamin,
> >
> > On Mon, 2024-09-23 at 17:42 +0800, Jamin Lin wrote:
> >
> > > +
> > > +/* interrupt status */
> > > +group_value = set->int_statu
On Mon, 23 Sep 2024, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Add a way to enable/disable buffered IOREQs for PVH machines
> and disable them for ARM. ARM does not support buffered
> IOREQ's nor the legacy way to map IOREQ info pages.
>
> See the following for more details:
> htt
On Sun, Sep 22, 2024 at 02:31:08PM +, Ricardo Ribalda wrote:
> Mark Cave-Ayland reported that after landing the pre-computed _PRT, the
> above mentioned testcase failed to pass.
>
> It seems that it is due to WinXP not handling properly a variable
> package. Let's replace it.
Thanks, will me
On Mon, 23 Sep 2024, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Expose handle_bufioreq in xen_register_ioreq().
> This is to allow machines to enable or disable buffered ioreqs.
>
> No functional change since all callers still set it to
> HVM_IOREQSRV_BUFIOREQ_ATOMIC.
>
> Signed-o
From: Daniel Henrique Barboza
Gitlab issue [1] reports a misleading error when trying to run a 'rv64'
cpu with 'zfinx' and without 'f':
$ ./build/qemu-system-riscv64 -nographic -M virt -cpu rv64,zfinx=true,f=false
qemu-system-riscv64: Zfinx cannot be supported together with F extension
The user
From: Warner Losh
Added a generic definition for RISC-V64 target-specific details.
Implemented the 'regpairs_aligned' function,which returns 'false'
to indicate that register pairs are not aligned in the RISC-V64 ABI.
Signed-off-by: Warner Losh
Signed-off-by: Ajeet Singh
Reviewed-by: Richard H
From: Mark Corbin
Added functions for setting up the RISC-V signal trampoline and signal
frame:
'set_sigtramp_args()': Configures the RISC-V CPU state with arguments
for the signal handler. It sets up the registers with the signal
number,pointers to the signal info and user context, the signal h
From: Milan P. Stanić
build fails on musl libc (alpine linux) with this error:
../util/cpuinfo-riscv.c: In function 'cpuinfo_init':
../util/cpuinfo-riscv.c:63:21: error: '__NR_riscv_hwprobe' undeclared (first
use in this function); did you mean 'riscv_hwprobe'?
63 | if (syscall(__NR_
From: Mark Corbin
Added the initial implementation for RISC-V CPU initialization and main
loop. This includes setting up the general-purpose registers and
program counter based on the provided target architecture definitions.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Co-authored-by
From: Mark Corbin
Added the 'get_mcontext' function to extract and populate
the RISC-V machine context from the CPU state.
This function is used to gather the current state of the
general-purpose registers and store it in a 'target_mcontext_'
structure.
Signed-off-by: Mark Corbin
Signed-off-by:
From: Alvin Chang
This commit allows program to write textra trigger CSR for type 2, 3, 6
triggers. In this preliminary patch, the textra.MHVALUE and the
textra.MHSELECT fields are allowed to be configured. Other fields, such
as textra.SBYTEMASK, textra.SVALUE, and textra.SSELECT, are hardwired t
From: Andrew Jones
C doesn't extend the sign bit for unsigned types since there isn't a
sign bit to extend. This means a promotion of a u32 to a u64 results
in the upper 32 bits of the u64 being zero. If that result is then
used as a mask on another u64 the upper 32 bits will be cleared. rv32
phy
From: Alexandre Ghiti
The Svvptc extension describes a uarch that does not cache invalid TLB
entries: that's the case for qemu so there is nothing particular to
implement other than the introduction of this extension.
Since qemu already exposes Svvptc behaviour, let's enable it by default
since
From: Mark Corbin
Added definitions for RISC-V register structures, including
general-purpose registers and floating-point registers, in
'target_arch_reg.h'. Implemented the 'target_copy_regs' function to
copy register values from the CPU state to the target register
structure, ensuring proper en
From: Mark Corbin
Added definitions for RISC-V VM parameters, including maximum and
default sizes for text, data, and stack, as well as address space
limits.
Implemented helper functions for retrieving and setting specific
values in the CPU state, such as stack pointer and return values.
Signed-
From: Mark Corbin
Included the prototype for the 'target_cpu_set_tls' function in the
'target_arch.h' header file. This function is responsible for setting
the Thread Local Storage (TLS) register for RISC-V architecture.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed-by: Richar
From: Tomasz Jeznach
The RISC-V IOMMU spec predicts that the IOMMU can use translation caches
to hold entries from the DDT. This includes implementation for all cache
commands that are marked as 'not implemented'.
There are some artifacts included in the cache that predicts s-stage and
g-stage e
From: Mark Corbin
Implemented the 'setup_sigtramp' function for setting up the signal
trampoline code in the RISC-V architecture.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed-by: Richard Henderson
Message-ID: <20240916155119.14610-8-itac...@freebsd.org>
Signed-off-by: Alista
From: Mark Corbin
Added definitions for RISC-V signal handling, including structures
and constants for managing signal frames and context
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Co-authored-by: Warner Losh
Reviewed-by: Richard Henderson
Message-ID: <20240916155119.14610-14-itac
From: Mark Corbin
Introduced definitions for the RISC-V system call interface, including
the 'target_pt_regs' structure that outlines the register storage
layout during a system call.
Added constants for hardware machine identifiers.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Co-aut
From: Daniel Henrique Barboza
Add an additional test to further exercise the IOMMU where we attempt to
initialize the command, fault and page-request queues.
These steps are taken from chapter 6.2 of the RISC-V IOMMU spec,
"Guidelines for initialization". It emulates what we expect from the
soft
From: Mark Corbin
Added functions for cloning CPU registers and resetting the CPU state
for RISC-V architecture.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed-by: Richard Henderson
Message-ID: <20240916155119.14610-4-itac...@freebsd.org>
Signed-off-by: Alistair Francis
---
From: Tomasz Jeznach
DBG support adds three additional registers: tr_req_iova, tr_req_ctl and
tr_response.
The DBG cap is always enabled. No on/off toggle is provided for it.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by: Alistair F
From: Mark Corbin
Implemented functions for setting up and initializing threads in the
RISC-V architecture.
The 'target_thread_set_upcall' function sets up the stack pointer,
program counter, and function argument for new threads.
The 'target_thread_init' function initializes thread registers bas
From: Mark Corbin
Added implementations for 'set_mcontext' and 'get_ucontext_sigreturn'
functions for RISC-V architecture,
Both functions ensure that the CPU state and user context are properly
managed.
Signed-off-by: Mark Corbin
Signed-off-by: Warner Losh
Signed-off-by: Ajeet Singh
Co-author
From: Mark Corbin
Added the 'do_freebsd_arch_sysarch' function to emulate the 'sysarch'
system call for the RISC-V architecture.
Currently, this function returns '-TARGET_EOPNOTSUPP' to indicate that
the operation is not supported.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed
From: Mark Corbin
Introduced RISC-V specific ELF definitions and hardware capability
detection.
Additionally, a function to retrieve hardware capabilities
('get_elf_hwcap') is implemented, which returns the common bits set in
each CPU's ISA strings.
Signed-off-by: Mark Corbin
Signed-off-by: Aje
From: Haibo Xu
As per the step 5 in the process documented in bios-tables-test.c,
generate the expected ACPI SRAT AML data file for RISC-V using the
rebuild-expected-aml.sh script and update the
bios-tables-test-allowed-diff.h.
This is a new file being added for the first time. Hence, iASL diff
From: Warner Losh
Added configuration for RISC-V 64-bit target to the build system.
Signed-off-by: Warner Losh
Signed-off-by: Ajeet Singh
Reviewed-by: Richard Henderson
Message-ID: <20240916155119.14610-18-itac...@freebsd.org>
Signed-off-by: Alistair Francis
---
configs/targets/riscv64-bsd-
From: Daniel Henrique Barboza
The RISC-V IOMMU PCI device we're going to add next is a reference
implementation of the riscv-iommu spec [1], which predicts that the
IOMMU can be implemented as a PCIe device.
However, RISC-V International (RVI), the entity that ratified the
riscv-iommu spec, didn
From: Thomas Huth
If QEMU has been configured with "--without-default-devices", the build
is currently failing with:
/usr/bin/ld: libqemu-riscv32-softmmu.a.p/target_riscv_cpu_helper.c.o:
in function `riscv_cpu_do_interrupt':
.../qemu/target/riscv/cpu_helper.c:1678:(.text+0x2214): undefined
From: Andrew Jones
While the spec doesn't state it, setting timecmp to UINT64_MAX is
another way to stop a timer, as it's considered setting the next
timer event to occur at infinity. And, even if the time CSR does
eventually reach UINT64_MAX, the very next tick will bring it back to
zero, once a
From: Haibo Xu
Add ACPI SRAT table test case for RISC-V when NUMA was enabled.
Signed-off-by: Haibo Xu
Reviewed-by: Sunil V L
Acked-by: Alistair Francis
Message-ID:
Signed-off-by: Alistair Francis
---
tests/qtest/bios-tables-test.c | 28
1 file changed, 28 ins
From: Haibo Xu
As per process documented (steps 1-3) in bios-tables-test.c, add
empty AML data file for RISC-V ACPI SRAT table and add the entry
in bios-tables-test-allowed-diff.h.
Signed-off-by: Haibo Xu
Reviewed-by: Sunil V L
Acked-by: Alistair Francis
Message-ID:
<0e30216273f2f59916bc6513
From: Andrew Jones
Just as the hart bit setting of the AIA should be calculated as
ceil(log2(max_hart_id + 1)) the group bit setting should be
calculated as ceil(log2(max_group_id + 1)). The hart bits are
implemented by passing max_hart_id to find_last_bit() and adding
one to the result. Do the s
From: Tomasz Jeznach
The RISC-V IOMMU specification is now ratified as-per the RISC-V
international process. The latest frozen specifcation can be found at:
https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf
Add the foundation of the device emulation for RISC-V
From: Tomasz Jeznach
Extend memory transaction attributes with process identifier to allow
per-request address translation logic to use requester_id / process_id
to identify memory mapping (e.g. enabling IOMMU w/ PASID translations).
Signed-off-by: Tomasz Jeznach
Reviewed-by: Frank Chang
Revie
From: Alistair Francis
The OpenTitan Ibex CPU now supports the the Zba, Zbb, Zbc
and Zbs bit-manipulation sub-extensions ratified in
v.1.0.0 of the RISC-V Bit- Manipulation ISA Extension, so let's enable
them in QEMU as well.
1: https://github.com/lowRISC/opentitan/pull/9748
Signed-off-by: Alis
From: Tomasz Jeznach
Generate device tree entry for riscv-iommu PCI device, along with
mapping all PCI device identifiers to the single IOMMU device instance.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by: Alistair Francis
Message-I
From: Tomasz Jeznach
This header will be used by the RISC-V IOMMU emulation to be added
in the next patch. Due to its size it's being sent in separate for
an easier review.
One thing to notice is that this header can be replaced by the future
Linux RISC-V IOMMU driver header, which would become
From: Samuel Holland
When riscv_load_firmware() loads an ELF, the ELF segment addresses are
used, not the passed-in firmware_load_addr. The machine models assume
the firmware entry point is what they provided for firmware_load_addr,
and use that address to generate the boot ROM, so if the ELF is
From: Tomasz Jeznach
Add PCIe Address Translation Services (ATS) capabilities to the IOMMU.
This will add support for ATS translation requests in Fault/Event
queues, Page-request queue and IOATC invalidations.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Fr
From: Jason Chien
RVV spec allows implementations to set vl with values within
[ceil(AVL/2),VLMAX] when VLMAX < AVL < 2*VLMAX. This commit adds a
property "rvv_vl_half_avl" to enable setting vl = ceil(AVL/2). This
behavior helps identify compiler issues and bugs.
Signed-off-by: Jason Chien
Revi
From: Tomasz Jeznach
The IMSIC state variable eistate[] is modified by CSR instructions
within a range dedicated to the local CPU and by MMIO writes from any CPU.
Access to eistate from MMIO accessors is protected by the BQL, but
read-modify-write (RMW) sequences from CSRRW do not acquire the BQL
From: Mark Corbin
Implemented the RISC-V CPU execution loop, including handling various
exceptions and system calls. The loop continuously executes CPU
instructions,processes exceptions, and handles system calls by invoking
FreeBSD syscall handlers.
Signed-off-by: Mark Corbin
Signed-off-by: Aje
From: Alvin Chang
According to RISC-V Debug specification, the optional textra32 and
textra64 trigger CSRs can be used to configure additional matching
conditions for the triggers. For example, if the textra.MHSELECT field
is set to 4 (mcontext), this trigger will only match or fire if the low
bi
From: Daniel Henrique Barboza
To test the RISC-V IOMMU emulation we'll use its PCI representation.
Create a new 'riscv-iommu-pci' libqos device that will be present with
CONFIG_RISCV_IOMMU. This config is only available for RISC-V, so this
device will only be consumed by the RISC-V libqos machin
From: Tomasz Jeznach
The RISC-V IOMMU can be modelled as a PCIe device following the
guidelines of the RISC-V IOMMU spec, chapter 7.1, "Integrating an IOMMU
as a PCIe device".
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by: Alistair F
From: Daniel Henrique Barboza
Add a simple guideline to use the existing RISC-V IOMMU support we just
added.
This doc will be updated once we add the riscv-iommu-sys device.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20240903201633.93182-13-dbarb...@vent
The following changes since commit 01dc65a3bc262ab1bec8fe89775e9bbfa627becb:
Merge tag 'pull-target-arm-20240919' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-09-19
14:15:15 +0100)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/
u.git tags/qemu-openbios-20240924
for you to fetch changes up to 972208be775a37dccb3047702ea1582e9936102c:
roms/openbios: update OpenBIOS images to c3a19c1e built from submodule
(2024-09-24 20:58:54 +0100)
qemu-openbios queu
On Tue, 24 Sep 2024, Bernhard Beschow wrote:
Am 24. September 2024 09:59:21 UTC schrieb BALATON Zoltan :
On Mon, 23 Sep 2024, Bernhard Beschow wrote:
Am 23. September 2024 10:43:19 UTC schrieb BALATON Zoltan :
On Mon, 23 Sep 2024, Bernhard Beschow wrote:
Populate this read-only register with
On 24.09.24 18:22, Nina Schoetterl-Glausch wrote:
On Tue, 2024-09-10 at 19:58 +0200, David Hildenbrand wrote:
We actually want to check the available RAM, not the maximum RAM size.
Signed-off-by: David Hildenbrand
Reviewed-by: Nina Schoetterl-Glausch
Nit below.
---
target/s390x/kvm/pv.c
Am 23. September 2024 10:38:46 UTC schrieb BALATON Zoltan :
>On Mon, 23 Sep 2024, Bernhard Beschow wrote:
>> The device model already has a header file. Also extract its implementation
>> into
>> an accompanying source file like other e500 devices.
>>
>> This commit is also a preparation for t
Am 24. September 2024 10:15:43 UTC schrieb BALATON Zoltan :
>On Mon, 23 Sep 2024, Bernhard Beschow wrote:
>> The CCSR space is just a container which is meant to be covered by platform
>> device memory regions. However, QEMU only implements a subset of these
>> devices.
>> Add some logging to s
Per the Armv7-M Architecture Reference Manual (ARM DDI 0403E):
The System Control Space (SCS, address range 0xE000E000 to
0xE000EFFF) is a memory-mapped 4KB address space that provides
32-bit registers for configuration, status reporting and control.
All accesses to the SCS are little endi
Hi Peter,
(patch merged as commit 6087df574400659226861fa5ba47970f1fbd277b).
On 12/9/23 16:04, Peter Maydell wrote:
The FEAT_MOPS SETG* instructions are very similar to the SET*
instructions, but as well as setting memory contents they also
set the MTE tags. They are architecturally required to
Am 24. September 2024 09:59:21 UTC schrieb BALATON Zoltan :
>On Mon, 23 Sep 2024, Bernhard Beschow wrote:
>> Am 23. September 2024 10:43:19 UTC schrieb BALATON Zoltan
>> :
>>> On Mon, 23 Sep 2024, Bernhard Beschow wrote:
Populate this read-only register with some arbitrary values which avo
Ilya Leoshkevich writes:
> On Tue, 2024-09-24 at 12:54 +0100, Alex Bennée wrote:
>> Ilya Leoshkevich writes:
>>
>> (add Mahesh to CC)
>>
>> > GCC produces invalid code for microblaze atomics.
>> >
>> > The fix is unfortunately not upstream, so fetch it from an external
>> > location and apply
On Tue, 2024-09-10 at 19:58 +0200, David Hildenbrand wrote:
> We actually want to check the available RAM, not the maximum RAM size.
>
> Signed-off-by: David Hildenbrand
Reviewed-by: Nina Schoetterl-Glausch
Nit below.
> ---
> target/s390x/kvm/pv.c | 2 +-
> 1 file changed, 1 insertion(+), 1 de
On Tue, 2024-09-24 at 15:24 +0200, Thomas Huth wrote:
> According to https://marc.info/?l=fedora-devel-list&m=171934833215726
> the GlusterFS development effectively ended. Thus mark it as
> deprecated
> in QEMU, so we can remove it in a future release if the project does
> not gain momentum again.
On Tue, Sep 10, 2024 at 3:06 PM Noah Goldstein wrote:
>
> On Fri, Aug 30, 2024 at 3:37 PM Noah Goldstein
> wrote:
> >
> > On Fri, Aug 30, 2024 at 3:36 PM Noah Goldstein
> > wrote:
> > >
> > > The new option '-qemu-children' makes it so that on `execve` the child
> > > process will be launch by
On Tue, 24 Sep 2024 13:24:10 +
Ricardo Ribalda wrote:
> Signed-off-by: Ricardo Ribalda
Acked-by: Igor Mammedov
> ---
> tests/qtest/bios-tables-test-allowed-diff.h | 15 +++
> 1 file changed, 15 insertions(+)
>
> diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
> b/t
On Sat, 21 Sep 2024 07:29:55 +
Hal Martin wrote:
> This patch adds support for SMBIOS type 7 (Cache Information) to qemu.
>
> level: cache level (1-8)
> size: cache size in bytes
>
> Example usage:
> -smbios type=7,level=1,size=0x8000
>
> Signed-off-by: Hal Martin
> ---
> hw/smbios/smbio
On Tue, Sep 24, 2024 at 15:24:51 +0200, Thomas Huth wrote:
> According to https://marc.info/?l=fedora-devel-list&m=171934833215726
> the GlusterFS development effectively ended. Thus mark it as deprecated
> in QEMU, so we can remove it in a future release if the project does
> not gain momentum aga
On Tue, 24 Sep 2024 13:24:12 +
Ricardo Ribalda wrote:
> Signed-off-by: Ricardo Ribalda
Acked-by: Igor Mammedov
> ---
> tests/data/acpi/x86/pc/DSDT | Bin 8527 -> 8526 bytes
> tests/data/acpi/x86/pc/DSDT.acpierst| Bin 8438 -> 8437 bytes
> tests/data/acpi/x86/pc/DS
On Tue, 24 Sep 2024 15:00:58 +0200
Mauro Carvalho Chehab wrote:
> Em Tue, 17 Sep 2024 14:15:19 +0200
> Igor Mammedov escreveu:
>
> > I'm done with this round of review.
> >
> > Given that the series accumulated a bunch of cleanups,
> > I'd suggest to move all cleanups/renamings not related
> >
According to https://marc.info/?l=fedora-devel-list&m=171934833215726
the GlusterFS development effectively ended. Thus mark it as deprecated
in QEMU, so we can remove it in a future release if the project does
not gain momentum again.
Signed-off-by: Thomas Huth
---
docs/about/deprecated.rst | 9
Signed-off-by: Ricardo Ribalda
---
tests/qtest/bios-tables-test-allowed-diff.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..f81f4e2469 100644
--- a/tests/qtest/bios
1 - 100 of 182 matches
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