Re: [PATCH v2 01/11] hw/s390/ccw-device: Convert to three-phase reset

On 30/08/2024 16.58, Peter Maydell wrote: Convert the TYPE_CCW_DEVICE to three-phase reset. This is a device class which is subclassed, so it needs to be three-phase before we can convert the subclass. Signed-off-by: Peter Maydell --- hw/s390x/ccw-device.c | 7 --- 1 file changed, 4 inse

Re: [PATCH] tests/functional/test_vnc: Reduce raciness in find_free_ports()

On 03/09/2024 16.50, Daniel P. Berrangé wrote: On Tue, Sep 03, 2024 at 04:35:53PM +0200, Philippe Mathieu-Daudé wrote: Pass the port range as argument. In order to reduce races when looking for free ports, use a per-target per-process base port (based on the target built-in hash). Signed-off-by

[PATCH v4 1/2] target/loongarch: Add loongson binary translation feature

Loongson Binary Translation (LBT) is used to accelerate binary translation, which contains 4 scratch registers (scr0 to scr3), x86/ARM eflags (eflags) and x87 fpu stack pointer (ftop). Now LBT feature is added in kvm mode, not supported in TCG mode since it is not emulated. Feature variable lbt is

[PATCH v4 0/2] target/loongarch: Add loongson binary translation feature

Loongson Binary Translation (LBT) is used to accelerate binary translation. LBT feature is added in kvm mode, not supported in TCG mode since it is not emulated. Here lbt=on/off property is added to parse command line to enable/disable lbt feature. Also fix registers relative lbt are saved and res

[PATCH v4 2/2] target/loongarch: Implement lbt registers save/restore function

Six registers scr0 - scr3, eflags and ftop are added in percpu vmstate. And two functions kvm_loongarch_get_lbt/kvm_loongarch_put_lbt are added to save/restore lbt registers. Signed-off-by: Bibo Mao --- target/loongarch/cpu.h | 12 target/loongarch/kvm/kvm.c | 60 +++

[PATCH] chardev: introduce 'reconnect-ms' and deprecate 'reconnect'

The 'reconnect' option only allows to specify the time in seconds, which is way too long for certain workflows. We have a lightweight disk backend server, which takes about 20ms to live update, but due to this limitation in QEMU, previously the guest disk controller would hang for one second becau

RE: [PATCH v3 2/2] target/riscv: Add textra matching condition for the triggers

Hi Alistair, > -Original Message- > From: Alistair Francis > Sent: Monday, August 26, 2024 8:26 AM > To: Alvin Che-Chia Chang(張哲嘉) > Cc: qemu-ri...@nongnu.org; qemu-devel@nongnu.org; > alistair.fran...@wdc.com; bin.m...@windriver.com; liwei1...@gmail.com; > dbarb...@ventanamicro.com; zhi

[PATCH -next] fw_cfg: Constify struct kobj_type

This 'struct kobj_type' is not modified. It is only used in kobject_init_and_add() which takes a 'const struct kobj_type *ktype' parameter. Constifying this structure and moving it to a read-only section, and this can increase over all security. ``` [Before] text databssdechex

RE: [SPAM] [PATCH v3 00/11] support I2C for AST2700

Hi Cedric, > Subject: Re: [SPAM] [PATCH v3 00/11] support I2C for AST2700 > > On 9/3/24 10:35, Jamin Lin wrote: > > v1: > > - support I2C for AST2700 > > > > v2: > > - fix review issues and add reviewer suggestion > > - update avocado test case for AST2700 I2C > > - support i2c bus pool > > > > v

Re: [PATCH 1/1] target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension

On Mon, Sep 2, 2024 at 11:38 PM Maria Klauchek wrote: > > FCSR is a part of F extension. Print it to log if FPU option is enabled. > > Signed-off-by: Maria Klauchek Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/cpu.c | 6 ++ > 1 file changed, 6 insertions(+) > > di

Re: [PATCH 1/1] target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension

On Mon, Sep 2, 2024 at 11:38 PM Maria Klauchek wrote: > > FCSR is a part of F extension. Print it to log if FPU option is enabled. > > Signed-off-by: Maria Klauchek Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 6 ++ > 1 file changed, 6 insertions(+) > > diff --git

Re: [PATCH 0/5] Introduce svukte ISA extension

On Tue, Sep 3, 2024 at 4:16 PM Fea.Wang wrote: > > Refer to the draft of svukte extension from: > https://github.com/riscv/riscv-isa-manual/pull/1564 > > Svukte provides a means to make user-mode accesses to supervisor memory > raise page faults in constant time, mitigating attacks that attempt to

Re: [PATCH 1/5] target/riscv: Add svukte extension capability variable

On Tue, Sep 3, 2024 at 4:15 PM Fea.Wang wrote: > > Refer to the draft of svukte extension from: > https://github.com/riscv/riscv-isa-manual/pull/1564 We won't be able to merge this while the spec is just a pull request. We need a fixes spec that we can point out with a version Alistair > > Svuk

Re: [PATCH v2] escc: convert Sun mouse to use QemuInputHandler

This works well. On Tue, Sep 3, 2024 at 1:38 PM Mark Cave-Ayland < mark.cave-ayl...@ilande.co.uk> wrote: > Update the Sun mouse implementation to use QemuInputHandler instead of the > legacy qemu_add_mouse_event_handler() function. > > Note that this conversion adds extra sunmouse_* members to ES

Re: [PATCH 4/5] target/riscv: Check memory access to meet svuket rule

On 9/3/24 3:17 AM, Fea.Wang wrote: Follow the Svukte spec, do the memory access address checking 1. Include instruction fetches or explicit memory accesses 2. System run in effective privilege U or VU 3. Check senvcfg[UKTE] being set, or hstatus[HUKTE] being set if instruction is HLV, HLV

Re: [PATCH 1/1] target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension

On 9/2/24 7:34 AM, Maria Klauchek wrote: FCSR is a part of F extension. Print it to log if FPU option is enabled. Signed-off-by: Maria Klauchek --- Reviewed-by: Daniel Henrique Barboza target/riscv/cpu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/t

[PATCH] hw/arm/omap1: Remove unused omap_uwire_attach() method

The recently removed 'cheetah' machine was the single user of the omap_uwire_attach() method. Remove it altogether with the uWireSlave structure. Replace the send/receive callbacks by Unimplemented logging. Signed-off-by: Philippe Mathieu-Daudé --- Based-on: <20240903160751.4100218-1-peter.mayd..

Re: [PATCH for-9.2 26/53] hw/misc: Remove cbus

On 3/9/24 18:07, Peter Maydell wrote: The devices in hw/misc/cbus.c were used only by the now-removed nseries machine types, so they can be removed. As this is the last use of the CONFIG_NSERIES define we can remove that from KConfig now. Signed-off-by: Peter Maydell --- MAINTAINERS

Re: [PATCH for-9.2 19/53] hw/dma: Remove pxa2xx_dma

On 3/9/24 18:07, Peter Maydell wrote: Remove the pxa2xx-specific pxa2xx_dma device. Signed-off-by: Peter Maydell --- include/hw/arm/pxa.h | 4 - hw/dma/pxa2xx_dma.c | 591 --- hw/dma/meson.build | 1 - 3 files changed, 596 deletions(-) delet

Re: [PATCH for-9.2 01/53] hw/arm: Remove deprecated akita, borzoi, spitz, terrier, tosa boards

On 3/9/24 18:06, Peter Maydell wrote: The Sharp XScale-based PDA board models akita, borzoi, spitz, terrier, and tosa were all deprecated in 9.0, so our deprecation cycle permits removing them for the 9.2 release. Remove the source files for the board models themselves, and their documentation.

Re: [PATCH for-9.2 09/53] hw/arm: Remove 'connex' and 'verdex' machines

On 3/9/24 18:07, Peter Maydell wrote: The connex and verdex machines have been deprecated since 9.0 and so can be removed for the 9.2 release. Signed-off-by: Peter Maydell --- MAINTAINERS | 8 -- docs/system/arm/gumstix.rst | 21 docs/system/t

Re: [PATCH for-9.2 36/53] docs: Document removal of old Arm boards

On 3/9/24 18:07, Peter Maydell wrote: Now we have removed all the board types that it covers, we can move the text about old Arm boards from deprecated.rst to removed-features.rst, tweaking it appropriately. Signed-off-by: Peter Maydell --- docs/about/deprecated.rst | 15 ---

Re: [PATCH v7 01/12] exec/memtxattr: add process identifier to the transaction attributes

On 9/3/24 5:31 PM, Richard Henderson wrote: On 9/3/24 13:16, Daniel Henrique Barboza wrote: From: Tomasz Jeznach Extend memory transaction attributes with process identifier to allow per-request address translation logic to use requester_id / process_id to identify memory mapping (e.g. enab

Re: [PATCH 1/2] hw/sd: Remove legacy sd_set_cb()

On 9/3/24 13:10, Philippe Mathieu-Daudé wrote: (Cc'ing Guenter who asked to keep the SX1 machine) On 3/9/24 22:04, Philippe Mathieu-Daudé wrote: sd_set_cb() was only used by omap2_mmc_init() which got recently removed. Time to remove it. For historical background on the me_no_qdev_me_kill_mammo

Re: [PATCH v5 5/8] device/virtio-nsm: Support for Nitro Secure Module device

On Wed, Sep 4, 2024, 2:32 AM Michael S. Tsirkin wrote: > On Wed, Sep 04, 2024 at 01:58:15AM +0600, Dorjoy Chowdhury wrote: > > On Thu, Aug 29, 2024 at 1:11 AM Michael S. Tsirkin > wrote: > > > > > > On Thu, Aug 29, 2024 at 01:04:05AM +0600, Dorjoy Chowdhury wrote: > > > > On Thu, Aug 29, 2024 at

Re: [PATCH v2] escc: convert Sun mouse to use QemuInputHandler

On 9/3/24 13:38, Mark Cave-Ayland wrote: Update the Sun mouse implementation to use QemuInputHandler instead of the legacy qemu_add_mouse_event_handler() function. Note that this conversion adds extra sunmouse_* members to ESCCChannelState but they are not added to the migration stream (similar

[PATCH v2] escc: convert Sun mouse to use QemuInputHandler

Update the Sun mouse implementation to use QemuInputHandler instead of the legacy qemu_add_mouse_event_handler() function. Note that this conversion adds extra sunmouse_* members to ESCCChannelState but they are not added to the migration stream (similar to the Sun keyboard members). If this were

Re: [PATCH for-9.2 41/53] hw/sd: Remove omap2_mmc device

On 3/9/24 18:07, Peter Maydell wrote: Remove the OMAP2 specific code from omap_mmc.c. Signed-off-by: Peter Maydell --- include/hw/arm/omap.h | 5 hw/sd/omap_mmc.c | 63 --- 2 files changed, 68 deletions(-) -struct omap_mmc_s *omap2_mmc_

Re: [PATCH for-9.2 16/53] hw/sd: Remove pxa2xx_mmci.c

On 3/9/24 18:07, Peter Maydell wrote: Remove the pxa2xx-specific pxa2xx_mmci device. Signed-off-by: Peter Maydell --- include/hw/arm/pxa.h | 10 - hw/sd/pxa2xx_mmci.c | 594 --- hw/sd/meson.build| 1 - hw/sd/trace-events | 4 - 4 files c

Re: [PATCH v5 5/8] device/virtio-nsm: Support for Nitro Secure Module device

On Wed, Sep 04, 2024 at 01:58:15AM +0600, Dorjoy Chowdhury wrote: > On Thu, Aug 29, 2024 at 1:11 AM Michael S. Tsirkin wrote: > > > > On Thu, Aug 29, 2024 at 01:04:05AM +0600, Dorjoy Chowdhury wrote: > > > On Thu, Aug 29, 2024 at 12:28 AM Michael S. Tsirkin > > > wrote: > > > > > > > > On Thu, A

Re: [PATCH v7 01/12] exec/memtxattr: add process identifier to the transaction attributes

On 9/3/24 13:16, Daniel Henrique Barboza wrote: From: Tomasz Jeznach Extend memory transaction attributes with process identifier to allow per-request address translation logic to use requester_id / process_id to identify memory mapping (e.g. enabling IOMMU w/ PASID translations). Signed-off-b

Re: [Question] [Block] Is there a way to control the read caching of a block device?

Cc'ing the qemu-block@ list On 3/9/24 20:13, DUO Labs wrote: I know that the `cache` parameter for `-drive` controls the caching behavior when writing from the guest to the host, but is there a way to control the reading behavior host->guest? Currently, on HEAD, if I open a file on both the gu

[PATCH v7 10/12] hw/riscv/riscv-iommu: add DBG support

From: Tomasz Jeznach DBG support adds three additional registers: tr_req_iova, tr_req_ctl and tr_response. The DBG cap is always enabled. No on/off toggle is provided for it. Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Reviewed-by: Frank Chang Reviewed-by: Alistair F

[PATCH v7 01/12] exec/memtxattr: add process identifier to the transaction attributes

From: Tomasz Jeznach Extend memory transaction attributes with process identifier to allow per-request address translation logic to use requester_id / process_id to identify memory mapping (e.g. enabling IOMMU w/ PASID translations). Signed-off-by: Tomasz Jeznach Reviewed-by: Frank Chang Revie

[PATCH v7 08/12] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)

From: Tomasz Jeznach The RISC-V IOMMU spec predicts that the IOMMU can use translation caches to hold entries from the DDT. This includes implementation for all cache commands that are marked as 'not implemented'. There are some artifacts included in the cache that predicts s-stage and g-stage e

[PATCH v7 05/12] hw/riscv: add riscv-iommu-pci reference device

From: Tomasz Jeznach The RISC-V IOMMU can be modelled as a PCIe device following the guidelines of the RISC-V IOMMU spec, chapter 7.1, "Integrating an IOMMU as a PCIe device". Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Reviewed-by: Frank Chang Reviewed-by: Alistair F

[PATCH v7 02/12] hw/riscv: add riscv-iommu-bits.h

From: Tomasz Jeznach This header will be used by the RISC-V IOMMU emulation to be added in the next patch. Due to its size it's being sent in separate for an easier review. One thing to notice is that this header can be replaced by the future Linux RISC-V IOMMU driver header, which would become

[PATCH v7 09/12] hw/riscv/riscv-iommu: add ATS support

From: Tomasz Jeznach Add PCIe Address Translation Services (ATS) capabilities to the IOMMU. This will add support for ATS translation requests in Fault/Event queues, Page-request queue and IOATC invalidations. Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Reviewed-by: Fr

[PATCH v7 12/12] docs/specs: add riscv-iommu

Add a simple guideline to use the existing RISC-V IOMMU support we just added. This doc will be updated once we add the riscv-iommu-sys device. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- docs/specs/index.rst | 1 + docs/specs/riscv-iommu.rst | 90 ++

[PATCH v7 04/12] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device

The RISC-V IOMMU PCI device we're going to add next is a reference implementation of the riscv-iommu spec [1], which predicts that the IOMMU can be implemented as a PCIe device. However, RISC-V International (RVI), the entity that ratified the riscv-iommu spec, didn't bother assigning a PCI ID for

[PATCH v7 11/12] qtest/riscv-iommu-test: add init queues test

Add an additional test to further exercise the IOMMU where we attempt to initialize the command, fault and page-request queues. These steps are taken from chapter 6.2 of the RISC-V IOMMU spec, "Guidelines for initialization". It emulates what we expect from the software/OS when initializing the IO

[PATCH v7 06/12] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug

From: Tomasz Jeznach Generate device tree entry for riscv-iommu PCI device, along with mapping all PCI device identifiers to the single IOMMU device instance. Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Reviewed-by: Frank Chang Reviewed-by: Alistair Francis --- hw/r

[PATCH v7 07/12] test/qtest: add riscv-iommu-pci tests

To test the RISC-V IOMMU emulation we'll use its PCI representation. Create a new 'riscv-iommu-pci' libqos device that will be present with CONFIG_RISCV_IOMMU. This config is only available for RISC-V, so this device will only be consumed by the RISC-V libqos machine. Start with basic tests: a PC

[PATCH v7 00/12] riscv: QEMU RISC-V IOMMU Support

Hi, In this new version the only significant code change was made in patch 3, where we're no longer modifying the host address with the translated address. The remaining of the changes consist in adding more in-code docs (a.k.a comments) on the design choices made in the emulation. The docs were

[PATCH v7 03/12] hw/riscv: add RISC-V IOMMU base emulation

From: Tomasz Jeznach The RISC-V IOMMU specification is now ratified as-per the RISC-V international process. The latest frozen specifcation can be found at: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf Add the foundation of the device emulation for RISC-V

Re: [PATCH 1/2] hw/sd: Remove legacy sd_set_cb()

(Cc'ing Guenter who asked to keep the SX1 machine) On 3/9/24 22:04, Philippe Mathieu-Daudé wrote: sd_set_cb() was only used by omap2_mmc_init() which got recently removed. Time to remove it. For historical background on the me_no_qdev_me_kill_mammoth_with_rocks kludge, see commit 007d1dbf72 ("sd

[PATCH 2/2] hw/sd: Remove legacy sd_enable()

sd_enable() was only used by omap_mmc_enable() which got recently removed. Time to remove it. Since the SDState::enable boolean is now always %true, we can remove it and simplify. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sd/sd.h| 1 - include/hw/sd/sdcard_legacy.h | 9

Re: [PATCH] target/hppa: Fix random 32-bit linux-user crashes

On 9/3/24 09:41, Helge Deller wrote: The linux-user hppa target crashes randomly for me since commit 081a0ed188d8 ("target/hppa: Do not mask in copy_iaoq_entry"). That commit dropped the masking of the IAOQ addresses while copying them from other registers and instead keeps them with all 64 bits

[PATCH 1/2] hw/sd: Remove legacy sd_set_cb()

sd_set_cb() was only used by omap2_mmc_init() which got recently removed. Time to remove it. For historical background on the me_no_qdev_me_kill_mammoth_with_rocks kludge, see commit 007d1dbf72 ("sd: Hide the qdev-but-not-quite thing created by sd_init()"). Signed-off-by: Philippe Mathieu-Daudé -

Re: [PATCH v2 10/17] migration/multifd: Convert multifd_send()::next_channel to atomic

On 3.09.2024 17:01, Fabiano Rosas wrote: "Maciej S. Szmigiero" writes: On 30.08.2024 20:13, Fabiano Rosas wrote: "Maciej S. Szmigiero" writes: From: "Maciej S. Szmigiero" This is necessary for multifd_send() to be able to be called from multiple threads. Signed-off-by: Maciej S. Szmigie

[PATCH 0/2] hw/sd: Remove a pair of legacy methods

The omap2_mmc device -- deprecated and about to be removed -- was the last user of the legacy sd_set_cb() and sd_enable() methods. Remove them too along with the me_no_qdev_me_kill_mammoth_with_rocks kludge. Based-on: <20240903160751.4100218-1-peter.mayd...@linaro.org> Philippe Mathieu-Daudé (2):

Re: [PATCH v5 5/8] device/virtio-nsm: Support for Nitro Secure Module device

On Thu, Aug 29, 2024 at 1:11 AM Michael S. Tsirkin wrote: > > On Thu, Aug 29, 2024 at 01:04:05AM +0600, Dorjoy Chowdhury wrote: > > On Thu, Aug 29, 2024 at 12:28 AM Michael S. Tsirkin wrote: > > > > > > On Thu, Aug 22, 2024 at 09:08:46PM +0600, Dorjoy Chowdhury wrote: > > > > Nitro Secure Module

Re: [RFC V1 1/6] Revert "vhost-backend: remove vhost_kernel_reset_device()"

On 9/3/2024 6:44 AM, Euan Turner wrote: Hi Steve, On 30/08/2024 12:56, Steve Sistare wrote: This reverts commit e6383293eb01928692047e617665a742cca87e23. The reset function is needed for CPR. Signed-off-by: Steve Sistare ---   hw/virtio/vhost-backend.c | 6 ++   1 file changed, 6 insertion

[PATCH v2] target/hppa: Fix PSW V-bit packaging in cpu_hppa_get for hppa64

While adding hppa64 support, the psw_v variable got extended from 32 to 64 bits. So, when packaging the PSW-V bit from the psw_v variable for interrupt processing, check bit 31 instead the 63th (sign) bit. This fixes a hard to find Linux kernel boot issue where the loss of the PSW-V bit due to an

Re: [PATCH v2 05/17] thread-pool: Implement non-AIO (generic) pool support

On Tue, 3 Sept 2024 at 12:54, Maciej S. Szmigiero wrote: > > On 3.09.2024 15:55, Stefan Hajnoczi wrote: > > On Tue, 27 Aug 2024 at 13:58, Maciej S. Szmigiero > > wrote: > >> > >> From: "Maciej S. Szmigiero" > >> > >> Migration code wants to manage device data sending threads in one place. > >> >

Re: [PATCH v2 09/17] migration/multifd: Device state transfer support - receive side

On 3.09.2024 16:42, Fabiano Rosas wrote: "Maciej S. Szmigiero" writes: On 30.08.2024 22:22, Fabiano Rosas wrote: "Maciej S. Szmigiero" writes: From: "Maciej S. Szmigiero" Add a basic support for receiving device state via multifd channels - channels that are shared with RAM transfers. T

Re: [PATCH] target/hppa: Fix PSW V-bit packaging in cpu_hppa_get for hppa64

On 9/3/24 03:28, Helge Deller wrote: While adding hppa64 support, the psw_v variable got extended from 32 to 64 bits. So, when packaging the PSW-V bit from the psw_v variable for interrupt processing, check bit 31 instead the 63th (sign) bit. This fixes a hard to find Linux kernel boot issue wh

Re: [PATCH v2 05/17] thread-pool: Implement non-AIO (generic) pool support

On 3.09.2024 16:26, Fabiano Rosas wrote: "Maciej S. Szmigiero" writes: On 3.09.2024 00:07, Fabiano Rosas wrote: "Maciej S. Szmigiero" writes: From: "Maciej S. Szmigiero" Migration code wants to manage device data sending threads in one place. QEMU has an existing thread pool implementat

[Question] [Block] Is there a way to control the read caching of a block device?

I know that the `cache` parameter for `-drive` controls the caching behavior when writing from the guest to the host, but is there a way to control the reading behavior host->guest? Currently, on HEAD, if I open a file on both the guest and host, and write some data to the drive on the (macOS)

Re: [PATCH 2/2] qemu/osdep: handle sysconf(_SC_OPEN_MAX) return value == -1

On 3/9/24 17:21, Daniel P. Berrangé wrote: On Tue, Sep 03, 2024 at 05:02:44PM +0200, Philippe Mathieu-Daudé wrote: On 3/9/24 15:37, Clément Léger wrote: On 03/09/2024 15:34, Philippe Mathieu-Daudé wrote: On 3/9/24 09:53, Clément Léger wrote: On 02/09/2024 21:38, Philippe Mathieu-Daudé wrote:

Re: [PATCH] target/cris: Remove the deprecated CRIS target

On 3/9/24 18:13, Peter Maydell wrote: On Tue, 3 Sept 2024 at 16:28, Philippe Mathieu-Daudé wrote: The CRIS target is deprecated since v9.0 (commit c7bbef40234 "docs: mark CRIS support as deprecated"). Remove: - Buildsys / CI infra - User emulation - System emulation (axis-dev88 machine and ET

Re: [PATCH 7/8] python/qapi: move scripts/qapi to python/qemu/qapi

On Mon, Sep 2, 2024, 4:51 AM Daniel P. Berrangé wrote: > On Fri, Aug 30, 2024 at 02:22:50PM -0400, John Snow wrote: > > Gave Dan a related answer. For you, my explanation is: > > > > - It's nice to have just one configuration for static analysis in just > one > > place > > - It's nice to have tha

Re: [PATCH] plugins: add two events for cpu_restore_state_from_tb() and cpu_io_recompile()

Richard Henderson writes: > On 9/2/24 10:52, Alex Bennée wrote: >> Pierrick Bouvier writes: >> >>> Hi Xingran, >>> >>> On 9/2/24 03:42, Alex Bennée wrote: Xingran Wang writes: > Currently, the instruction count obtained by plugins using the translation > block execution callb

Re: [PATCH for-9.2 00/53] arm: Drop deprecated boards

On Tue, Sep 3, 2024 at 7:04 PM Peter Maydell wrote: > The PXA display device doesn't pass anything through to the guest, > by the way -- it just draws the pixels in the guest framebuffer > in a different place in the UI window. As the FIXME comment in > pxa2xx_lcd.c notes, this should really have

Re: [PATCH for-9.2 00/53] arm: Drop deprecated boards

On Tue, 3 Sept 2024 at 17:55, Paolo Bonzini wrote: > > On 9/3/24 18:06, Peter Maydell wrote: > > This patchset removes the various Arm machines which we deprecated > > for the 9.0 release and are therefore allowed to remove for the 9.2 > > release: > > akita, borzoi, cheetah, connex, mainstone,

Re: [PATCH for-9.2 00/53] arm: Drop deprecated boards

On 9/3/24 18:06, Peter Maydell wrote: This patchset removes the various Arm machines which we deprecated for the 9.0 release and are therefore allowed to remove for the 9.2 release: akita, borzoi, cheetah, connex, mainstone, n800, n810, spitz, terrier, tosa, verdex, z2 We get to drop over 30,

Re: [PATCH v2 05/17] thread-pool: Implement non-AIO (generic) pool support

On 3.09.2024 15:55, Stefan Hajnoczi wrote: On Tue, 27 Aug 2024 at 13:58, Maciej S. Szmigiero wrote: From: "Maciej S. Szmigiero" Migration code wants to manage device data sending threads in one place. QEMU has an existing thread pool implementation, however it was limited to queuing AIO ope

Re: [PATCH 1/1] platform-bus: fix refcount leak

On Fri, 30 Aug 2024 at 11:47, Xingtao Yao (Fujitsu) via wrote: > > > > > -Original Message- > > From: qemu-devel-bounces+yaoxt.fnst=fujitsu@nongnu.org > > On Behalf Of Gao > > Shiyuan via > > Sent: Thursday, August 29, 2024 9:10 PM > > To: Paolo Bonzini > > Cc: qemu-devel@nongnu.org;

Re: [PATCH 2/8] python/qapi: change "FIXME" to "TODO"

On Sat, Aug 31, 2024, 2:02 AM Markus Armbruster wrote: > John Snow writes: > > > On Fri, Aug 30, 2024 at 7:09 AM Markus Armbruster > wrote: > > > >> John Snow writes: > >> > >> > qemu.git/python/setup.cfg disallows checking in any code with "XXX", > >> > "FIXME" or "TODO" in the comments. Soft

Re: [PATCH] plugins: add two events for cpu_restore_state_from_tb() and cpu_io_recompile()

On 9/2/24 10:52, Alex Bennée wrote: Pierrick Bouvier writes: Hi Xingran, On 9/2/24 03:42, Alex Bennée wrote: Xingran Wang writes: Currently, the instruction count obtained by plugins using the translation block execution callback is larger than the actual value. Adding callbacks in cpu_re

[PATCH] target/hppa: Fix random 32-bit linux-user crashes

The linux-user hppa target crashes randomly for me since commit 081a0ed188d8 ("target/hppa: Do not mask in copy_iaoq_entry"). That commit dropped the masking of the IAOQ addresses while copying them from other registers and instead keeps them with all 64 bits up until the full gva is formed with t

Re: [PATCH] hw/arm/boot: Explain why load_elf_hdr() error is ignored

On Tue, 3 Sept 2024 at 15:41, Philippe Mathieu-Daudé wrote: > > If the file is not an ELF file, arm_setup_direct_kernel_boot() > falls back to try it as a uimage or an AArch64 Image file or as > last resort a bare raw binary. We can discard load_elf_hdr() > error and silently return. > > Signed-of

Re: [PATCH v3] hw/arm/boot: Report error msg if loading elf/dtb failed

On Tue, 3 Sept 2024 at 14:52, Philippe Mathieu-Daudé wrote: > > On 3/9/24 15:39, Changbin Du wrote: > > Print errors before exit. Do not exit silently. > > > > Cc: Philippe Mathieu-Daudé > > Signed-off-by: Changbin Du > > > > --- > > v3: use load_elf_strerror() to format errno. > > v2: remove ms

Re: [PATCH] hw/arm/xilinx_zynq: Enable Security Extensions

On Fri, 30 Aug 2024 at 09:05, Edgar E. Iglesias wrote: > > On Thu, Aug 29, 2024 at 01:50:02PM +0100, Peter Maydell wrote: > > On Wed, 28 Aug 2024 at 01:51, Sebastian Huber > > wrote: > > > > > > The system supports the Security Extensions (core and GIC). This change > > > is > > > necessary to

Re: [PATCH] target/arm: Correct names of VFP VFNMA and VFNMS insns

On 9/2/24 06:21, Peter Maydell wrote: On Fri, 30 Aug 2024 at 16:21, Peter Maydell wrote: In vfp.decode we have the names of the VFNMA and VFNMS instructions the wrong way around. The architecture says that bit 6 is the 'op' bit, which is 1 for VFNMA and 1 for VFNMS, but we label these two D

Re: [PATCH 0/3] hw/sh4: Remove the deprecated SHIX machine

On Tue, 3 Sept 2024 at 16:40, Philippe Mathieu-Daudé wrote: > > Remove the deprecated SH4 SHIX machine, along > with the TC58128 NAND EEPROM. > > Philippe Mathieu-Daudé (3): > hw/sh4: Remove the deprecated SHIX machine > hw/block: Remove TC58128 NAND EEPROM > hw/sh4: Remove sh7750_register_i

[PATCH for-9.2 17/53] hw/input: Remove pxa2xx_keypad

Remove the pxa2xx-specific pxa2xx_keypad device. Signed-off-by: Peter Maydell --- include/hw/arm/pxa.h | 12 -- hw/input/pxa2xx_keypad.c | 331 --- hw/input/meson.build | 1 - 3 files changed, 344 deletions(-) delete mode 100644 hw/input/pxa2xx_key

[PATCH for-9.2 08/53] hw/arm: Remove 'cheetah' machine

The 'cheetah' machine has been deprecated since 9.0, so we can remove it for the 9.2 release. (tsc210x.c is also used by nseries, so move its MAINTAINER file line there; the nseries boards are also about to be removed.) Signed-off-by: Peter Maydell --- MAINTAINERS |

Re: [PATCH] target/cris: Remove the deprecated CRIS target

On Tue, 3 Sept 2024 at 16:28, Philippe Mathieu-Daudé wrote: > > The CRIS target is deprecated since v9.0 (commit c7bbef40234 > "docs: mark CRIS support as deprecated"). > > Remove: > - Buildsys / CI infra > - User emulation > - System emulation (axis-dev88 machine and ETRAX devices) > - Tests > >

[PATCH for-9.2 15/53] hw/arm: Remove pxa2xx.c

All the callers of pxa270_init() and pxa255_init() have now been removed, so we can remove pxa2xx.c. This also removes the only uses of a lot of pxa2xx specific devices, which will be removed in subsequent commits. Signed-off-by: Peter Maydell --- include/hw/arm/pxa.h | 78 -- hw/arm/pxa2xx.c

[PATCH for-9.2 51/53] hw/misc/omap_clk: Remove OMAP2-specifics

Remove the handling for all non-OMAP1 SoCs. Signed-off-by: Peter Maydell --- hw/misc/omap_clk.c | 527 + 1 file changed, 2 insertions(+), 525 deletions(-) diff --git a/hw/misc/omap_clk.c b/hw/misc/omap_clk.c index c77ca2fc74e..0157c9be759 100644 --- a

[PATCH for-9.2 18/53] hw/display: Remove pxa2xx_lcd.c

Remove the pxa2xx-specific pxa2xx_lcd device. Signed-off-by: Peter Maydell --- include/hw/arm/pxa.h|6 - hw/display/pxa2xx_lcd.c | 1451 --- hw/display/meson.build |1 - 3 files changed, 1458 deletions(-) delete mode 100644 hw/display/pxa2xx_lcd.

[PATCH for-9.2 35/53] hw: Remove PCMCIA subsystem

The only PCMCIA subsystem was the PXA2xx SoC and the machines using it, which have now been removed. Although in theory we have a few machine types which have PCMCIA (e.g. kzm, the strongarm machines, sh4's sh7750), none of those machines implement their PCMCIA controller, and they're all old and n

[PATCH for-9.2 29/53] hw/input: Remove tsc210x device

Remove the tsc210x touchscreen controller device, which was only used by the n800 and n810. The uWireSlave struct is still used in omap1.c (at least for compilation purposes -- nothing any longer calls omap_uwire_attach() and so the struct's members will not be used at runtime), so we move it into

[PATCH for-9.2 10/53] hw/arm: Remove 'mainstone' machine

The 'mainstone' machine has been deprecated since 9.0, and so we can remove it for the 9.2 release. Signed-off-by: Peter Maydell --- MAINTAINERS | 2 - docs/system/arm/mainstone.rst | 25 docs/system/target-arm.rst | 1 - configs/devic

[PATCH for-9.2 11/53] hw/misc: Remove MAINSTONE_FPGA device

The MAINSTONE_FPGA device was used only by the 'mainstone' machine type, so we can remove it now. Signed-off-by: Peter Maydell --- MAINTAINERS | 1 - hw/misc/mst_fpga.c | 269 hw/misc/meson.build | 1 - 3 files changed, 271 deletions(-)

[PATCH for-9.2 19/53] hw/dma: Remove pxa2xx_dma

Remove the pxa2xx-specific pxa2xx_dma device. Signed-off-by: Peter Maydell --- include/hw/arm/pxa.h | 4 - hw/dma/pxa2xx_dma.c | 591 --- hw/dma/meson.build | 1 - 3 files changed, 596 deletions(-) delete mode 100644 hw/dma/pxa2xx_dma.c diff --git

[PATCH for-9.2 53/53] hw: Remove omap2 specific defines and enums

Remove some defines and enums that are OMAP2 specific and no longer used anywhere. Signed-off-by: Peter Maydell --- include/hw/arm/omap.h | 207 -- 1 file changed, 207 deletions(-) diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h index 3f9860070

[PATCH for-9.2 40/53] hw/intc: Remove omap2-intc device

Remove the OMAP2 specific code from omap_intc.c. Signed-off-by: Peter Maydell --- hw/intc/omap_intc.c | 276 1 file changed, 276 deletions(-) diff --git a/hw/intc/omap_intc.c b/hw/intc/omap_intc.c index 435c47600fc..c14b22d3819 100644 --- a/hw/intc/o

[PATCH for-9.2 52/53] hw/dma: Remove omap_dma4 device

The omap_dma4 device was only used in the OMAP2 SoC, which has been removed. Signed-off-by: Peter Maydell --- include/hw/arm/omap.h | 1 - hw/dma/omap_dma.c | 451 +- 2 files changed, 3 insertions(+), 449 deletions(-) diff --git a/include/hw/arm/oma

[PATCH for-9.2 05/53] hw/ide: Remove DSCM-1XXXX microdrive device model

The DSCM-1 microdrive device model was used only by the XScale-based Zaurus machine types. Now they have been removed, we can delete this device too. Signed-off-by: Peter Maydell --- include/hw/pcmcia.h | 3 - hw/ide/microdrive.c | 644 hw/ide/

[PATCH for-9.2 16/53] hw/sd: Remove pxa2xx_mmci.c

Remove the pxa2xx-specific pxa2xx_mmci device. Signed-off-by: Peter Maydell --- include/hw/arm/pxa.h | 10 - hw/sd/pxa2xx_mmci.c | 594 --- hw/sd/meson.build| 1 - hw/sd/trace-events | 4 - 4 files changed, 609 deletions(-) delete mode 100644

[PATCH for-9.2 39/53] hw/char: Remove omap2_uart

Remove the OMAP2 specific code from omap_uart.c. Signed-off-by: Peter Maydell --- include/hw/arm/omap.h | 5 -- hw/char/omap_uart.c | 113 -- 2 files changed, 118 deletions(-) diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h index b569580b09

[PATCH for-9.2 41/53] hw/sd: Remove omap2_mmc device

Remove the OMAP2 specific code from omap_mmc.c. Signed-off-by: Peter Maydell --- include/hw/arm/omap.h | 5 hw/sd/omap_mmc.c | 63 --- 2 files changed, 68 deletions(-) diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h index 67bb83dff5d

[PATCH for-9.2 28/53] hw/input: Remove tsc2005 touchscreen controller

Remove the tsc2005 touchscreen controller, which was only used by the n800 and n810 machines. Signed-off-by: Peter Maydell --- MAINTAINERS| 1 - include/hw/input/tsc2xxx.h | 5 - hw/input/tsc2005.c | 571 - hw/input/Kconfig

[PATCH for-9.2 06/53] hw/display: Remove tc6393xb device

The tc6393xb was used only by the XScale-based Zaurus machine types. Now they have been removed we can remove this device too. Signed-off-by: Peter Maydell --- MAINTAINERS | 2 - include/hw/display/tc6393xb.h | 21 -- hw/display/tc6393xb.c | 568 -

[PATCH for-9.2 12/53] hw/arm: Remove 'z2' machine

The 'z2' machine was deprecated in 9.0, so we can remove it for 9.2. Signed-off-by: Peter Maydell --- MAINTAINERS | 1 - configs/devices/arm-softmmu/default.mak | 1 - hw/arm/z2.c | 355 hw/arm/Kconfig

[PATCH for-9.2 07/53] hw/arm/KConfig: Replace ZAURUS with ZAURUS_SCOOP

The ZAURUS KConfig symbol used to do multiple things: * pull in the tc6393xb display device * pull in the Zaurus SCOOP GPIO device * pull in hw/block/nand.c code * pull in hw/block/ecc.c code and was used by multiple machine types in the Zaurus family. Now that we've removed all the Zaurus mac

[PATCH for-9.2 13/53] hw/arm: Remove STRONGARM->PXA2XX dependency

Currently the STRONGARM KConfig symbol pulls in PXA2XX. Since we've now removed all the true uses of PXA2XX, we'd like to remove the PXA2XX symbol too. To permit that, make STRONGARM directly select the things it truly depends on: * pxa25x-timer * SSI Signed-off-by: Peter Maydell --- hw/arm/Kc

[PATCH for-9.2 46/53] hw/block: Remove ecc

The ecc.c code was used only by the PXA2xx and OMAP2 SoC devices, which we have removed, so it is now completely unused. Note that hw/misc/eccmemctl.c does not in fact use any of the code frome ecc.c, so that KConfig dependency was incorrect. Signed-off-by: Peter Maydell --- include/hw/block/fl

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