John Snow writes:
> On Fri, Aug 30, 2024 at 7:09 AM Markus Armbruster wrote:
>
>> John Snow writes:
>>
>> > qemu.git/python/setup.cfg disallows checking in any code with "XXX",
>> > "FIXME" or "TODO" in the comments. Soften the restriction to only
>> > prohibit "FIXME", and change the two occur
On 2024/08/31 0:05, Peter Xu wrote:
On Fri, Aug 30, 2024 at 03:11:38PM +0900, Akihiko Odaki wrote:
On 2024/08/30 4:48, Peter Xu wrote:
On Thu, Aug 29, 2024 at 01:39:36PM +0900, Akihiko Odaki wrote:
I am calling the fact that embedded memory regions are accessible in
instance_finalize() "live".
The new option '-qemu-children' makes it so that on `execve` the child
process will be launch by the same `qemu` executable that is currently
running along with its current commandline arguments.
The motivation for the change is to make it so that plugins running
through `qemu` can continue to run
On Fri, Aug 30, 2024 at 3:36 PM Noah Goldstein wrote:
>
> The new option '-qemu-children' makes it so that on `execve` the child
> process will be launch by the same `qemu` executable that is currently
> running along with its current commandline arguments.
>
> The motivation for the change is to
On Wed, Aug 28, 2024 at 5:23 AM Mark Cave-Ayland
wrote:
>
> This tests the Fifo8 implementation for basic operations as well as testing
> for
> the correct *_bufptr() including handling wraparound of the internal FIFO
> buffer.
>
> Signed-off-by: Mark Cave-Ayland
Reviewed-by: Octavian Purdila
On Wed, Aug 28, 2024 at 5:23 AM Mark Cave-Ayland
wrote:
>
> This is a wrapper function around fifo8_peekpop_buf() that allows the caller
> to
> peek into FIFO, including handling the case where there is a wraparound of the
> internal FIFO buffer.
>
> Signed-off-by: Mark Cave-Ayland
Reviewed-by:
On Wed, Aug 28, 2024 at 5:23 AM Mark Cave-Ayland
wrote:
>
> This allows uses to peek the byte at the current head of the FIFO.
>
> Signed-off-by: Mark Cave-Ayland
Reviewed-by: Octavian Purdila
> ---
> include/qemu/fifo8.h | 11 +++
> util/fifo8.c | 6 ++
> 2 files changed
On Wed, Aug 28, 2024 at 5:23 AM Mark Cave-Ayland
wrote:
>
> Pass the do_pop value from fifo8_peekpop_buf() to fifo8_peekpop_bufptr() to
> allow peeks to the FIFO buffer, including adjusting the skip parameter to
> handle the case where the internal FIFO buffer wraps around.
>
> Signed-off-by: Mark
On Wed, Aug 28, 2024 at 5:23 AM Mark Cave-Ayland
wrote:
>
> The fifo8_pop_buf() function will soon also be used for peek operations, so
> rename
> the function accordingly. Create a new fifo8_pop_buf() wrapper function that
> can
> be used by existing callers.
>
> Signed-off-by: Mark Cave-Ayland
On Wed, Aug 28, 2024 at 5:23 AM Mark Cave-Ayland
wrote:
>
> The upcoming peek functionality will require passing a non-zero value to
> fifo8_peekpop_bufptr().
>
> Signed-off-by: Mark Cave-Ayland
Reviewed-by: Octavian Purdila
> ---
> util/fifo8.c | 4 ++--
> 1 file changed, 2 insertions(+), 2
On Wed, Aug 28, 2024 at 5:23 AM Mark Cave-Ayland
wrote:
>
> The skip parameter specifies the number of bytes to be skipped from the
> current
> FIFO head before the peek or pop operation.
>
> Signed-off-by: Mark Cave-Ayland
Reviewed-by: Octavian Purdila
> ---
> util/fifo8.c | 12 +++-
On Wed, Aug 28, 2024 at 5:23 AM Mark Cave-Ayland
wrote:
>
> Rather than operate on fifo->head directly, introduce a new head variable
> which is
> set to the value of fifo->head and use it instead. This is to allow future
> adjustment of the head position within the internal FIFO buffer.
>
> Sign
On Wed, Aug 28, 2024 at 5:23 AM Mark Cave-Ayland
wrote:
>
> This is to emphasise that the function returns a pointer to the internal FIFO
> buffer.
>
> Signed-off-by: Mark Cave-Ayland
Reviewed-by: Octavian Purdila
> ---
> util/fifo8.c | 8
> 1 file changed, 4 insertions(+), 4 deletio
From: Bryan Zhang
Adds an integration test for 'qatzip'.
Reviewed-by: Fabiano Rosas
Signed-off-by: Bryan Zhang
Signed-off-by: Hao Xiang
Signed-off-by: Yichen Wang
---
tests/qtest/migration-test.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/tests/qtest/mi
From: Yuan Liu
add Intel QATzip compression method introduction
Reviewed-by: Nanhai Zou
Reviewed-by: Peter Xu
Reviewed-by: Fabiano Rosas
Signed-off-by: Yuan Liu
Signed-off-by: Yichen Wang
---
docs/devel/migration/features.rst | 1 +
docs/devel/migration/qatzip-compression.rst |
From: Bryan Zhang
Adds support for migration parameters to control QATzip compression
level.
Acked-by: Markus Armbruster
Signed-off-by: Bryan Zhang
Signed-off-by: Hao Xiang
Signed-off-by: Yichen Wang
---
migration/migration-hmp-cmds.c | 4
migration/options.c| 34 +
From: Bryan Zhang
Add a 'qatzip' feature, which is automatically disabled, and which
depends on the QATzip library if enabled.
Reviewed-by: Fabiano Rosas
Signed-off-by: Bryan Zhang
Signed-off-by: Hao Xiang
Signed-off-by: Yichen Wang
---
meson.build | 10 ++
meson_o
v9:
- Rebase changes on top of cec99171931ea79215c79661d33423ac84e63b6e;
- Address comments and add Review-by in commit messages;
v8:
- Rebase changes on top of 2eefd4fcec4b8fe41ceee2a8f00cdec1fe81b75c;
- Fix typo and grammars in documentation and comments;
v7:
- Rebase changes on top of 0173b9
From: Bryan Zhang
Adds support for 'qatzip' as an option for the multifd compression
method parameter, and implements using QAT for 'qatzip' compression and
decompression.
Acked-by: Markus Armbruster
Reviewed-by: Fabiano Rosas
Reviewed-by: Prasad Pandit
Signed-off-by: Bryan Zhang
Signed-off-
Hi Richard,
On 8/29/24 7:16 PM, Richard Henderson wrote:
On 8/30/24 06:13, Gustavo Romero wrote:
1 .text 1e60 40001000 40001000 00011000 2**12
4 .data 00012000 4020 4020 0002 2**12
4040 g .data 00
Am Fri, 30 Aug 2024 18:34:52 +0100
schrieb Peter Maydell :
> The TYPE_NUBUS_DEVICE class lets the user specify the nubus slot
> using an int32 "slot" QOM property. Its realize method doesn't do
> any range checking on this value, which Coverity notices by way of
> the possibility that 'nd->slot *
Am Fri, 30 Aug 2024 18:34:51 +0100
schrieb Peter Maydell :
> The datasheets for the SoC and board we model here are still
> available from the NXP website; add their URLs and titles for
> future reference.
>
> Signed-off-by: Peter Maydell
> ---
> hw/m68k/mcf5208.c | 8
> 1 file changed
Am Fri, 30 Aug 2024 18:34:50 +0100
schrieb Peter Maydell :
> In m5208_sys_read(), we have a loop of n from 0 to 31, and we
> calculate (2u << n). For the n == 31 iteration this will shift off
> the top of the unsigned 32 bit integer.
>
> This is harmless, because we're going to stop the loop wit
On 8/30/2024 1:05 AM, Eugenio Perez Martin wrote:
On Fri, Aug 30, 2024 at 6:20 AM Si-Wei Liu wrote:
On 8/29/2024 9:53 AM, Eugenio Perez Martin wrote:
On Wed, Aug 21, 2024 at 2:56 PM Jonah Palmer wrote:
Decouples the IOVA allocator from the IOVA->HVA tree and instead adds
the allocated I
Also, leading underscores are supposed to be reserved for compiler
implementations (and there only needs to be a single trailing
underscore) so it should really be:
__CXL_Early_Discovery_TABLE_H__ -> CXL_EARLY_DISCOVERY_TABLE_H_
--
Rebecca
On 8/30/2024 12:06 PM, Michael D Kinney via groups.
"Maciej S. Szmigiero" writes:
> From: "Maciej S. Szmigiero"
>
> Add a basic support for receiving device state via multifd channels -
> channels that are shared with RAM transfers.
>
> To differentiate between a device state and a RAM packet the packet
> header is read first.
>
> Depending wheth
On Fri, Aug 30, 2024 at 10:09:25AM +0200, Cédric Le Goater wrote:
> Hello,
>
>
> > > > I solved the problem by adding support for IBM Bonnell (which
> > > > instantiates
> > > > the TPM chip through its devicetree file, similar to tacoma-bmc) to my
> > > > local
> > > > copy of qemu.
> > >
> >
And by the way, feel free to integrate this with your other series (as
it's a very similar topic) in a v3, so we can review both at the same time.
Thanks,
Pierrick
On 8/30/24 12:30, Pierrick Bouvier wrote:
Hi Rowan,
thanks for this good complement on the virt address read function.
However,
Hi Rowan,
thanks for this good complement on the virt address read function.
However, to be able to merge a new plugins API function, we must have a
concrete usage of it, through one of the existing plugin.
What could be a good demonstration of value brought by being able to
read a physical ad
"Maciej S. Szmigiero" writes:
> From: "Maciej S. Szmigiero"
>
> load_finish SaveVMHandler allows migration code to poll whether
> a device-specific asynchronous device state loading operation had finished.
>
> In order to avoid calling this handler needlessly the device is supposed
> to notify t
On 8/30/24 08:25, Alex Bennée wrote:
At first I thought I could compile the user-mode test for system mode
however we already have a fairly comprehensive test case for system
mode in "memory" so lets use that.
First we extend the test to report where the test_data region is. Then
we expand the p
On 8/29/24 02:03, Alex Bennée wrote:
Pierrick Bouvier writes:
Add an explicit test to check expected memory values are read/written.
8,16,32 load/store are tested for all arch.
64,128 load/store are tested for aarch64/x64.
atomic operations (8,16,32,64) are tested for x64 only.
By default, at
"Maciej S. Szmigiero" writes:
> From: "Maciej S. Szmigiero"
>
> qemu_loadvm_load_state_buffer() and its load_state_buffer
> SaveVMHandler allow providing device state buffer to explicitly
> specified device via its idstr and instance id.
>
> Signed-off-by: Maciej S. Szmigiero
Reviewed-by: Fabi
"Maciej S. Szmigiero" writes:
> From: "Maciej S. Szmigiero"
>
> Since device state transfer via multifd channels requires multifd
> channels with packets and is currently not compatible with multifd
> compression add an appropriate query function so device can learn
> whether it can actually mak
This patch allows for easier manipulation of the cache description
register, CCSIDR. Which is helpful for testing as well. Currently
numbers get hard-coded and might be prone to errors.
Therefore, this patch adds wrappers for different types of CPUs
available in tcg to decribe caches. Two function
On Fri, 30 Aug 2024 17:29:59 +0100
Peter Maydell wrote:
> On Fri, 30 Aug 2024 at 17:19, Alireza Sanaee
> wrote:
> >
> > Add wrapper for different types of CPUs available in tcg to decribe
> > caches. Two functions `make_ccsidr32` and `make_ccsidr64`
> > describing descriptions. The 32 bit versio
On Fri, Aug 30, 2024 at 7:09 AM Markus Armbruster wrote:
> John Snow writes:
>
> > qemu.git/python/setup.cfg disallows checking in any code with "XXX",
> > "FIXME" or "TODO" in the comments. Soften the restriction to only
> > prohibit "FIXME", and change the two occurrences of "FIXME" in qapi to
On Fri, Aug 30, 2024 at 7:20 AM Markus Armbruster wrote:
> John Snow writes:
>
> > This is being done for the sake of unifying the linting and static type
> > analysis configurations between scripts/qapi and python/qemu/*.
> >
> > With this change, the qapi module will now be checked by mypy, fl
"Maciej S. Szmigiero" writes:
> From: "Maciej S. Szmigiero"
>
> This is necessary for multifd_send() to be able to be called
> from multiple threads.
>
> Signed-off-by: Maciej S. Szmigiero
> ---
> migration/multifd.c | 24 ++--
> 1 file changed, 18 insertions(+), 6 deletion
For this MdePkg change to add an ACPI table type, do you mind opening a PR?
There are some minor code style issues that need to be addressed.
Structure type names and define names should be all upper case.
__CXL_Early_Discovery_TABLE_H__ -> __CXL_EARLY_DISCOVERY_TABLE_H__
File names sho
In aspeed_gpio_update() we calculate "mask = 1 << gpio", where
gpio can be between 0 and 31. Coverity complains about this
because 1 << 31 won't fit in a signed integer.
For QEMU this isn't an error because we enable -fwrapv,
but we can keep Coverity happy by doing the shift on
unsigned numbers.
On Fri, Aug 30, 2024 at 7:29 AM Daniel P. Berrangé
wrote:
> On Fri, Aug 30, 2024 at 01:20:35PM +0200, Markus Armbruster wrote:
> > John Snow writes:
> >
> > > This is being done for the sake of unifying the linting and static type
> > > analysis configurations between scripts/qapi and python/qem
30.08.2024 17:50, Andrew Jones пишет:
> On Fri, Aug 30, 2024 at 02:05:05PM GMT, Vladimir Isaev wrote:
>> Hi Andrew,
>>
>> 29.08.2024 11:40, Andrew Jones wrote:
>>> While the spec doesn't state it, setting timecmp to UINT64_MAX is
>>> another way to stop a timer, as it's considered setting the ne
The TYPE_NUBUS_DEVICE class lets the user specify the nubus slot
using an int32 "slot" QOM property. Its realize method doesn't do
any range checking on this value, which Coverity notices by way of
the possibility that 'nd->slot * NUBUS_SUPER_SLOT_SIZE' might
overflow the 32-bit arithmetic it is u
This patchset fixes a couple of very minor Coverity issues: one
"shift off top of integer", and one "overflow in multiplication".
Neither will happen in normal use. I would not bother backporting
either fix to stable.
I threw in also a patch adding a comment to mcf5208.c giving the URLs
of the da
In m5208_sys_read(), we have a loop of n from 0 to 31, and we
calculate (2u << n). For the n == 31 iteration this will shift off
the top of the unsigned 32 bit integer.
This is harmless, because we're going to stop the loop with n == 31
anyway, but we can avoid the error by using 64-bit arithmeti
The datasheets for the SoC and board we model here are still
available from the NXP website; add their URLs and titles for
future reference.
Signed-off-by: Peter Maydell
---
hw/m68k/mcf5208.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/m68k/mcf5208.c b/hw/m68k/mcf5208.c
index
On 8/30/2024 3:25 AM, Cédric Le Goater wrote:
On 8/29/24 22:35, Mike Kowal wrote:
On 8/29/2024 7:29 AM, Cédric Le Goater wrote:
On 8/1/24 22:30, Michael Kowal wrote:
From: Glenn Miles
Current code was updating the PIPR inside the xive_tctx_accept()
function
instead of the xive_tctx_set_c
v13 for riscv zicfilp and zicfiss extensions support in qemu.
zicfilp and zicfiss spec pdf
https://github.com/riscv/riscv-cfi/releases/download/v1.0/riscv-cfi.pdf
github sources to spec
https://github.com/riscv/riscv-cfi
I have kept names of `cpu_get_bcfien` or `cpu_get_fcfien` same and didn't c
Implements setting lp expected when `jalr` is encountered and implements
`lpad` instruction of zicfilp. `lpad` instruction is taken out of
auipc x0, . This is an existing HINTNOP space. If `lpad` is
target of an indirect branch, cpu checks for 20 bit value in x7 upper
with 20 bit value embedded in
sw check exception support was recently added. This patch further augments
sw check exception by providing support for additional code which is
provided in *tval. Adds `sw_check_code` field in cpuarchstate. Whenever
sw check exception is raised *tval gets the value deposited in
`sw_check_code`.
Si
zicfilp [1] riscv cpu extension enables forward control flow integrity.
If enabled, all indirect calls must land on a landing pad instruction.
This patch sets up space for zicfilp extension in cpuconfig. zicfilp
is dependend on zicsr.
[1] - https://github.com/riscv/riscv-cfi
Signed-off-by: Deepa
sspush and sspopchk have equivalent compressed encoding taken from zcmop.
cmop.1 is sspush x1 while cmop.5 is sspopchk x5. Due to unusual encoding
for both rs1 and rs2 from space bitfield, this required a new codec.
Signed-off-by: Deepak Gupta
Acked-by: Alistair Francis
---
disas/riscv.c | 19 +
Signed-off-by: Deepak Gupta
Co-developed-by: Jim Shu
Co-developed-by: Andy Chiu
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
disas/riscv.c | 18 +-
disas/riscv.h | 2 ++
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/r
zicfiss has following instructions
- sspopchk: pops a value from shadow stack and compares with x1/x5.
If they dont match, reports a sw check exception with tval = 3.
- sspush: pushes value in x1/x5 on shadow stack
- ssrdp: reads current shadow stack
- ssamoswap: swaps contents of shadow sta
zicfilp protects forward control flow (if enabled) by enforcing all
indirect call and jmp must land on a landing pad instruction `lpad`. If
target of an indirect call or jmp is not `lpad` then cpu/hart must raise
a sw check exception with tval = 2.
This patch implements the mechanism using TCG. Ta
Signed-off-by: Deepak Gupta
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c5ebcefeb5..2592465e24 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1485,6 +1485,7 @@ const RISCVCPUM
zicfiss [1] riscv cpu extension enables backward control flow integrity.
This patch sets up space for zicfiss extension in cpuconfig. And imple-
ments dependency on A, zicsr, zimop and zcmop extensions.
[1] - https://github.com/riscv/riscv-cfi
Signed-off-by: Deepak Gupta
Co-developed-by: Jim Sh
zicfilp introduces a new state elp ("expected landing pad") in cpu.
During normal execution, elp is idle (NO_LP_EXPECTED) i.e not expecting
landing pad. On an indirect call, elp moves LP_EXPECTED. When elp is
LP_EXPECTED, only a subsquent landing pad instruction can set state back
to NO_LP_EXPECTED
Shadow stack instructions can be decoded as zimop / zcmop or shadow stack
instructions depending on whether shadow stack are enabled at current
privilege. This requires a TB flag so that correct TB generation and correct
TB lookup happens. `DisasContext` gets a field indicating whether bcfi is
enab
Enable disassembly for sspush, sspopchk, ssrdp & ssamoswap.
Disasembly is only enabled if zimop and zicfiss ext is set to true.
Signed-off-by: Deepak Gupta
Acked-by: Alistair Francis
---
disas/riscv.c | 40 +++-
disas/riscv.h | 1 +
2 files changed, 40 inser
zicfiss introduces a new state ssp ("shadow stack register") in cpu.
ssp is expressed as a new unprivileged csr (CSR_SSP=0x11) and holds
virtual address for shadow stack as programmed by software.
Shadow stack (for each mode) is enabled via bit3 in *envcfg CSRs.
Shadow stack can be enabled for a m
This patch adds one more word for tcg compile which can be obtained during
unwind time to determine fault type for original operation (example AMO).
Depending on that, fault can be promoted to store/AMO fault.
Signed-off-by: Deepak Gupta
Suggested-by: Richard Henderson
Reviewed-by: Richard Hende
Signed-off-by: Deepak Gupta
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 55754cb374..c9aeffee4e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1481,6 +1481,7 @@ const RISCVCPUM
Execution environment config CSR controlling user env and current
privilege state shouldn't be limited to qemu-system only. *envcfg
CSRs control enabling of features in next lesser mode. In some cases
bits *envcfg CSR can be lit up by kernel as part of kernel policy or
software (user app) can choos
elp state is recorded in *status on trap entry (less privilege to higher
privilege) and restored in elp from *status on trap exit (higher to less
privilege).
Additionally this patch introduces a forward cfi helper function to
determine if current privilege has forward cfi is enabled or not based o
zicfiss protects shadow stack using new page table encodings PTE.W=1,
PTE.R=0 and PTE.X=0. This encoding is reserved if zicfiss is not
implemented or if shadow stack are not enabled.
Loads on shadow stack memory are allowed while stores to shadow stack
memory leads to access faults. Shadow stack ac
Extra word 2 is stored during tcg compile and `decode_save_opc` needs
additional argument in order to pass the value. This will be used during
unwind to get extra information about instruction like how to massage
exceptions. Updated all callsites as well.
Resolves: https://gitlab.com/qemu-project/
sspush/sspopchk have compressed encodings carved out of zcmops.
compressed sspush is designated as c.mop.1 while compressed sspopchk
is designated as c.mop.5.
Note that c.sspush x1 exists while c.sspush x5 doesn't. Similarly
c.sspopchk x5 exists while c.sspopchk x1 doesn't.
Signed-off-by: Deepak
On Thu, Aug 29, 2024 at 10:56:41PM -0700, Deepak Gupta wrote:
On Fri, Aug 30, 2024 at 03:20:04PM +1000, Richard Henderson wrote:
On 8/30/24 09:34, Deepak Gupta wrote:
+bool cpu_get_bcfien(CPURISCVState *env)
It occurs to me that a better name would be "cpu_get_sspen".
The backward cfi is mere
On Fri, 30 Aug 2024 at 17:19, Alireza Sanaee wrote:
>
> Add wrapper for different types of CPUs available in tcg to decribe
> caches. Two functions `make_ccsidr32` and `make_ccsidr64`
> describing descriptions. The 32 bit version receives extra parameters
> that became unknown later in 64 bit.
>
>
On Mon, 26 Aug 2024 at 04:12, Mauro Carvalho Chehab
wrote:
>
> Em Sun, 25 Aug 2024 12:34:14 +0100
> Peter Maydell escreveu:
>
> > On Sun, 25 Aug 2024 at 04:46, Mauro Carvalho Chehab
> > wrote:
> > >
> > > Accurately injecting an ARM Processor error ACPI/APEI GHES
> > > error record requires the
Add wrapper for different types of CPUs available in tcg to decribe
caches. Two functions `make_ccsidr32` and `make_ccsidr64`
describing descriptions. The 32 bit version receives extra parameters
that became unknown later in 64 bit.
For CCSIDR register, 32 bit version follows specification [1].
Co
This commit adds support for the `openat2()` syscall in the
`linux-user` userspace emulator.
It is implemented by extracting a new helper `maybe_do_fake_open()`
out of the exiting `do_guest_openat()` and share that with the
new `do_guest_openat2()`. Unfortunatly we cannot just make
do_guest_openat
From: Michael Vogt
Hi,
This is v3 of the openat2 support in linux-user. Thanks again for the
excellent second round of feedback from Richard Henderson.
This version tries to be closer to the kernels behavior, i.e. now
do_openat2() uses a new copy_struct_from_user() helper that is very
similar
Hi!
While running a lot of tests (i.e. with a very loaded machine), I noticed
that tests/avocado/riscv_opensbi.py is very flaky when the host machine is
slow. I can easily reproduce the problem when running a big compilation job
on all CPUs in the background and then run the riscv_opensbi.p
At first I thought I could compile the user-mode test for system mode
however we already have a fairly comprehensive test case for system
mode in "memory" so lets use that.
First we extend the test to report where the test_data region is. Then
we expand the pdot() function to track the total numbe
In vfp.decode we have the names of the VFNMA and VFNMS instructions
the wrong way around. The architecture says that bit 6 is the 'op'
bit, which is 1 for VFNMA and 1 for VFNMS, but we label these two
lines of decode the other way around. This doesn't cause any
user-visible problem because in the
On Fri, Aug 30, 2024 at 03:11:38PM +0900, Akihiko Odaki wrote:
> On 2024/08/30 4:48, Peter Xu wrote:
> > On Thu, Aug 29, 2024 at 01:39:36PM +0900, Akihiko Odaki wrote:
> > > > > I am calling the fact that embedded memory regions are accessible in
> > > > > instance_finalize() "live". A device can p
Convert the s390 CPU to the Resettable interface. This is slightly
more involved than the other CPU types were (see commits
9130cade5fc22..d66e64dd006df) because S390 has its own set of
different kinds of reset with different behaviours that it needs to
trigger.
We handle this by adding these res
Convert the TYPE_CCW_DEVICE to three-phase reset. This is a
device class which is subclassed, so it needs to be three-phase
before we can convert the subclass.
Signed-off-by: Peter Maydell
---
hw/s390x/ccw-device.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/s39
We used to need the transitional_function machinery to handle bus
classes and device classes which still used their legacy reset
handling. We have now converted all bus classes to three phase
reset, and simplified the device class legacy reset so it is just an
adapting wrapper function around regi
Now that all devices which still implement a the legacy reset method
register it via device_class_legacy_reset(), we can simplify the
handling of these devices. Instead of using the complex
Resettable::get_transitional_function machinery, we register a hold
phase method which invokes the DeviceCla
Convert the virtio-ccw code to three-phase reset. This allows us to
remove a call to device_class_set_parent_reset(), replacing it with
the three-phase equivalent resettable_class_set_parent_phases().
Removing all the device_class_set_parent_reset() uses will allow us
to remove some of the glue co
Currently we have transitional machinery between legacy reset
and three phase reset that works in two directions:
* if you invoke three phase reset on a device which has set
the DeviceClass::legacy_reset method, we detect this in
device_get_transitional_reset() and arrange that we call
th
Rename the DeviceClass::reset field to legacy_reset; this is helpful
both in flagging up that it's best not used in new code and in
making it easy to search for where it's being used still.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
incl
The Alpha and HPPA CPU class structs include a 'parent_reset'
field which is never used; delete them.
(These targets don't seem to implement reset at all; if they did they
should do it using the three-phase reset mechanism, which uses a
'ResettablePhases parent_phases' field instead of the old
'De
There are no callers of device_class_set_parent_reset() left in the tree,
as they've all been converted to use three-phase reset and the
corresponding resettable_class_set_parent_phases() function.
Remove device_class_set_parent_reset().
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-
The main aim of this patchseries is to remove the two remaining uses
of device_class_set_parent_reset() in the tree, which are virtio-ccw
and the s390 CPU class. Doing that lets us do some followup cleanup.
(The diffstat looks alarming but is almost all coccinelle automated
changes.)
Changes v1->v
Define a device_class_set_legacy_reset() function which
sets the DeviceClass::reset field. This serves two purposes:
* it makes it clearer to the person writing code that
DeviceClass::reset is now legacy and they should look for
the new alternative (which is Resettable)
* it makes it easier
On Fri, Aug 30, 2024 at 02:05:05PM GMT, Vladimir Isaev wrote:
> Hi Andrew,
>
> 29.08.2024 11:40, Andrew Jones wrote:
> > While the spec doesn't state it, setting timecmp to UINT64_MAX is
> > another way to stop a timer, as it's considered setting the next
> > timer event to occur at infinity.
>
On Fri, Aug 30, 2024 at 3:52 PM Jonah Palmer wrote:
>
>
>
> On 8/30/24 4:05 AM, Eugenio Perez Martin wrote:
> > On Fri, Aug 30, 2024 at 6:20 AM Si-Wei Liu wrote:
> >>
> >>
> >>
> >> On 8/29/2024 9:53 AM, Eugenio Perez Martin wrote:
> >>> On Wed, Aug 21, 2024 at 2:56 PM Jonah Palmer
> >>> wrote:
On Fri, Aug 30, 2024 at 3:58 PM Jonah Palmer wrote:
>
>
>
> On 8/29/24 12:55 PM, Eugenio Perez Martin wrote:
> > On Wed, Aug 21, 2024 at 2:56 PM Jonah Palmer
> > wrote:
> >>
> >> Implements a GPA->IOVA and IOVA->SVQ HVA tree for handling mapping,
> >> unmapping, and translations for guest and ho
On Wed, Aug 28, 2024 at 06:59:20PM -0700, Sia Jee Heng wrote:
> Update the virt SPCR golden reference file for RISC-V to accommodate the
> SPCR Table revision 4 [1], utilizing the iasl binary compiled from the
> latest ACPICA repository. The SPCR table has been modified to
> adhere to the revision
On 8/29/24 12:55 PM, Eugenio Perez Martin wrote:
On Wed, Aug 21, 2024 at 2:56 PM Jonah Palmer wrote:
Implements a GPA->IOVA and IOVA->SVQ HVA tree for handling mapping,
unmapping, and translations for guest and host-only memory,
respectively.
By splitting up a full IOVA->HVA tree (containi
On 8/30/24 4:05 AM, Eugenio Perez Martin wrote:
On Fri, Aug 30, 2024 at 6:20 AM Si-Wei Liu wrote:
On 8/29/2024 9:53 AM, Eugenio Perez Martin wrote:
On Wed, Aug 21, 2024 at 2:56 PM Jonah Palmer wrote:
Decouples the IOVA allocator from the IOVA->HVA tree and instead adds
the allocated IO
Mostly a straight-forward conversion. Looks like we can simply drop
the avocado datadrainer stuff when not using the avocado framework
anymore.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
MAINTAINERS |
The machine_microblaze.py file contained two tests, one for each
endianness. Since we only support one QEMU target binary per file
in the new functional test environment, we have to split this file
up into two files now.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signe
From: Philippe Mathieu-Daudé
Straight forward conversion. Update the SHA1 hashes to
SHA256 hashes since SHA1 should not be used anymore nowadays.
Expose cpio_extract() in qemu_test.utils for possible reuse.
Signed-off-by: Philippe Mathieu-Daudé
Message-ID: <20240822104238.75045-3-phi...@linaro.
The avocado_qemu.Test class has been renamed a while back in commit
2283b627bc ("tests/avocado: Rename avocado_qemu.Test -> QemuSystemTest"),
so we should reflect this now in the documentation, too.
Reviewed-by: Daniel P. Berrangé
Signed-off-by: Thomas Huth
---
docs/devel/testing/avocado.rst |
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