Re: [PATCH RESEND v9 7/9] rust: add crate to expose bindings and interfaces

🎱 On Fri, 30 Aug 2024, 04:19 Junjie Mao, wrote: > On 8/28/2024 9:08 PM, Alex Bennée wrote: > > Manos Pitsidianakis writes: > > > >> Add rust/qemu-api, which exposes rust-bindgen generated FFI bindings and > >> provides some declaration macros for symbols visible to the rest of > >> QEMU. > > >

Re: [PATCH] chardev: allow specifying finer-grained reconnect timeouts

Eric Blake writes: > On Thu, Aug 29, 2024 at 01:56:43PM GMT, Markus Armbruster wrote: >> Daniil Tatianin writes: >> >> > The "reconnect" option only allows to specify the time in seconds, >> > which is way too long for certain workflows. > > ... >> > @@ -287,7 +292,8 @@ >> > '*teln

[PATCH v2 14/14] tcg/riscv: Enable native vector support for TCG host

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.h | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index eb5129a976..b8f553207e 100644 --- a/tcg/riscv/tcg-target.h +++

[PATCH v2 13/14] tcg/riscv: Implement vector roti/v/x shi ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.c.inc | 98 +- tcg/riscv/tcg-target.h | 8 ++-- tcg/riscv/tcg-target.opc.h | 3 ++ 3 files changed, 104 insertions(+), 5 deletions(-) diff --git a/tcg/

[PATCH v2 12/14] tcg/riscv: Implement vector shs/v ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target-con-set.h | 1 + tcg/riscv/tcg-target.c.inc | 44 ++ tcg/riscv/tcg-target.h | 4 ++-- 3 files changed, 47 insertions(+), 2 deletions(-) diff --git

[PATCH v2 11/14] tcg/riscv: Implement vector min/max ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.c.inc | 29 + tcg/riscv/tcg-target.h | 2 +- 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.i

[PATCH v2 10/14] tcg/riscv: Implement vector sat/mul ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.c.inc | 36 tcg/riscv/tcg-target.h | 4 ++-- 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-

[PATCH v2 09/14] tcg/riscv: Implement vector neg ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.c.inc | 8 tcg/riscv/tcg-target.h | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 1e8c0fb031..4fc

[PATCH v2 08/14] tcg/riscv: Implement vector cmp ops

From: TANG Tiancheng 1.Address immediate value constraints in RISC-V Vector Extension 1.0 for comparison instructions. 2.Extend comparison results from mask registers to SEW-width elements, following recommendations in The RISC-V SPEC Volume I (Version 20240411). This aligns with TCG's cmp_ve

[PATCH v2 07/14] tcg/riscv: Add support for basic vector opcodes

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target-con-set.h | 2 ++ tcg/riscv/tcg-target-con-str.h | 1 + tcg/riscv/tcg-target.c.inc | 54 ++ tcg/riscv/tcg-target.h | 2 +- 4 files changed, 58 inse

[PATCH v2 06/14] tcg/riscv: Implement vector mov/dup{m/i}

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.c.inc | 54 ++ 1 file changed, 54 insertions(+) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 6f8814564a..b6b4bdc269 100644 ---

[PATCH v2 05/14] tcg/riscv: Implement vector load/store

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target-con-set.h | 2 + tcg/riscv/tcg-target.c.inc | 169 - 2 files changed, 167 insertions(+), 4 deletions(-) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/r

[PATCH v2 04/14] tcg/riscv: Add riscv vset{i}vli support

From: TANG Tiancheng In RISC-V, vector operations require initial configuration using the vset{i}vl{i} instruction. This instruction: 1. Sets the vector length (vl) in bytes 2. Configures the vtype register, which includes: SEW (Single Element Width) LMUL (vector register group multi

[PATCH v2 03/14] tcg/riscv: Add basic support for vector

From: Swung0x48 The RISC-V vector instruction set utilizes the LMUL field to group multiple registers, enabling variable-length vector registers. This implementation uses only the first register number of each group while reserving the other register numbers within the group. In TCG, each VEC_IR

[PATCH v2 02/14] util: Add RISC-V vector extension probe in cpuinfo

From: TANG Tiancheng Add support for probing RISC-V vector extension availability in the backend. This information will be used when deciding whether to use vector instructions in code generation. While the compiler doesn't support RISCV_HWPROBE_EXT_ZVE64X, we use RISCV_HWPROBE_IMA_V instead. S

[PATCH v2 01/14] tcg/op-gvec: Fix iteration step in 32-bit operation

From: TANG Tiancheng The loop in the 32-bit case of the vector compare operation was incorrectly incrementing by 8 bytes per iteration instead of 4 bytes. This caused the function to process only half of the intended elements. Signed-off-by: TANG Tiancheng Fixes: 9622c697d1 (tcg: Add gvec compa

[PATCH v2 00/14] tcg/riscv: Add support for vector

From: TANG Tiancheng This patch set introduces support for the RISC-V vector extension in TCG backend for RISC-V targets. v2: 1. Remove [PATCH v1 03/15] and use a simpler approach with fixed constraints at initialization in the backend instead of modifying register allocation constraints i

Re: [PATCH v4 6/7] memory: Do not create circular reference with subregion

On 2024/08/30 4:48, Peter Xu wrote: On Thu, Aug 29, 2024 at 01:39:36PM +0900, Akihiko Odaki wrote: I am calling the fact that embedded memory regions are accessible in instance_finalize() "live". A device can perform operations on its memory regions during instance_finalize() and we should be aw

Re: [PATCH v12 11/20] target/riscv: introduce ssp and enabling controls for zicfiss

On Fri, Aug 30, 2024 at 03:20:04PM +1000, Richard Henderson wrote: On 8/30/24 09:34, Deepak Gupta wrote: +bool cpu_get_bcfien(CPURISCVState *env) It occurs to me that a better name would be "cpu_get_sspen". The backward cfi is merely a consequence of the shadow stack. Want me to change cpu_g

Re: [PATCH for-9.2 00/10] s390: Convert virtio-ccw, cpu to three-phase reset, and followup cleanup

Quoting Peter Maydell (2024-08-29 17:53:02) > On Wed, 28 Aug 2024 at 09:13, Nico Boehr wrote: > > > > Quoting Nico Boehr (2024-08-26 14:08:20) > > > There was a little hickup without the fixup to patch 2, but after Nina > > > pushed the fixup, we did not observe any failures related to your > > >

Re: [PATCH v12 11/20] target/riscv: introduce ssp and enabling controls for zicfiss

On 8/30/24 09:34, Deepak Gupta wrote: +bool cpu_get_bcfien(CPURISCVState *env) It occurs to me that a better name would be "cpu_get_sspen". The backward cfi is merely a consequence of the shadow stack. +{ +/* no cfi extension, return false */ +if (!env_archcpu(env)->cfg.ext_zicfiss) {

Re: [PULL 2/3] hw/audio/virtio-snd: fix invalid param check

Cc: qemu-sta...@nongnu.org Without this patch, the virtio-sound device will not work in the next QEMU stable-8.2 and stable-9.0 versions. With best regards, Volker > From: Volker Rümelin > > Commit 9b6083465f ("virtio-snd: check for invalid param shift > operands") tries to prevent invalid para

Re: [RFC 1/2] vhost-vdpa: Decouple the IOVA allocator

On 8/29/2024 9:53 AM, Eugenio Perez Martin wrote: On Wed, Aug 21, 2024 at 2:56 PM Jonah Palmer wrote: Decouples the IOVA allocator from the IOVA->HVA tree and instead adds the allocated IOVA range to an IOVA-only tree (iova_map). This IOVA tree will hold all IOVA ranges that have been alloca

[RFC PATCH 1/2] hw/arm/sbsa-ref: Enable CXL Host Bridge by pxb-cxl

The memory layout places 1M space for 16 host bridge register regions in the sbsa-ref memmap. In addition, this creates a default pxb-cxl (bus_nr=0xfe) bridge with one cxl-rp on sbsa-ref. Signed-off-by: Yuquan Wang --- hw/arm/sbsa-ref.c | 54 --- 1 fil

[RFC PATCH 0/2] Sbsa-ref CXL Enablement

RFC because - Many contents are ported from Jonathan' patch on qemu virt design - Bring plenty of PCDs values and modifying the original PCIE values - Less experience and not particularly confident in ACPI area so this might be stupidly broken in a way I've not considered. Currently the base C

[RFC PATCH 2/2] hw/arm/sbsa-ref: Support CXL Fixed Memory Window

In order to provide CFMWs on sbsa-ref, this extends 1TB space from the hole above RAM Memory [SBSA_MEM] for CXL Fixed Memory Window. 0xA00 is chosen as the base address of this space because of 3 reasons: 1) It is more suitable to choose a static address instead of that implementation in v

[RFC PATCH edk2-platforms 0/2] add basic support for CXL on sbsa-ref

RFC because - Many contents are ported from Jonathan' patch on qemu virt design - Bring plenty of PCDs values and modifying the original PCIE values - Less experience and not particularly confident in ACPI area so this might be stupidly broken in a way I've not considered. This series leverage

[RFC PATCH edk2-platforms 1/2] SbsaQemu: Add acpi0016 & acpi0017 objects into DSDT

This adds relevant definitions and descriptions of acpi0016 and acpi0017 to support CXL. With the implementation of pxb-cxl on the original pcie host bridge, the previous space layout of mmio32 & mmio64 have to be divided to provide the mmio space for cxl host bridge. I'm not sure if the new spac

[RFC PATCH edk2-platforms 2/2] SbsaQemu: AcpiTables: Add CEDT Table

Provide CXL Early Discovery Table that describes the static CXL Platform Components of sbsa-ref. This adds a static CXL Host Bridge structure and a CXL Fixed Memory Window structure which are implemented as two independent space on sbsa-ref: [SBSA_CXL_HOST] & [SBSA_CXL_FIXED_WINDOW]. Signed-off-b

PING: [PATCH v3] target/i386/kvm: Refine VMX controls setting for backward compatibility

Dear Maintainers and Paolo, I hope this email finds you well. This is my second follow-up regarding the patch I submitted for review. I previously sent a reminder on July 23rd, but I have yet to receive any updates or further comments. I understand that you have many responsibilities, but I would

Re: [PATCH v12 04/20] target/riscv: save and restore elp state on priv transitions

On 8/30/24 09:34, Deepak Gupta wrote: elp state is recorded in *status on trap entry (less privilege to higher privilege) and restored in elp from *status on trap exit (higher to less privilege). Additionally this patch introduces a forward cfi helper function to determine if current privilege h

[RFC PATCH 1/1] MdePkg/IndustryStandard: add definitions for ACPI 6.4 CEDT

This adds #defines and struct typedefs for the various structure types in the ACPI 6.4 CXL Early Discovery Table (CEDT). Signed-off-by: Yuquan Wang --- MdePkg/Include/IndustryStandard/Acpi64.h | 5 ++ .../IndustryStandard/CXLEarlyDiscoveryTable.h | 69 +++ 2 files changed,

[RFC PATCH 0/1] MdePkg/IndustryStandard: add definitions for ACPI 6.4 CEDT

RFC because - Less experience and not particularly confident in edk2 area so this might be stupidly broken in a way I've not considered. I am trying to support cxl on Qemu sbsa-ref platform, but it relies on CXL ACPI elements within compiled UEFI flash instead of virt/i386 using qemu-build-Acpi

Re: [PATCH v12 01/20] target/riscv: expose *envcfg csr and priv to qemu-user as well

On 8/30/24 09:34, Deepak Gupta wrote: Execution environment config CSR controlling user env and current privilege state shouldn't be limited to qemu-system only. *envcfg CSRs control enabling of features in next lesser mode. In some cases bits *envcfg CSR can be lit up by kernel as part of kernel

Re: [PATCH v2 1/1] linux-user: add openat2 support in linux-user

On 8/30/24 00:44, Michael Vogt wrote: +static int maybe_do_fake_open(CPUArchState *cpu_env, int dirfd, + const char *fname, int flags, mode_t mode, + bool safe, bool *use_returned_fd) { g_autofree char *proc_name = NULL; cons

Re: [PATCH RESEND v9 7/9] rust: add crate to expose bindings and interfaces

On 8/28/2024 9:08 PM, Alex Bennée wrote: Manos Pitsidianakis writes: Add rust/qemu-api, which exposes rust-bindgen generated FFI bindings and provides some declaration macros for symbols visible to the rest of QEMU. As mentioned on IRC I'm hitting a compilation error that bisects to this com

Re: [PATCH v2 7/7] hw/net/can/xlnx-versal-canfd: Fix FIFO issues

Hi Pavel, On 8/29/2024 6:24 AM, Pavel Pisa wrote: > Generally, I agree that index should wrap up for cyclic FIFO > implementation and change looks logical to me but I do not > see and studied all consequences related to emulated HW. > > If that is confirmed or corrected by somebody from AMD/Xilin

Re: [PATCH] hw/misc: Add a virtual PCILeech device

Thanks for your comments, and let me answer the top-level questions first. Firstly, how useful is this to QEMU users in general? > It seems very specific. > > Secondly, there's no documentation here that explains > what it is, why users might care about it, or how to use it. > > Thirdly, it looks

Re: [PATCH 9/9] tests/unit: add test-fifo unit test

On Wed, Aug 28, 2024 at 10:25 PM Mark Cave-Ayland wrote: > > This tests the Fifo8 implementation for basic operations as well as testing > for > the correct *_bufptr() including handling wraparound of the internal FIFO > buffer. > > Signed-off-by: Mark Cave-Ayland Acked-by: Alistair Francis

Re: [PATCH 8/9] fifo8: introduce fifo8_peek() function

On Wed, Aug 28, 2024 at 10:26 PM Mark Cave-Ayland wrote: > > This allows uses to peek the byte at the current head of the FIFO. > > Signed-off-by: Mark Cave-Ayland Reviewed-by: Alistair Francis Alistair > --- > include/qemu/fifo8.h | 11 +++ > util/fifo8.c | 6 ++ > 2 fi

Re: [PATCH 7/9] fifo8: add fifo8_peek_buf() function

On Wed, Aug 28, 2024 at 10:25 PM Mark Cave-Ayland wrote: > > This is a wrapper function around fifo8_peekpop_buf() that allows the caller > to > peek into FIFO, including handling the case where there is a wraparound of the > internal FIFO buffer. > > Signed-off-by: Mark Cave-Ayland Reviewed-by

Re: [PATCH 6/9] fifo8: honour do_pop argument in fifo8_peekpop_buf()

On Wed, Aug 28, 2024 at 10:25 PM Mark Cave-Ayland wrote: > > Pass the do_pop value from fifo8_peekpop_buf() to fifo8_peekpop_bufptr() to > allow peeks to the FIFO buffer, including adjusting the skip parameter to > handle the case where the internal FIFO buffer wraps around. > > Signed-off-by: Mar

Re: [PATCH 5/9] fifo8: rename fifo8_pop_buf() to fifo8_peekpop_buf()

On Wed, Aug 28, 2024 at 10:25 PM Mark Cave-Ayland wrote: > > The fifo8_pop_buf() function will soon also be used for peek operations, so > rename > the function accordingly. Create a new fifo8_pop_buf() wrapper function that > can > be used by existing callers. > > Signed-off-by: Mark Cave-Aylan

Re: [PATCH 4/9] fifo8: replace fifo8_pop_bufptr() with fifo8_peekpop_bufptr() in fifo8_pop_buf()

On Wed, Aug 28, 2024 at 10:25 PM Mark Cave-Ayland wrote: > > The upcoming peek functionality will require passing a non-zero value to > fifo8_peekpop_bufptr(). > > Signed-off-by: Mark Cave-Ayland Reviewed-by: Alistair Francis Alistair > --- > util/fifo8.c | 4 ++-- > 1 file changed, 2 insert

Re: [PATCH 3/9] fifo8: add skip parameter to fifo8_peekpop_bufptr()

On Wed, Aug 28, 2024 at 10:24 PM Mark Cave-Ayland wrote: > > The skip parameter specifies the number of bytes to be skipped from the > current > FIFO head before the peek or pop operation. > > Signed-off-by: Mark Cave-Ayland Reviewed-by: Alistair Francis Alistair > --- > util/fifo8.c | 12 +

Re: [PATCH 2/9] fifo8: introduce head variable for fifo8_peekpop_bufptr()

On Wed, Aug 28, 2024 at 10:25 PM Mark Cave-Ayland wrote: > > Rather than operate on fifo->head directly, introduce a new head variable > which is > set to the value of fifo->head and use it instead. This is to allow future > adjustment of the head position within the internal FIFO buffer. > > Sig

Re: [PATCH 1/9] fifo8: rename fifo8_peekpop_buf() to fifo8_peekpop_bufptr()

On Wed, Aug 28, 2024 at 10:25 PM Mark Cave-Ayland wrote: > > This is to emphasise that the function returns a pointer to the internal FIFO > buffer. > > Signed-off-by: Mark Cave-Ayland Reviewed-by: Alistair Francis Alistair > --- > util/fifo8.c | 8 > 1 file changed, 4 insertions(+)

Re: [PATCH] target/riscv: Stop timer with infinite timecmp

On Thu, Aug 29, 2024 at 6:40 PM Andrew Jones wrote: > > While the spec doesn't state it, setting timecmp to UINT64_MAX is > another way to stop a timer, as it's considered setting the next > timer event to occur at infinity. And, even if the time CSR does > eventually reach UINT64_MAX, the very ne

Re: [PATCH v5 4/5] target/riscv: Add Smrnmi mnret instruction.

On Fri, Aug 30, 2024 at 2:12 AM Tommy Wu wrote: > > On Mon, Aug 19, 2024 at 11:49 AM Alistair Francis > wrote: > > > > On Fri, Aug 9, 2024 at 6:12 PM Tommy Wu wrote: > > > > > > This patch adds a new instruction `mnret`. `mnret` is an M-mode-only > > > instruction that uses the values in `mnepc

[PATCH v12 16/20] target/riscv: implement zicfiss instructions

zicfiss has following instructions - sspopchk: pops a value from shadow stack and compares with x1/x5. If they dont match, reports a sw check exception with tval = 3. - sspush: pushes value in x1/x5 on shadow stack - ssrdp: reads current shadow stack - ssamoswap: swaps contents of shadow sta

[PATCH v12 08/20] disas/riscv: enable `lpad` disassembly

Signed-off-by: Deepak Gupta Co-developed-by: Jim Shu Co-developed-by: Andy Chiu Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- disas/riscv.c | 18 +- disas/riscv.h | 2 ++ 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c b/disas/r

[PATCH v12 15/20] target/riscv: update `decode_save_opc` to store extra word2

Extra word 2 is stored during tcg compile and `decode_save_opc` needs additional argument in order to pass the value. This will be used during unwind to get extra information about instruction like how to massage exceptions. Updated all callsites as well. Resolves: https://gitlab.com/qemu-project/

[PATCH v12 17/20] target/riscv: compressed encodings for sspush and sspopchk

sspush/sspopchk have compressed encodings carved out of zcmops. compressed sspush is designated as c.mop.1 while compressed sspopchk is designated as c.mop.5. Note that c.sspush x1 exists while c.sspush x5 doesn't. Similarly c.sspopchk x5 exists while c.sspopchk x1 doesn't. Signed-off-by: Deepak

[PATCH v12 05/20] target/riscv: additional code information for sw check

sw check exception support was recently added. This patch further augments sw check exception by providing support for additional code which is provided in *tval. Adds `sw_check_code` field in cpuarchstate. Whenever sw check exception is raised *tval gets the value deposited in `sw_check_code`. Si

[PATCH v12 10/20] target/riscv: Add zicfiss extension

zicfiss [1] riscv cpu extension enables backward control flow integrity. This patch sets up space for zicfiss extension in cpuconfig. And imple- ments dependency on A, zicsr, zimop and zcmop extensions. [1] - https://github.com/riscv/riscv-cfi Signed-off-by: Deepak Gupta Co-developed-by: Jim Sh

[PATCH v12 20/20] target/riscv: Expose zicfiss extension as a cpu property

Signed-off-by: Deepak Gupta Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c5ebcefeb5..2592465e24 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1485,6 +1485,7 @@ const RISCVCPUM

[PATCH v12 00/20] riscv support for control flow integrity extensions

v12 for riscv zicfilp and zicfiss extensions support in qemu. zicfilp and zicfiss spec pdf https://github.com/riscv/riscv-cfi/releases/download/v1.0/riscv-cfi.pdf github sources to spec https://github.com/riscv/riscv-cfi Links for previous versions [1] - v1 https://lists.nongnu.org/archive/html/

[PATCH v12 14/20] target/riscv: AMO operations always raise store/AMO fault

This patch adds one more word for tcg compile which can be obtained during unwind time to determine fault type for original operation (example AMO). Depending on that, fault can be promoted to store/AMO fault. Signed-off-by: Deepak Gupta Suggested-by: Richard Henderson Reviewed-by: Richard Hende

[PATCH v12 11/20] target/riscv: introduce ssp and enabling controls for zicfiss

zicfiss introduces a new state ssp ("shadow stack register") in cpu. ssp is expressed as a new unprivileged csr (CSR_SSP=0x11) and holds virtual address for shadow stack as programmed by software. Shadow stack (for each mode) is enabled via bit3 in *envcfg CSRs. Shadow stack can be enabled for a m

[PATCH v12 09/20] target/riscv: Expose zicfilp extension as a cpu property

Signed-off-by: Deepak Gupta Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 55754cb374..c9aeffee4e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1481,6 +1481,7 @@ const RISCVCPUM

[PATCH v12 18/20] disas/riscv: enable disassembly for zicfiss instructions

Enable disassembly for sspush, sspopchk, ssrdp & ssamoswap. Disasembly is only enabled if zimop and zicfiss ext is set to true. Signed-off-by: Deepak Gupta Acked-by: Alistair Francis --- disas/riscv.c | 40 +++- disas/riscv.h | 1 + 2 files changed, 40 inser

[PATCH v12 13/20] target/riscv: mmu changes for zicfiss shadow stack protection

zicfiss protects shadow stack using new page table encodings PTE.W=1, PTE.R=0 and PTE.X=0. This encoding is reserved if zicfiss is not implemented or if shadow stack are not enabled. Loads on shadow stack memory are allowed while stores to shadow stack memory leads to access faults. Shadow stack ac

[PATCH v12 12/20] target/riscv: tb flag for shadow stack instructions

Shadow stack instructions can be decoded as zimop / zcmop or shadow stack instructions depending on whether shadow stack are enabled at current privilege. This requires a TB flag so that correct TB generation and correct TB lookup happens. `DisasContext` gets a field indicating whether bcfi is enab

[PATCH v12 01/20] target/riscv: expose *envcfg csr and priv to qemu-user as well

Execution environment config CSR controlling user env and current privilege state shouldn't be limited to qemu-system only. *envcfg CSRs control enabling of features in next lesser mode. In some cases bits *envcfg CSR can be lit up by kernel as part of kernel policy or software (user app) can choos

[PATCH v12 19/20] disas/riscv: enable disassembly for compressed sspush/sspopchk

sspush and sspopchk have equivalent compressed encoding taken from zcmop. cmop.1 is sspush x1 while cmop.5 is sspopchk x5. Due to unusual encoding for both rs1 and rs2 from space bitfield, this required a new codec. Signed-off-by: Deepak Gupta Acked-by: Alistair Francis --- disas/riscv.c | 19 +

[PATCH v12 02/20] target/riscv: Add zicfilp extension

zicfilp [1] riscv cpu extension enables forward control flow integrity. If enabled, all indirect calls must land on a landing pad instruction. This patch sets up space for zicfilp extension in cpuconfig. zicfilp is dependend on zicsr. [1] - https://github.com/riscv/riscv-cfi Signed-off-by: Deepa

[PATCH v12 06/20] target/riscv: tracking indirect branches (fcfi) for zicfilp

zicfilp protects forward control flow (if enabled) by enforcing all indirect call and jmp must land on a landing pad instruction `lpad`. If target of an indirect call or jmp is not `lpad` then cpu/hart must raise a sw check exception with tval = 2. This patch implements the mechanism using TCG. Ta

[PATCH v12 04/20] target/riscv: save and restore elp state on priv transitions

elp state is recorded in *status on trap entry (less privilege to higher privilege) and restored in elp from *status on trap exit (higher to less privilege). Additionally this patch introduces a forward cfi helper function to determine if current privilege has forward cfi is enabled or not based o

[PATCH v12 07/20] target/riscv: zicfilp `lpad` impl and branch tracking

Implements setting lp expected when `jalr` is encountered and implements `lpad` instruction of zicfilp. `lpad` instruction is taken out of auipc x0, . This is an existing HINTNOP space. If `lpad` is target of an indirect branch, cpu checks for 20 bit value in x7 upper with 20 bit value embedded in

[PATCH v12 03/20] target/riscv: Introduce elp state and enabling controls for zicfilp

zicfilp introduces a new state elp ("expected landing pad") in cpu. During normal execution, elp is idle (NO_LP_EXPECTED) i.e not expecting landing pad. On an indirect call, elp moves LP_EXPECTED. When elp is LP_EXPECTED, only a subsquent landing pad instruction can set state back to NO_LP_EXPECTED

Re: [PATCH v3 4/4] tests/tcg/aarch64: Extend MTE gdbstub tests to system mode

On 8/30/24 06:13, Gustavo Romero wrote:   1 .text 1e60  40001000  40001000  00011000  2**12   4 .data 00012000  4020  4020  0002  2**12 4040 g   .data    mte_page I was not able to make the MEMORY

Re: [PATCH] raw-format: Fix error message for invalid offset/size

On Thu, Aug 29, 2024 at 08:55:27PM +0200, Kevin Wolf wrote: > s->offset and s->size are only set at the end of the function and still > contain the old values when formatting the error message. Print the > parameters with the new values that we actually checked instead. > > Fixes: 500e2434207d ('r

Re: [PATCH 11/13] pnv/xive: Update PIPR when updating CPPR

On 8/29/2024 7:29 AM, Cédric Le Goater wrote: On 8/1/24 22:30, Michael Kowal wrote: From: Glenn Miles Current code was updating the PIPR inside the xive_tctx_accept() function instead of the xive_tctx_set_cppr function, which is where the HW would have it updated. Did you confirm with th

Re: [PATCH v2 2/2] vhost-user: add a request-reply lock

On Thu, Aug 29, 2024 at 11:05:15AM -0400, Michael S. Tsirkin wrote: > > Personally I still prefer we look into why a separate mutex won't work and > > why that timed out; that could be part of whoever is going to investigate > > the whole issue (including the hang later on). Otherwise I'm ok from >

Re: [PATCH 10/13] pnv/xive: Add special handling for pool targets

On 8/29/2024 7:14 AM, Cédric Le Goater wrote: On 8/1/24 22:30, Michael Kowal wrote: From: Glenn Miles Hypervisor "pool" targets do not get their own interrupt line and instead must share an interrupt line with the hypervisor "physical" targets. This also means that the pool ring must use so

Re: [PATCH v3 4/4] tests/tcg/aarch64: Extend MTE gdbstub tests to system mode

Hi Richard, On 8/28/24 9:43 PM, Richard Henderson wrote: On 8/28/24 04:01, Gustavo Romero wrote:   SECTIONS   { -    /* virt machine, RAM starts at 1gb */ +    /* Skip first 1 GiB on virt machine: RAM starts at 1 GiB. */   . = (1 << 30); Better is to use MEMORY {   RAM (rwx) : ORIGIN =

Re: [PATCH 09/13] ppc/xive2: Support "Pull Thread Context to Odd Thread Reporting Line"

On 8/29/2024 7:08 AM, Cédric Le Goater wrote: On 8/1/24 22:30, Michael Kowal wrote: From: Glenn Miles Adds support for single byte writes to offset 0xC38 of the TIMA address space.  When this offset is written to, the hardware disables the thread context and copies the current state informat

Re: [PATCH v2 12/17] migration/multifd: Device state transfer support - send side

On 29.08.2024 02:41, Fabiano Rosas wrote: "Maciej S. Szmigiero" writes: From: "Maciej S. Szmigiero" A new function multifd_queue_device_state() is provided for device to queue its state for transmission via a multifd channel. Signed-off-by: Maciej S. Szmigiero --- include/migration/misc.

Re: [PATCH v2 00/17] Multifd 🔀 device state transfer support with VFIO consumer

On 29.08.2024 02:51, Fabiano Rosas wrote: "Maciej S. Szmigiero" writes: On 28.08.2024 22:46, Fabiano Rosas wrote: "Maciej S. Szmigiero" writes: From: "Maciej S. Szmigiero" This is an updated v2 patch series of the v1 series located here: https://lore.kernel.org/qemu-devel/cover.171871758

Re: [PATCH v4 6/7] memory: Do not create circular reference with subregion

On Thu, Aug 29, 2024 at 01:39:36PM +0900, Akihiko Odaki wrote: > > > I am calling the fact that embedded memory regions are accessible in > > > instance_finalize() "live". A device can perform operations on its memory > > > regions during instance_finalize() and we should be aware of that. > > > >

Re: [PATCH for-9.2] kvm: Use 'unsigned long' for request argument in functions wrapping ioctl()

On Thu, Aug 15, 2024 at 01:27:47PM GMT, Peter Maydell wrote: > From: Johannes Stoelp > > Change the data type of the ioctl _request_ argument from 'int' to > 'unsigned long' for the various accel/kvm functions which are > essentially wrappers around the ioctl() syscall. > > The correct type for

Re: [PATCH] chardev: allow specifying finer-grained reconnect timeouts

On Thu, Aug 29, 2024 at 01:56:43PM GMT, Markus Armbruster wrote: > Daniil Tatianin writes: > > > The "reconnect" option only allows to specify the time in seconds, > > which is way too long for certain workflows. ... > > @@ -287,7 +292,8 @@ > > '*telnet': 'bool', > > '*

[PATCH] raw-format: Fix error message for invalid offset/size

s->offset and s->size are only set at the end of the function and still contain the old values when formatting the error message. Print the parameters with the new values that we actually checked instead. Fixes: 500e2434207d ('raw-format: Split raw_read_options()') Signed-off-by: Kevin Wolf ---

Re: [PULL 17/20] target/arm: Do memory type alignment check when translation disabled

On Wed, 28 Aug 2024 at 16:51, Peter Maydell wrote: > > On Wed, 28 Aug 2024 at 08:22, Michael Tokarev wrote: > > > > 05.03.2024 16:52, Peter Maydell wrote: > > > From: Richard Henderson > > > > > > If translation is disabled, the default memory type is Device, which > > > requires alignment check

Re: [RFC 2/2] vhost-vdpa: Implement GPA->IOVA & IOVA->SVQ HVA trees

On Wed, Aug 21, 2024 at 2:56 PM Jonah Palmer wrote: > > Implements a GPA->IOVA and IOVA->SVQ HVA tree for handling mapping, > unmapping, and translations for guest and host-only memory, > respectively. > > By splitting up a full IOVA->HVA tree (containing both guest and > host-only memory mappings

Re: [RFC 1/2] vhost-vdpa: Decouple the IOVA allocator

On Wed, Aug 21, 2024 at 2:56 PM Jonah Palmer wrote: > > Decouples the IOVA allocator from the IOVA->HVA tree and instead adds > the allocated IOVA range to an IOVA-only tree (iova_map). This IOVA tree > will hold all IOVA ranges that have been allocated (e.g. in the > IOVA->HVA tree) and are remov

[PATCH v2 0/1] plugins: add API to read guest CPU memory from hwaddr

This patch adds a single API function which allows reading from a guest CPU physical address. I don't know of a good way to add a self-contained test for this feature to tests/tcg/plugins, but I did come up with a small test case to demonstrate the functionality using peiyuanix/riscv-os: First, g

[PATCH v2 1/1] plugins: add API to read guest CPU memory from hwaddr

Signed-off-by: Rowan Hart --- include/qemu/qemu-plugin.h | 22 ++ plugins/api.c| 17 + plugins/qemu-plugins.symbols | 1 + 3 files changed, 40 insertions(+) diff --git a/include/qemu/qemu-plugin.h b/include/qemu/qemu-plugin.h index c71c705b6

[PATCH] sysbus-fdt: DT node generation for tegra234-mgbe assigned device

Implement the code generating the guest device tree node for a tegra234 Multi-Gigabit Ethernet (MGBE) controller assigned device (physical function). The tricky part is the reset properties. For the device to be probed on guest side, mac and pcs resets are requested. As opposed to the clocks we ca

Re: [PATCH v3 0/7] vfio/igd: add passthrough support for IGDs of gen 11 and later

On Wed, 28 Aug 2024 15:43:21 +0200 "Corvin Köhne" wrote: > Hi, > > Qemu has experimental support for GPU passthrough of Intels integrated graphic > devices. Unfortunately, Intel has changed some bits for their gen 11 devices > and later. To support these devices, we have to account for those cha

Re: [PATCH v5 4/5] target/riscv: Add Smrnmi mnret instruction.

On Mon, Aug 19, 2024 at 11:49 AM Alistair Francis wrote: > > On Fri, Aug 9, 2024 at 6:12 PM Tommy Wu wrote: > > > > This patch adds a new instruction `mnret`. `mnret` is an M-mode-only > > instruction that uses the values in `mnepc` and `mnstatus` to return to the > > program counter, privilege m

Re: [PATCH for-9.2 00/10] s390: Convert virtio-ccw, cpu to three-phase reset, and followup cleanup

On Wed, 28 Aug 2024 at 09:13, Nico Boehr wrote: > > Quoting Nico Boehr (2024-08-26 14:08:20) > > There was a little hickup without the fixup to patch 2, but after Nina > > pushed the fixup, we did not observe any failures related to your > > changes in our CI. Thanks! > > Peter, after a few CI run

Re: [PATCH v2 2/4] reset: Add RESET_TYPE_WAKEUP

On Thu, 29 Aug 2024 at 16:48, David Hildenbrand wrote: > > > I have rewritten the documentation section to make it more explicit > > that the reset might not happen. I would appreciate feedback if some > > part still needs some care or if it is clear now. > > > >If the machine supports waking

Re: [PATCH v2 2/4] reset: Add RESET_TYPE_WAKEUP

I have rewritten the documentation section to make it more explicit that the reset might not happen. I would appreciate feedback if some part still needs some care or if it is clear now. If the machine supports waking up from a suspended state and needs to reset its devices during wake-up (

Re: [PATCH RESEND] hw/openrisc/openrisc_sim: keep serial@90000000 as default

On Wed, Aug 28, 2024 at 04:38:49PM +0100, Peter Maydell wrote: > On Tue, 27 Aug 2024 at 19:53, Stafford Horne wrote: > > > > On Sun, Aug 25, 2024 at 03:09:20PM +0100, Peter Maydell wrote: > > > On Sun, 25 Aug 2024 at 12:35, Jason A. Donenfeld wrote: > > > > > > > > On Fri, Aug 23, 2024 at 07:28:4

Re: [PATCH v5 2/5] target/riscv: Handle Smrnmi interrupt and exception.

On Thu, Aug 15, 2024 at 9:40 AM Alvin Che-Chia Chang(張哲嘉) wrote: > > Hi Tommy, > > > -Original Message- > > From: qemu-riscv-bounces+alvinga=andestech@nongnu.org > > On Behalf Of > > Tommy Wu > > Sent: Friday, August 9, 2024 4:12 PM > > To: qemu-devel@nongnu.org; qemu-ri...@nongnu.org

Re: [PATCH for-9.2 00/10] s390: Convert virtio-ccw, cpu to three-phase reset, and followup cleanup

On Thu, 29 Aug 2024 at 15:44, Nico Boehr wrote: > > Quoting Peter Maydell (2024-08-29 15:35:30) > > On Thu, 29 Aug 2024 at 14:26, Nico Boehr wrote: > > > > > > Quoting Peter Maydell (2024-08-29 15:09:44) > > > > Thanks. I tried this repro, but mkosi falls over almost > > > > immediately: > > > >

Re: [PATCH v2 2/2] vhost-user: add a request-reply lock

On Thu, Aug 29, 2024 at 10:29:24AM -0400, Peter Xu wrote: > On Thu, Aug 29, 2024 at 02:45:45PM +0530, Prasad Pandit wrote: > > Hello Michael, > > > > On Thu, 29 Aug 2024 at 13:12, Michael S. Tsirkin wrote: > > > Weird. Seems to indicate some kind of deadlock? > > > > * Such a deadlock should oc

[PATCH v2 1/1] linux-user: add openat2 support in linux-user

This commit adds support for the `openat2()` syscall in the `linux-user` userspace emulator. It is implemented by extracting a new helper `maybe_do_fake_open()` out of the exiting `do_guest_openat()` and share that with the new `do_guest_openat2()`. Unfortunatly we cannot just make do_guest_openat

[PATCH v2 0/1] linux-user: add openat2 support in linux-user

Hi, This is v2 of the openat2 support in linux-user. Thanks for the excellent feedback from Richard Henderson. I reworked/updated the patch and (hopefully) addressed all comments/suggestions. Extracting the helper made it much clearer indeed. The patch still requires openat2.h from the host, But

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