Add read*/write*_fail qtest APIs to check for memory access failures.
Signed-off-by: Octavian Purdila
---
tests/qtest/libqtest-single.h | 92 +++
tests/qtest/libqtest.h| 76 +
system/qtest.c| 44 ++---
Add flexcomm usart polling and irq unit tests.
Signed-off-by: Octavian Purdila
---
tests/qtest/flexcomm-usart-test.c | 314 ++
tests/qtest/meson.build | 3 +-
2 files changed, 316 insertions(+), 1 deletion(-)
create mode 100644 tests/qtest/flexcomm-usart-
This patch set adds support for NXP's RT500 MCU [1] and the RT595
EVK[2]. More RT500 device models will be submitted in future patch sets.
The goal of this first patch set is to provide a minimal set that
allows running the NXP MCU SDK hello world example[4].
The patch set introduces a (python) t
From: Sebastian Ene
Add master and loopback tests for flexcomm spi.
Signed-off-by: Sebastian Ene
[tavip: add master mode test, convert to qtest]
Signed-off-by: Octavian Purdila
---
tests/qtest/flexcomm-spi-test.c | 144
tests/qtest/meson.build | 2 +-
Add support for NXP's flexcomm usart. It supports interupts and FIFO
access but no DMA.
The patch includes an automatically generated header which contains
the register layout and helpers.
The header can be regenerated with the svd-flexcomm-usart target when
the build is configured with --enable-
Add qtest APIs to check the device clock frequency.
Signed-off-by: tavip
---
include/hw/qdev-clock.h | 10 +++
tests/qtest/libqtest-single.h | 24 +
tests/qtest/libqtest.h| 22 +++
hw/core/qdev-clock.c | 2 +-
system/qtest.c
Add mcux-soc-svd subproject that contains SVD files that are going to
be used to generate C header with register layout definitions and
other helpers to create device models.
Guard the subproject by a configuration option since it is rarely
going to be used - whenever new headers will be generated
Add a simple i2c peripheral to be used for testing I2C device
models. The peripheral has a fixed number of registers that can be
read and written.
Signed-off-by: Octavian Purdila
---
include/hw/misc/i2c_tester.h | 30
hw/misc/i2c_tester.c | 94 +++
Add basic support for the RT500 SoC. It supports enough peripherals to
run the NXP's microXpresso SDK hello world example.
The patch includes an automatically generated header which contains
peripheral base addreses and interrupt numbers.
The header can be regenerated with the svd-rt500 target wh
Add support for NXP's flexcomm i2c. It does not support slave mode or
DMA.
The patch includes an automatically generated header which contains
the register layout and helpers.
The header can be regenerated with the svd-flexcomm-i2c target when
the build is configured with --enable-mcux-soc-svd.
Add flexcomm function selection unit tests.
Signed-off-by: Octavian Purdila
---
tests/qtest/flexcomm-test.c | 86 +
tests/qtest/meson.build | 1 +
2 files changed, 87 insertions(+)
create mode 100644 tests/qtest/flexcomm-test.c
diff --git a/tests/qtest/
The RT500 reset controller has two instances that have the same
register layout but with different fields for some registers.
The model only provides set and clear functionality for the various
reset lines which is common for both instances. Because of that only
one type is implemented for both co
Add utility macros for accessing register or register bit fields in
tests, e.g.:
REG32_WRITE(FLEXCOMM, PSELID, persel);
g_assert(REG32_READ_FIELD(FLEXCOMM, PSELID, PERSEL) == persel);
Signed-off-by: Octavian Purdila
---
tests/qtest/reg-utils.h | 70 +
This is mostly a stub which completes SPI transactions as noops
by masking out the error interrupts and never clearing the IPCMDDONE
interrupt.
Although incomplete, this allows software that uses NXP's mcuxpresso
SDK to run the SDK board initialization functions.
It also supports AHB memory acces
From: Stefan Stanacar
The CMSIS System View Description format(CMSIS-SVD) is an XML based
description of Arm Cortex-M microcontrollers provided and maintained
by sillicon vendors. It includes details such as peripherals registers
(down to bitfields), peripheral register block addresses, reset
val
Add test to exercise clocks set and clear, system PLL initialization,
audio PLL initialization, systick and ostimer clock source selection.
Signed-off-by: Octavian Purdila
---
tests/qtest/rt500-clkctl-test.c | 195
tests/qtest/meson.build | 1 +
2 files
Signed-off-by: tavip
---
hw/ssi/ssi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c
index 3f357e8f16..d1f3ce7c22 100644
--- a/hw/ssi/ssi.c
+++ b/hw/ssi/ssi.c
@@ -105,7 +105,9 @@ static void ssi_peripheral_realize(DeviceState *dev, Error
**errp
Add a simple FIFO unit test that test wrap around and push, pop and
peek for both fifo8 and fifo32.
Signed-off-by: Octavian Purdila
---
tests/unit/test-fifo.c | 97 ++
tests/unit/meson.build | 1 +
2 files changed, 98 insertions(+)
create mode 100644 tes
Add a simple SPI peripheral that echoes back received data. Useful for
testing SPI controllers.
Signed-off-by: Octavian Purdila
---
include/hw/misc/spi_tester.h | 32 ++
hw/misc/spi_tester.c | 52
hw/misc/Kconfig | 5
Add basic support for the RT595-EVK board, enough to be able to run
the NXP's microXpresso SDK hello world example.
Signed-off-by: Octavian Purdila
---
hw/arm/rt595-evk.c | 64 ++
hw/arm/Kconfig | 5
hw/arm/meson.build | 1 +
3 files changed
Add support for NXP's FLEXCOMM device model. It uses the NXP RT595 SVD
file to generate the register structure.
FLEXCOMM is a generic serial communication module which support
multiple functions: UART, SPI and I2C. These are configurable at runtime.
This patch adds the infrastructure to support a
Add master mode tests for flexcomm i2c.
Signed-off-by: Octavian Purdila
---
tests/qtest/flexcomm-i2c-test.c | 169
tests/qtest/meson.build | 2 +-
2 files changed, 170 insertions(+), 1 deletion(-)
create mode 100644 tests/qtest/flexcomm-i2c-test.c
dif
Add fifo32_peek() that returns the first element from the queue
without popping it.
Signed-off-by: Octavian Purdila
---
include/qemu/fifo32.h | 28
1 file changed, 28 insertions(+)
diff --git a/include/qemu/fifo32.h b/include/qemu/fifo32.h
index 4e9fd1b5ef..77aab488
From: Sebastian Ene
Add support for NXP's flexcomm spi. It supports FIFO access,
interrupts and master mode only. It does not support DMA.
The patch includes an automatically generated header which contains
the register layout and helpers.
The header can be regenerated with the svd-flexcomm-spi
Philippe Mathieu-Daudé writes:
> Hi Ani,
>
> On 9/8/24 08:49, Ani Sinha wrote:
>> error_report() is more appropriate for error situations. Replace fprintf with
>> error_report. Cosmetic. No functional change.
>> CC: qemu-triv...@nongnu.org
>> CC: zhao1@intel.com
>
> (Pointless to carry Cc lin
On Tue, Aug 27, 2024 at 1:31 AM Deepak Gupta wrote:
>
> zicfiss protects shadow stack using new page table encodings PTE.W=0,
> PTE.R=0 and PTE.X=0. This encoding is reserved if zicfiss is not
Shouldn't this be R=0, W=1, and X=0 ?
Alistair
> implemented or if shadow stack are not enabled.
> Loa
On Thu, Apr 18, 2024 at 9:40 PM Clément Léger wrote:
>
> The Smdbltrp extension allows to generate M-mode targeted double trap
> exceptions [1]. Such exceptions are generated if a trap is taken while
> mstatus.sdt is set to 1. The specification states that if the Smnrmi
> extension is implemented,
On Tue, Aug 27, 2024 at 1:33 AM Deepak Gupta wrote:
>
> Shadow stack instructions can be decoded as zimop / zcmop or shadow stack
> instructions depending on whether shadow stack are enabled at current
> privilege. This requires a TB flag so that correct TB generation and correct
> TB lookup happe
On Tue, Aug 27, 2024 at 2:29 PM Richard Henderson
wrote:
>
> On 8/27/24 14:03, Alistair Francis wrote:
> > On Tue, Aug 27, 2024 at 1:58 PM Richard Henderson
> > wrote:
> >>
> >> On 8/27/24 13:53, Alistair Francis wrote:
> >>> Exposing the *envcfg CSRs to userspace seems tricky as everything is
>
On Thu, Apr 18, 2024 at 9:40 PM Clément Léger wrote:
>
> The Ssdbltrp extension allows handling trap when being in non-reentrant
> state (mainly during exception handling) for S-mode [1]. This patch add
> support for this extension as an experimental extension.
>
> Link:
> https://github.com/risc
On 27/08/2024 00.10, Philippe Mathieu-Daudé wrote:
Use the 'linux_kernel' namespace to provide common helpers
to functional tests booting a Linux kernel.
Suggested-by: Thomas Huth
Signed-off-by: Philippe Mathieu-Daudé
---
tests/functional/qemu_test/linux_kernel.py | 19 +++
On 26/08/2024 22.59, Philippe Mathieu-Daudé wrote:
On 26/8/24 11:10, Thomas Huth wrote:
On 24/08/2024 18.08, Philippe Mathieu-Daudé wrote:
Straight forward conversion. Update the SHA1 hashes to
SHA256 hashes since SHA1 should not be used anymore nowadays.
Add extract_from_deb() method in qemu_
On 8/23/24 2:23 AM, Peter Maydell wrote:
In sbsa_fdt_add_gic_node() we g_strdup_printf() two nodename
strings, but only free one.
Since the string is actually entirely constant and we don't
make any use of printf's format-string operations, we can
drop the g_strdup_printf() use entirely.
Signed
On 8/27/24 14:03, Alistair Francis wrote:
On Tue, Aug 27, 2024 at 1:58 PM Richard Henderson
wrote:
On 8/27/24 13:53, Alistair Francis wrote:
Exposing the *envcfg CSRs to userspace seems tricky as everything is
currently built with the S/M CSRs removed from user builds.
It is as simple as mo
On Tue, Aug 27, 2024 at 1:32 AM Deepak Gupta wrote:
>
> zicfiss [1] riscv cpu extension enables backward control flow integrity.
>
> This patch sets up space for zicfiss extension in cpuconfig. And imple-
> ments dependency on A, zicsr, zimop and zcmop extensions.
>
> [1] - https://github.com/risc
On Tue, Aug 27, 2024 at 1:32 AM Deepak Gupta wrote:
>
> Signed-off-by: Deepak Gupta
> Co-developed-by: Jim Shu
> Co-developed-by: Andy Chiu
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> disas/riscv.c | 18 +-
> disas/riscv.h | 2 ++
> 2 f
On 2024/08/27 4:42, Peter Xu wrote:
On Mon, Aug 26, 2024 at 06:10:25PM +0100, Peter Maydell wrote:
On Mon, 26 Aug 2024 at 16:22, Peter Xu wrote:
On Fri, Aug 23, 2024 at 03:13:11PM +0900, Akihiko Odaki wrote:
memory_region_update_container_subregions() used to call
memory_region_ref(), which
On Tue, Aug 27, 2024 at 1:33 AM Deepak Gupta wrote:
>
> Implements setting lp expected when `jalr` is encountered and implements
> `lpad` instruction of zicfilp. `lpad` instruction is taken out of
> auipc x0, . This is an existing HINTNOP space. If `lpad` is
> target of an indirect branch, cpu che
On Tue, Aug 27, 2024 at 1:58 PM Richard Henderson
wrote:
>
> On 8/27/24 13:53, Alistair Francis wrote:
> > Exposing the *envcfg CSRs to userspace seems tricky as everything is
> > currently built with the S/M CSRs removed from user builds.
>
> It is as simple as moving them out of ifdefs, then ini
On Tue, Aug 27, 2024 at 1:31 AM Deepak Gupta wrote:
>
> zicfilp protects forward control flow (if enabled) by enforcing all
> indirect call and jmp must land on a landing pad instruction `lpad`. If
> target of an indirect call or jmp is not `lpad` then cpu/hart must raise
> a sw check exception wi
On 8/27/24 13:53, Alistair Francis wrote:
Exposing the *envcfg CSRs to userspace seems tricky as everything is
currently built with the S/M CSRs removed from user builds.
It is as simple as moving them out of ifdefs, then initializing them as needed in reset
for CONFIG_USER_ONLY. That's what
With edk2-stable202408 LoongArch UEFI bios, CSR PGD register is set only
if its value is equal to zero for boot cpu, it causes reboot issue. Since
CSR PGD register is changed with linux kernel, UEFI BIOS cannot use it.
Add workaround to clear CSR registers relative with TLB in function
loongarch_c
On Tue, Aug 27, 2024 at 1:32 AM Deepak Gupta wrote:
>
> sw check exception support was recently added. This patch further augments
> sw check exception by providing support for additional code which is
> provided in *tval. Adds `sw_check_code` field in cpuarchstate. Whenever
> sw check exception i
On Tue, Aug 27, 2024 at 11:36 AM Richard Henderson
wrote:
>
> On 8/27/24 10:52, Deepak Gupta wrote:
> > senvcfg and menvcfg belong to S and M state and don't actually mean anything
> > for qemu-user.
>
> Certainly they do, in that you obviously have arch_prctl calls that adjust
> them. The fact
Previously the emulated CAN ID register was being set to the exact same
value stored in qemu_can_frame.can_id. This doesn't work correctly
because the Xilinx IP core uses a different bit arrangement than
qemu_can_frame for all of its ID registers. Correct this problem for
both RX and TX, including
The interrupt level should be 0 or 1. The existing code was using the
interrupt flags to determine the level. In the only machine currently
supported (xlnx-versal-virt), the GICv3 was masking off all bits except
bit 0 when applying it, resulting in the IRQ never being delivered.
Signed-off-by: Dou
The endianness of the CAN data was backwards in each group of 4 bytes.
For example, the following data:
00 11 22 33 44 55 66 77
was showing up like this:
33 22 11 00 77 66 55 44
Fix both the TX and RX code to put the data in the correct order.
Signed-off-by: Doug Brown
Reviewed-by: Francisco
The read index should not be changed when storing a new message into the
RX or TX FIFO. Changing it at this point will cause the reader to get
out of sync. The wrapping of the read index is already handled by the
pre-write functions for the FIFO status registers anyway.
Additionally, the calculati
When checking the QEMU_CAN_FRMF_TYPE_FD flag, we need to ignore other
potentially set flags. Before this change, received CAN FD frames from
SocketCAN weren't being recognized as CAN FD.
Signed-off-by: Doug Brown
Reviewed-by: Pavel Pisa
Reviewed-by: Francisco Iglesias
---
hw/net/can/xlnx-versa
Add support for QEMU_CAN_FRMF_ESI and QEMU_CAN_FRMF_BRS flags, and
ensure frame->flags is always initialized to 0.
Note that the Xilinx IP core doesn't allow manually setting the ESI bit
during transmits, so it's only implemented for the receive case.
Signed-off-by: Doug Brown
---
hw/net/can/xl
Use QEMU's helper functions can_dlc2len() and can_len2dlc() for
translating between the raw DLC value and the SocketCAN length value.
This also has the side effect of correctly handling received CAN FD
frames with a DLC of 0-8, which was broken previously.
Signed-off-by: Doug Brown
---
hw/net/ca
This series fixes several problems I ran into while trying to simulate
the AMD/Xilinx Versal CANFD controller in the xlnx-versal-virt machine
using Xilinx's v6.6_LTS_2024.1 kernel. With all of these patches
applied, everything works correctly alongside actual CAN devices.
- IRQs were accidentally
On Tue, Aug 27, 2024 at 1:30 AM Deepak Gupta wrote:
>
> zicfilp introduces a new state elp ("expected landing pad") in cpu.
> During normal execution, elp is idle (NO_LP_EXPECTED) i.e not expecting
> landing pad. On an indirect call, elp moves LP_EXPECTED. When elp is
> LP_EXPECTED, only a subsque
On Tue, Aug 27, 2024 at 1:31 AM Deepak Gupta wrote:
>
> v9 for riscv zicfilp and zicfiss extensions support in qemu.
Can you please link to the exact specification and version you used?
We have had issues where there are multiple RVI spec versions ratified
and it's difficult to figure out which
On Fri, Aug 23, 2024 at 10:18 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 8/20/24 12:27 PM, Jason Chien wrote:
> > Hi Daniel,
> >
> > On 2024/8/1 下午 11:43, Daniel Henrique Barboza wrote:
> >> From: Tomasz Jeznach
> >>
> >> The RISC-V IOMMU spec predicts that the IOMMU can use translation caches
Signed-off-by: Rowan Hart
---
docs/about/emulation.rst| 14 -
tests/tcg/plugins/syscall.c | 117
2 files changed, 130 insertions(+), 1 deletion(-)
diff --git a/docs/about/emulation.rst b/docs/about/emulation.rst
index eea1261baa..e85d494ff0 100644
--
On Fri, Aug 23, 2024 at 5:42 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 8/20/24 12:16 PM, Jason Chien wrote:
> > Hi Daniel,
> >
> > On 2024/8/1 下午 11:43, Daniel Henrique Barboza wrote:
> >> From: Tomasz Jeznach
> >>
> >> The RISC-V IOMMU specification is now ratified as-per the RISC-V
> >> inte
Signed-off-by: Rowan Hart
---
include/qemu/qemu-plugin.h | 32 +++-
plugins/api.c| 20
plugins/qemu-plugins.symbols | 1 +
3 files changed, 52 insertions(+), 1 deletion(-)
diff --git a/include/qemu/qemu-plugin.h b/include/qemu/q
This patch adds one API function to the QEMU plugin API
bool qemu_plugin_read_memory_vaddr(vaddr, GByteArray *, size_t);
The API allows reading memory from an arbitrary guest virtual
address, which is useful for many things but the motivating examples
are:
* Virtual Machine Introspection (VMI)
*
On Tue, Aug 27, 2024 at 1:30 AM Deepak Gupta wrote:
>
> zicfilp [1] riscv cpu extension enables forward control flow integrity.
> If enabled, all indirect calls must land on a landing pad instruction.
>
> This patch sets up space for zicfilp extension in cpuconfig. zicfilp
> is dependend on zicsr.
> -Original Message-
> From: Brian Cain
> Sent: Monday, August 26, 2024 6:27 PM
> To: qemu-devel@nongnu.org
> Cc: bc...@quicinc.com; quic_mathb...@quicinc.com;
> sidn...@quicinc.com; quic_mlie...@quicinc.com;
> ltaylorsimp...@gmail.com
> Subject: [PATCH v2 2/2] target/hexagon: add enums
> -Original Message-
> From: Brian Cain
> Sent: Monday, August 26, 2024 6:27 PM
> To: qemu-devel@nongnu.org
> Cc: bc...@quicinc.com; quic_mathb...@quicinc.com;
> sidn...@quicinc.com; quic_mlie...@quicinc.com;
> ltaylorsimp...@gmail.com; Laurent Vivier
> Subject: [PATCH v2 1/2] target/h
Hi Alex：
Any update？
yaozhenguo 于2024年8月7日周三 17:55写道：
>
> When hotplug and hotunplug vhost-user-net device quickly.
> qemu will crash. BT is as below:
>
> 0 __pthread_kill_implementation () at /usr/lib64/libc.so.6
> 1 raise () at /usr/lib64/libc.so.6
> 2 abort () at /usr/lib64/libc.so.6
>
On 8/27/24 10:52, Deepak Gupta wrote:
senvcfg and menvcfg belong to S and M state and don't actually mean anything
for qemu-user.
Certainly they do, in that you obviously have arch_prctl calls that adjust them. The fact
that you've modeled those so far as separate variables is part of what is
Hi Cedric,
Cédric Le Goater 於 2024年8月26日 週一 下午7:49寫道：
>
> Hello Jamin,
>
> On 7/26/24 08:00, Jamin Lin wrote:
> > Hi Cedric,
>
> I will looked at v2. Sorry for the late reply, I was on PTO.
>
> Thanks,
>
> C.
>
Thanks for help
Due to my company internal policy, it will automatically add the
foll
On Tue, Aug 27, 2024 at 10:33:04AM +1000, Richard Henderson wrote:
On 8/27/24 01:29, Deepak Gupta wrote:
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8e1f05e5b1..083d405516 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1022,6 +1022,11 @@ static void riscv_cpu_reset_h
On 8/27/24 01:29, Deepak Gupta wrote:
sspush/sspopchk have compressed encodings carved out of zcmops.
compressed sspush is designated as c.mop.1 while compressed sspopchk
is designated as c.mop.5.
Note that c.sspush x1 exists while c.sspush x5 doesn't. Similarly
c.sspopchk x5 exists while c.sspo
On 8/27/24 01:29, Deepak Gupta wrote:
Extra word 2 is stored during tcg compile and `decode_save_opc` needs
additional argument in order to pass the value. This will be used during
unwind to get extra information about instruction like how to massage
exceptions. Updated all callsites as well.
Si
On 8/27/24 01:29, Deepak Gupta wrote:
This patch adds one more word for tcg compile which can be obtained during
unwind time to determine fault type for original operation (example AMO).
Depending on that, fault can be promoted to store/AMO fault.
Signed-off-by: Deepak Gupta
Suggested-by: Richar
On 8/27/24 01:29, Deepak Gupta wrote:
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8e1f05e5b1..083d405516 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1022,6 +1022,11 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType
type)
env->load_res = -1;
se
The values previously used for "HEX_EXCP_*" were the cause code
definitions and not the event numbers. So in this commit, we update
the names to reflect the cause codes. In HEX_EVENT_TRAP0's case, we add
a new "HEX_EVENT_*" with the correct event number.
Signed-off-by: Brian Cain
---
linux-user
Signed-off-by: Brian Cain
---
target/hexagon/cpu_bits.h | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h
index 2e60c0fafe..ff596e2a94 100644
--- a/target/hexagon/cpu_bits.h
+++ b/target/hexagon/cpu_bi
Changes in v2:
* Fixed the HEX_EVENT_{INVALID*,PRIV*,etc} - several of these were actually
cause codes, just like TRAP0.
* I combined "Rename HEX_EXCP_ => HEX_EVENT_" and "rename
HEX_EVENT_TRAP0=>HEX_CAUSE_TRAP0"
into a single commit.
Brian Cain (2):
target/hexagon: rename HEX_EXCP_*=>HEX_CAUS
On 8/24/24 14:56, Ajeet Singh wrote:
From: Mark Corbin
Implemented functions for setting up and initializing threads in the
RISC-V architecture.
The 'target_thread_set_upcall' function sets up the stack pointer,
program counter, and function argument for new threads.
The 'target_thread_init' fun
Straight forward conversion. Update the SHA1 hashes to SHA256
hashes since SHA1 should not be used anymore nowadays.
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 1 +
tests/avocado/boot_linux_console.py | 97 --
tests/functional/m
▶ 4/5 test_aarch64_raspi3.Aarch64Raspi3Machine.test_aarch64_raspi3_atf
OK
4/5 qemu:func-thorough+func-aarch64-thorough+thorough /
func-aarch64-aarch64_raspi3 OK 1.96s 1 subtests passed
▶ 5/5 test_aarch64_raspi4.Aarch64Raspi4Machine.test_arm_raspi4
OK
5
Use the 'linux_kernel' namespace to provide common helpers
to functional tests booting a Linux kernel.
Suggested-by: Thomas Huth
Signed-off-by: Philippe Mathieu-Daudé
---
tests/functional/qemu_test/linux_kernel.py | 19 +++
1 file changed, 19 insertions(+)
create mode 100644 te
Straight forward conversion. Update the SHA1 hashes to SHA256
hashes since SHA1 should not be used anymore nowadays.
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 1 +
tests/avocado/boot_linux_console.py | 23 --
tests/functional/meson.build
Straight forward conversion. Update the SHA1 hashes to SHA256
hashes since SHA1 should not be used anymore nowadays.
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 1 +
tests/avocado/boot_linux_console.py | 85 ---
tests/functional/meson.bu
On 8/24/24 14:56, Ajeet Singh wrote:
From: Mark Corbin
Added functions for cloning CPU registers and resetting the CPU state
for RISC-V architecture.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed-by: Richard Henderson
---
bsd-user/riscv/target_arch_cpu.h | 14
On 8/24/24 14:56, Ajeet Singh wrote:
From: Mark Corbin
Added the initial implementation for RISC-V CPU initialization and main
loop. This includes setting up the general-purpose registers and
program counter based on the provided target architecture definitions.
Signed-off-by: Mark Corbin
Signe
On 8/26/24 19:43, Thomas Huth wrote:
Hi Richard,
since it seems like we're going to have RC4, here are some minor
fixes that could still be included.
The following changes since commit f259e4cb8a8b4ef5463326fc214a7d8d7703d5de:
Merge tag 'pull-trivial-patches' ofhttps://gitlab.com/mjt0k/qe
Signed-off-by: Jason Fan
---
include/qemu/bitops.h | 26 ++
1 file changed, 26 insertions(+)
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index 2c0a2fe751..d01c4b42f2 100644
--- a/include/qemu/bitops.h
+++ b/include/qemu/bitops.h
@@ -459,6 +459,32 @@ static
Jason Fan (1):
include/qemu/bitops.h: Add deposit8 for uint8_t bit operation
include/qemu/bitops.h | 26 ++
1 file changed, 26 insertions(+)
--
2.46.0.295.g3b9ea8a38a-goog
On 26/8/24 11:10, Thomas Huth wrote:
On 24/08/2024 18.08, Philippe Mathieu-Daudé wrote:
Straight forward conversion. Update the SHA1 hashes to
SHA256 hashes since SHA1 should not be used anymore nowadays.
Add extract_from_deb() method in qemu_test.utils package.
Should we maybe rather copy th
On 26/8/24 22:12, Peter Xu wrote:
On Mon, Aug 26, 2024 at 04:53:22PM -0300, Fabiano Rosas wrote:
As observed by Philippe, the multifd_ram_unfill_packet() function
currently leaves the MultiFDPacket structure with mixed
endianness. This is harmless, but ultimately not very clean. Aside
from that,
Peter Xu writes:
> On Mon, Aug 26, 2024 at 04:53:22PM -0300, Fabiano Rosas wrote:
>> As observed by Philippe, the multifd_ram_unfill_packet() function
>> currently leaves the MultiFDPacket structure with mixed
>> endianness. This is harmless, but ultimately not very clean. Aside
>> from that, the
On Mon, Aug 26, 2024 at 04:53:22PM -0300, Fabiano Rosas wrote:
> As observed by Philippe, the multifd_ram_unfill_packet() function
> currently leaves the MultiFDPacket structure with mixed
> endianness. This is harmless, but ultimately not very clean. Aside
> from that, the packet is also written t
On Mon, Aug 26, 2024 at 04:53:21PM -0300, Fabiano Rosas wrote:
> The methods are defined at module_init time and don't ever
> change. Make them const.
>
> Suggested-by: Philippe Mathieu-Daudé
> Signed-off-by: Fabiano Rosas
Reviewed-by: Peter Xu
--
Peter Xu
In preparation for adding new payload types to multifd, move most of
the no-compression code into multifd-nocomp.c. Let's try to keep a
semblance of layering by not mixing general multifd control flow with
the details of transmitting pages of ram.
There are still some pieces leftover, namely the p
We want multifd to be able to handle more types of data than just ram
pages. To start decoupling multifd from pages, replace p->pages
(MultiFDPages_t) with the new type MultiFDSendData that hides the
client payload inside an union.
The general idea here is to isolate functions that *need* to handl
Skip saving and loading any ram data in the packet in the case of a
SYNC. This fixes a shortcoming of the current code which requires a
reset of the MultiFDPages_t fields right after the previous
pending_job finishes, otherwise the very next job might be a SYNC and
multifd_send_fill_packet() will p
All references to pages are being removed from the multifd worker
threads in order to allow multifd to deal with different payload
types.
multifd_send_zero_page_detect() is called by all multifd migration
paths that deal with pages and is the last spot where zero pages and
normal page amounts are
Separate the multifd sync from flushing the client data to the
channels. These two operations are closely related but not strictly
necessary to be executed together.
The multifd sync is intrinsic to how multifd works. The multiple
channels operate independently and may finish IO out of order in
re
Prior to moving the ram code into multifd-nocomp.c, change the code to
register the nocomp ops dynamically so we don't need to have the ops
structure defined in multifd.c.
While here, move the ops struct initialization to the end of the file
to make the next diff cleaner.
Reviewed-by: Prasad Pand
Add a new data structure to replace p->pages in the multifd
channel. This new structure will hide the multifd payload type behind
an union, so we don't need to add a new field to the channel each time
we want to handle a different data type.
This also allow us to keep multifd_send_pages() as is, w
As observed by Philippe, the multifd_ram_unfill_packet() function
currently leaves the MultiFDPacket structure with mixed
endianness. This is harmless, but ultimately not very clean. Aside
from that, the packet is also written to on the recv side to ensure
the ramblock name is null-terminated.
Sto
The methods are defined at module_init time and don't ever
change. Make them const.
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Fabiano Rosas
---
migration/multifd-nocomp.c | 2 +-
migration/multifd-qpl.c| 2 +-
migration/multifd-uadk.c | 2 +-
migration/multifd-zlib.c | 2 +-
m
This value never changes and is always the same as page_count. We
don't need a copy of it per-channel plus one in the extra slot. Remove
it.
Reviewed-by: Peter Xu
Signed-off-by: Fabiano Rosas
---
migration/multifd.c | 6 ++
migration/multifd.h | 2 --
2 files changed, 2 insertions(+), 6 del
The total_normal_pages and total_zero_pages elements are used only for
the end tracepoints of the multifd threads. These are not super useful
since they record per-channel numbers and are just the sum of all the
pages that are transmitted per-packet, for which we already have
tracepoints. Remove th
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