[PATCH v3 08/17] bsd-user: Implement RISC-V sysarch system call emulation

From: Mark Corbin Added the 'do_freebsd_arch_sysarch' function to emulate the 'sysarch' system call for the RISC-V architecture. Currently, this function returns '-TARGET_EOPNOTSUPP' to indicate that the operation is not supported. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed

[PATCH v3 14/17] bsd-user: Implement RISC-V signal trampoline setup functions

From: Mark Corbin Added functions for setting up the RISC-V signal trampoline and signal frame: 'set_sigtramp_args()': Configures the RISC-V CPU state with arguments for the signal handler. It sets up the registers with the signal number,pointers to the signal info and user context, the signal h

[PATCH v3 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection

From: Mark Corbin Introduced RISC-V specific ELF definitions and hardware capability detection. Additionally, a function to retrieve hardware capabilities ('get_elf_hwcap') is implemented, which returns the common bits set in each CPU's ISA strings. Signed-off-by: Mark Corbin Signed-off-by: Aje

[PATCH v3 15/17] bsd-user: Implement 'get_mcontext' for RISC-V

From: Mark Corbin Added the 'get_mcontext' function to extract and populate the RISC-V machine context from the CPU state. This function is used to gather the current state of the general-purpose registers and store it in a 'target_mcontext_' structure. Signed-off-by: Mark Corbin Signed-off-by:

[PATCH v3 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling

From: Mark Corbin Implemented the RISC-V CPU execution loop, including handling various exceptions and system calls. The loop continuously executes CPU instructions,processes exceptions, and handles system calls by invoking FreeBSD syscall handlers. Signed-off-by: Mark Corbin Signed-off-by: Aje

[PATCH v3 13/17] bsd-user: Define RISC-V signal handling structures and constants

From: Mark Corbin Added definitions for RISC-V signal handling, including structures and constants for managing signal frames and context Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_signal.h

[PATCH v3 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions

From: Mark Corbin Added functions for cloning CPU registers and resetting the CPU state for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_cpu.h | 14 ++ 1 file changed, 14 insertions(+) di

[PATCH v3 12/17] bsd-user: Add generic RISC-V64 target definitions

From: Warner Losh Added a generic definition for RISC-V64 target-specific details. Implemented the 'regpairs_aligned' function,which returns 'false' to indicate that register pairs are not aligned in the RISC-V64 ABI. Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh Reviewed-by: Richard H

[PATCH v3 06/17] bsd-user: Define RISC-V register structures and register copying

From: Mark Corbin Added definitions for RISC-V register structures, including general-purpose registers and floating-point registers, in 'target_arch_reg.h'. Implemented the 'target_copy_regs' function to copy register values from the CPU state to the target register structure, ensuring proper en

[PATCH v3 11/17] bsd-user: Define RISC-V system call structures and constants

From: Mark Corbin Introduced definitions for the RISC-V system call interface, including the 'target_pt_regs' structure that outlines the register storage layout during a system call. Added constants for hardware machine identifiers. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-aut

[PATCH v3 09/17] bsd-user: Add RISC-V thread setup and initialization support

From: Mark Corbin Implemented functions for setting up and initializing threads in the RISC-V architecture. The 'target_thread_set_upcall' function sets up the stack pointer, program counter, and function argument for new threads. The 'target_thread_init' function initializes thread registers bas

[PATCH v3 16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV

From: Mark Corbin Added implementations for 'set_mcontext' and 'get_ucontext_sigreturn' functions for RISC-V architecture, Both functions ensure that the CPU state and user context are properly managed. Signed-off-by: Mark Corbin Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh Co-author

[PATCH v3 00/17] bsd-user: Comprehensive RISCV Support

Key Changes Compared to Version 2: Patch 1: changed loop conditions to avoid setting r0 Patch 7: replaced manual byte swapping with const_le32 Patch 9: used ROUND_DOWN to align the stack Mark Corbin (15): bsd-user: Implement RISC-V CPU initialization and main loop bsd-user: Add RISC-V CPU exec

[PATCH v3 01/17] bsd-user: Implement RISC-V CPU initialization and main loop

From: Mark Corbin Added the initial implementation for RISC-V CPU initialization and main loop. This includes setting up the general-purpose registers and program counter based on the provided target architecture definitions. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by

[PATCH v3 17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files

From: Warner Losh Added configuration for RISC-V 64-bit target to the build system. Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- configs/targets/riscv64-bsd-user.mak | 4 1 file changed, 4 insertions(+) create mode 100644 configs/targets/risc

[PATCH v3 04/17] bsd-user: Implement RISC-V TLS register setup

From: Mark Corbin Included the prototype for the 'target_cpu_set_tls' function in the 'target_arch.h' header file. This function is responsible for setting the Thread Local Storage (TLS) register for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richar

[PATCH v3 07/17] bsd-user: Add RISC-V signal trampoline setup function

From: Mark Corbin Implemented the 'setup_sigtramp' function for setting up the signal trampoline code in the RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_sigtramp.h | 42 +++ 1

[PATCH v3 10/17] bsd-user: Define RISC-V VM parameters and helper functions

From: Mark Corbin Added definitions for RISC-V VM parameters, including maximum and default sizes for text, data, and stack, as well as address space limits. Implemented helper functions for retrieving and setting specific values in the CPU state, such as stack pointer and return values. Signed-

Re: [PATCH v2 0/2] *-user: Handle short reads in mmap_h_gt_g

On Tue, Aug 20, 2024 at 4:34 AM Philippe Mathieu-Daudé wrote: > On 20/8/24 07:08, Richard Henderson wrote: > > > Richard Henderson (2): > >linux-user: Handle short reads in mmap_h_gt_g > >bsd-user: Handle short reads in mmap_h_gt_g > > Series: > Reviewed-by: Philippe Mathieu-Daudé > Ser

Re: [PATCH 2/5] hw/net/can/xlnx-versal-canfd: Fix CAN FD flag check

Hello Pavel and Francisco, On 8/21/2024 6:11 PM, Pavel Pisa wrote: > Vikram Garhwal is listed even as whole CAN subsystem comaintainer > > > https://gitlab.com/qemu-project/qemu/-/blob/3472f54522a928f0020d6928d54c007f862c5478/MAINTAINERS#L2690 Unfortunately I am totally new to submitting patc

Re: [PATCH v8 13/13] acpi/ghes: check if the BIOS pointers for HEST are correct

Em Mon, 19 Aug 2024 16:07:33 +0200 Igor Mammedov escreveu: > > +err_source_struct = le64_to_cpu(ags->hest_addr_le) + > > +source * HEST_GHES_V2_TABLE_SIZE; > > there is no guaranties that HEST table will contain only GHESv2 sources, > and once such is added this pla

Re: [PATCH v8 03/13] acpi/ghes: Add support for GED error device

Em Mon, 19 Aug 2024 13:43:04 +0200 Igor Mammedov escreveu: > On Fri, 16 Aug 2024 09:37:35 +0200 > Mauro Carvalho Chehab wrote: > > > From: Jonathan Cameron > > > > As a GED error device is now defined, add another type > > of notification. > > > > Add error notification to GHES v2 using > >a

Re: [External] Re: [PATCH v8 4/5] migration: Introduce 'qatzip' compression method

On Thu, Aug 22, 2024 at 4:06 AM Prasad Pandit wrote: > > Hello, > > On Tue, 20 Aug 2024 at 22:40, Yichen Wang wrote: > > +static int qatzip_send_setup(MultiFDSendParams *p, Error **errp) > > +{ > > +QatzipData *q; > > +QzSessionParamsDeflate_T params; > > +const char *err_msg; > > +

Re: [PATCH] target/riscv: fix za64rs enabling

On 8/23/24 3:34 AM, Vladimir Isaev wrote: za64rs requires priv 1.12 when enabled by priv 1.11. This fixes annoying warning: warning: disabling za64rs extension for hart 0x because privilege spec version does not match on priv 1.11 CPUs. Fixes: 68c9e54beae8 ("target/riscv: do not en

Re: [PATCH] target: riscv: Enable Bit Manip for OpenTitan Ibex CPU

On 8/22/24 9:32 PM, Alistair Francis wrote: The OpenTitan Ibex CPU now supports the the Zba, Zbb, Zbc and Zbs bit-manipulation sub-extensions ratified in v.1.0.0 of the RISC-V Bit- Manipulation ISA Extension, so let's enable them in QEMU as well. 1: https://github.com/lowRISC/opentitan/pull/9

Re: [PATCH for-9.2 02/10] target/s390: Convert CPU to Resettable interface

On Fri, 23 Aug 2024 at 18:45, Nina Schoetterl-Glausch wrote: > > On Tue, 2024-08-13 at 17:52 +0100, Peter Maydell wrote: > > Convert the s390 CPU to the Resettable interface. This is slightly > > more involved than the other CPU types were (see commits > > 9130cade5fc22..d66e64dd006df) because S

[PATCH v8 00/17] riscv support for control flow integrity extensions

v8 for riscv zicfilp and zicfiss extensions support in qemu. Links for previous versions [1] - v1 https://lists.nongnu.org/archive/html/qemu-devel/2024-07/msg06017.html [2] - v2 https://lore.kernel.org/all/ed23bcbc-fdc4-4492-803c-daa958803...@linaro.org/T/ [3] - v3 https://lists.nongnu.org/archiv

[PATCH v8 12/17] target/riscv: AMO operations always raise store/AMO fault

This patch adds one more word for tcg compile which can be obtained during unwind time to determine fault type for original operation (example AMO). Depending on that, fault can be promoted to store/AMO fault. Signed-off-by: Deepak Gupta Suggested-by: Richard Henderson --- target/riscv/cpu.h

[PATCH v8 02/17] target/riscv: Introduce elp state and enabling controls for zicfilp

zicfilp introduces a new state elp ("expected landing pad") in cpu. During normal execution, elp is idle (NO_LP_EXPECTED) i.e not expecting landing pad. On an indirect call, elp moves LP_EXPECTED. When elp is LP_EXPECTED, only a subsquent landing pad instruction can set state back to NO_LP_EXPECTED

[PATCH v8 17/17] disas/riscv: enable disassembly for compressed sspush/sspopchk

sspush and sspopchk have equivalent compressed encoding taken from zcmop. cmop.1 is sspush x1 while cmop.5 is sspopchk x5. Due to unusual encoding for both rs1 and rs2 from space bitfield, this required a new codec. Signed-off-by: Deepak Gupta --- disas/riscv.c | 19 ++- disas/ri

[PATCH v8 06/17] target/riscv: zicfilp `lpad` impl and branch tracking

Implements setting lp expected when `jalr` is encountered and implements `lpad` instruction of zicfilp. `lpad` instruction is taken out of auipc x0, . This is an existing HINTNOP space. If `lpad` is target of an indirect branch, cpu checks for 20 bit value in x7 upper with 20 bit value embedded in

[PATCH v8 11/17] target/riscv: mmu changes for zicfiss shadow stack protection

zicfiss protects shadow stack using new page table encodings PTE.W=0, PTE.R=0 and PTE.X=0. This encoding is reserved if zicfiss is not implemented or if shadow stack are not enabled. Loads on shadow stack memory are allowed while stores to shadow stack memory leads to access faults. Shadow stack ac

[PATCH v8 05/17] target/riscv: tracking indirect branches (fcfi) for zicfilp

zicfilp protects forward control flow (if enabled) by enforcing all indirect call and jmp must land on a landing pad instruction `lpad`. If target of an indirect call or jmp is not `lpad` then cpu/hart must raise a sw check exception with tval = 2. This patch implements the mechanism using TCG. Ta

[PATCH v8 09/17] target/riscv: introduce ssp and enabling controls for zicfiss

zicfiss introduces a new state ssp ("shadow stack register") in cpu. ssp is expressed as a new unprivileged csr (CSR_SSP=0x11) and holds virtual address for shadow stack as programmed by software. Shadow stack (for each mode) is enabled via bit3 in *envcfg CSRs. Shadow stack can be enabled for a m

[PATCH v8 07/17] disas/riscv: enable `lpad` disassembly

Signed-off-by: Deepak Gupta Co-developed-by: Jim Shu Co-developed-by: Andy Chiu Reviewed-by: Richard Henderson --- disas/riscv.c | 18 +- disas/riscv.h | 2 ++ 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c b/disas/riscv.c index c8364c2b07..c7c92a

[PATCH v8 04/17] target/riscv: additional code information for sw check

sw check exception support was recently added. This patch further augments sw check exception by providing support for additional code which is provided in *tval. Adds `sw_check_code` field in cpuarchstate. Whenever sw check exception is raised *tval gets the value deposited in `sw_check_code`. Si

[PATCH v8 16/17] disas/riscv: enable disassembly for zicfiss instructions

Enable disassembly for sspush, sspopchk, ssrdp & ssamoswap. Disasembly is only enabled if zimop and zicfiss ext is set to true. Signed-off-by: Deepak Gupta --- disas/riscv.c | 40 +++- disas/riscv.h | 1 + 2 files changed, 40 insertions(+), 1 deletion(-) dif

[PATCH v8 10/17] target/riscv: tb flag for shadow stack instructions

Shadow stack instructions can be decoded as zimop / zcmop or shadow stack instructions depending on whether shadow stack are enabled at current privilege. This requires a TB flag so that correct TB generation and correct TB lookup happens. `DisasContext` gets a field indicating whether bcfi is enab

[PATCH v8 14/17] target/riscv: implement zicfiss instructions

zicfiss has following instructions - sspopchk: pops a value from shadow stack and compares with x1/x5. If they dont match, reports a sw check exception with tval = 3. - sspush: pushes value in x1/x5 on shadow stack - ssrdp: reads current shadow stack - ssamoswap: swaps contents of shadow sta

[PATCH v8 15/17] target/riscv: compressed encodings for sspush and sspopchk

sspush/sspopchk have compressed encodings carved out of zcmops. compressed sspush is designated as c.mop.1 while compressed sspopchk is designated as c.mop.5. Note that c.sspush x1 exists while c.sspush x5 doesn't. Similarly c.sspopchk x5 exists while c.sspopchk x1 doesn't. Signed-off-by: Deepak

[PATCH v8 13/17] target/riscv: update `decode_save_opc` to store extra word2

Extra word 2 is stored during tcg compile and `decode_save_opc` needs additional argument in order to pass the value. This will be used during unwind to get extra information about instruction like how to massage exceptions. Updated all callsites as well. Signed-off-by: Deepak Gupta --- target/r

[PATCH v8 08/17] target/riscv: Add zicfiss extension

zicfiss [1] riscv cpu extension enables backward control flow integrity. This patch sets up space for zicfiss extension in cpuconfig. And imple- ments dependency on A, zicsr, zimop and zcmop extensions. [1] - https://github.com/riscv/riscv-cfi Signed-off-by: Deepak Gupta Co-developed-by: Jim Sh

[PATCH v8 01/17] target/riscv: Add zicfilp extension

zicfilp [1] riscv cpu extension enables forward control flow integrity. If enabled, all indirect calls must land on a landing pad instruction. This patch sets up space for zicfilp extension in cpuconfig. zicfilp is dependend on zicsr. [1] - https://github.com/riscv/riscv-cfi Signed-off-by: Deepa

[PATCH v8 03/17] target/riscv: save and restore elp state on priv transitions

elp state is recorded in *status on trap entry (less privilege to higher privilege) and restored in elp from *status on trap exit (higher to less privilege). Additionally this patch introduces a forward cfi helper function to determine if current privilege has forward cfi is enabled or not based o

Re: [PATCH 5/5] hw/net/can/xlnx-versal-canfd: Handle RX of short FD frames

On Fri, Aug 16, 2024 at 09:35:05AM -0700, Doug Brown wrote: > There was no case for handling received CAN FD frames with a DLC of 0-8. > This was already handled properly with TX. Add similar code for RX. > > Signed-off-by: Doug Brown Reviewed-by: Francisco Iglesias > --- > hw/net/can/xlnx-v

Re: [PATCH 4/5] hw/net/can/xlnx-versal-canfd: Fix byte ordering

On Fri, Aug 16, 2024 at 09:35:04AM -0700, Doug Brown wrote: > The endianness of the CAN data was backwards in each group of 4 bytes. > For example, the following data: > > 00 11 22 33 44 55 66 77 > > was showing up like this: > > 33 22 11 00 77 66 55 44 > > Fix both the TX and RX code to put th

Re: [PATCH for-9.2 02/10] target/s390: Convert CPU to Resettable interface

On Tue, 2024-08-13 at 17:52 +0100, Peter Maydell wrote: > Convert the s390 CPU to the Resettable interface. This is slightly > more involved than the other CPU types were (see commits > 9130cade5fc22..d66e64dd006df) because S390 has its own set of > different kinds of reset with different behaviou

[PATCH v4 14/16] migration/multifd: Standardize on multifd ops names

Add the multifd_ prefix to all functions and remove the useless docstrings. Signed-off-by: Fabiano Rosas --- migration/multifd-qpl.c | 57 migration/multifd-uadk.c | 55 --- migration/multifd-zlib.c | 81 ++

[PATCH v4 00/16] migration/multifd: Remove multifd_send_state->pages

Hi, Not much changed sinced v3, the most notable is that I kept the nocomp names and created multifd-nocomp.c. I think "plain" is even more misterious, so let's keep what we are already used to. CI run: https://gitlab.com/farosas/qemu/-/pipelines/1425141484 v3: https://lore.kernel.org/r/20240801

[PATCH v4 15/16] migration/multifd: Register nocomp ops dynamically

Prior to moving the ram code into multifd-nocomp.c, change the code to register the nocomp ops dynamically so we don't need to have the ops structure defined in multifd.c. While here, move the ops struct initialization to the end of the file to make the next diff cleaner. Signed-off-by: Fabiano R

[PATCH v4 06/16] migration/multifd: Make MultiFDPages_t:offset a flexible array member

We're about to use MultiFDPages_t from inside the MultiFDSendData payload union, which means we cannot have pointers to allocated data inside the pages structure, otherwise we'd lose the reference to that memory once another payload type touches the union. Move the offset array into the end of the

[PATCH v4 10/16] migration/multifd: Isolate ram pages packet data

While we cannot yet disentangle the multifd packet from page data, we can make the code a bit cleaner by setting the page-related fields in a separate function. Signed-off-by: Fabiano Rosas --- migration/multifd.c| 99 +- migration/trace-events | 5 ++

[PATCH v4 05/16] migration/multifd: Introduce MultiFDSendData

Add a new data structure to replace p->pages in the multifd channel. This new structure will hide the multifd payload type behind an union, so we don't need to add a new field to the channel each time we want to handle a different data type. This also allow us to keep multifd_send_pages() as is, w

[PATCH v4 13/16] migration/multifd: Allow multifd sync without flush

Separate the multifd sync from flushing the client data to the channels. These two operations are closely related but not strictly necessary to be executed together. The multifd sync is intrinsic to how multifd works. The multiple channels operate independently and may finish IO out of order in re

[PATCH v4 03/16] migration/multifd: Remove pages->allocated

This value never changes and is always the same as page_count. We don't need a copy of it per-channel plus one in the extra slot. Remove it. Reviewed-by: Peter Xu Signed-off-by: Fabiano Rosas --- migration/multifd.c | 6 ++ migration/multifd.h | 2 -- 2 files changed, 2 insertions(+), 6 del

[PATCH v4 16/16] migration/multifd: Move nocomp code into multifd-nocomp.c

In preparation for adding new payload types to multifd, move most of the no-compression code into multifd-nocomp.c. Let's try to keep a semblance of layering by not mixing general multifd control flow with the details of transmitting pages of ram. There are still some pieces leftover, namely the p

[PATCH v4 04/16] migration/multifd: Pass in MultiFDPages_t to file_write_ramblock_iov

We want to stop dereferencing 'pages' so it can be replaced by an opaque pointer in the next patches. Reviewed-by: Peter Xu Signed-off-by: Fabiano Rosas --- migration/file.c| 3 ++- migration/file.h| 2 +- migration/multifd.c | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) dif

[PATCH v4 01/16] migration/multifd: Reduce access to p->pages

I'm about to replace the p->pages pointer with an opaque pointer, so do a cleanup now to reduce direct accesses to p->page, which makes the next diffs cleaner. Reviewed-by: Peter Xu Signed-off-by: Fabiano Rosas --- migration/multifd-qpl.c | 8 +--- migration/multifd-uadk.c | 9 +

[PATCH v4 09/16] migration/multifd: Remove total pages tracing

The total_normal_pages and total_zero_pages elements are used only for the end tracepoints of the multifd threads. These are not super useful since they record per-channel numbers and are just the sum of all the pages that are transmitted per-packet, for which we already have tracepoints. Remove th

[PATCH v4 07/16] migration/multifd: Replace p->pages with an union pointer

We want multifd to be able to handle more types of data than just ram pages. To start decoupling multifd from pages, replace p->pages (MultiFDPages_t) with the new type MultiFDSendData that hides the client payload inside an union. The general idea here is to isolate functions that *need* to handl

[PATCH v4 08/16] migration/multifd: Move pages accounting into multifd_send_zero_page_detect()

All references to pages are being removed from the multifd worker threads in order to allow multifd to deal with different payload types. multifd_send_zero_page_detect() is called by all multifd migration paths that deal with pages and is the last spot where zero pages and normal page amounts are

[PATCH v4 12/16] migration/multifd: Replace multifd_send_state->pages with client data

Multifd currently has a simple scheduling mechanism that distributes work to the various channels by keeping storage space within each channel and an extra space that is given to the client. Each time the client fills the space with data and calls into multifd, that space is given to the next idle

[PATCH v4 11/16] migration/multifd: Don't send ram data during SYNC

Skip saving and loading any ram data in the packet in the case of a SYNC. This fixes a shortcoming of the current code which requires a reset of the MultiFDPages_t fields right after the previous pending_job finishes, otherwise the very next job might be a SYNC and multifd_send_fill_packet() will p

[PATCH v4 02/16] migration/multifd: Inline page_size and page_count

The MultiFD*Params structures are for per-channel data. Constant values should not be there because that needlessly wastes cycles and storage. The page_size and page_count fall into this category so move them inline in multifd.h. Reviewed-by: Peter Xu Signed-off-by: Fabiano Rosas --- migration/

Re: [PATCH for-9.2 01/10] hw/s390/virtio-ccw: Convert to three-phase reset

On Tue, 2024-08-13 at 17:52 +0100, Peter Maydell wrote: > Convert the virtio-ccw code to three-phase reset. This allows us to > remove a call to device_class_set_parent_reset(), replacing it with > the three-phase equivalent resettable_class_set_parent_phases(). > Removing all the device_class_set

Re: [PATCH for-9.2 v6 08/12] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)

On 8/20/24 12:27 PM, Jason Chien wrote: Hi Daniel, On 2024/8/1 下午 11:43, Daniel Henrique Barboza wrote: From: Tomasz Jeznach The RISC-V IOMMU spec predicts that the IOMMU can use translation caches to hold entries from the DDT. This includes implementation for all cache commands that are m

Re: [PATCH] crypto: run qcrypto_pbkdf2_count_iters in a new thread

Hi folks, Sorry for the ping, but any thoughts on this? I mainly implemented what was discussed in the upstream bug[0]. Let me know what you think or any suggestions for this. Thank you, Tiago [0] https://gitlab.com/qemu-project/qemu/-/issues/2398 On Tue, Aug 13, 2024 at 10:19 AM Tiago Pasqual

Re: [PATCH 3/5] hw/net/can/xlnx-versal-canfd: Translate CAN ID registers

On Fri, Aug 16, 2024 at 09:35:03AM -0700, Doug Brown wrote: > Previously the emulated CAN ID register was being set to the exact same > value stored in qemu_can_frame.can_id. This doesn't work correctly > because the Xilinx IP core uses a different bit arrangement than > qemu_can_frame for all of i

Re: [PATCH for-9.2 6/6] hm/nvram/xlnx-versal-efuse-ctrl: Call register_finalize_block

On Thu, Aug 22, 2024 at 05:21:27PM +0100, Peter Maydell wrote: > The TYPE_XLNX_VERSAL_EFUSE_CTRL device creates a register block with > register_init_block32() in its instance_init method; we must > therefore destroy it in our instance_finalize method to avoid a leak > in the QOM introspection "ini

Re: [PATCH for-9.2 5/6] hw/misc/xlnx-versal-trng: Call register_finalize_block

On Thu, Aug 22, 2024 at 05:21:26PM +0100, Peter Maydell wrote: > The TYPE_XLNX_VERSAL_TRNG device creates a register block with > register_init_block32() in its instance_init method; we must > therefore destroy it in our instance_finalize method to avoid a leak > in the QOM introspection "init-insp

Re: [PATCH for-9.2 3/6] hw/nvram/xlnx-bbram: Call register_finalize_block

On Thu, Aug 22, 2024 at 05:21:24PM +0100, Peter Maydell wrote: > The TYPE_XLNX_BBRAM device creates a register block with > register_init_block32() in its instance_init method; we must > therefore destroy it in our instance_finalize method to avoid a leak > in the QOM introspection "init-inspect-fi

Re: [PATCH for-9.2 4/6] hw/nvram/xlnx-zynqmp-efuse: Call register_finalize_block

On Thu, Aug 22, 2024 at 05:21:25PM +0100, Peter Maydell wrote: > The TYPE_XLNX_ZYNQMP_EFUSE device creates a register block with > register_init_block32() in its instance_init method; we must > therefore destroy it in our instance_finalize method to avoid a leak > in the QOM introspection "init-ins

Re: [PATCH v3] tests/functional: Convert Aarch64 SBSA-Ref avocado tests

On 23.08.2024 15:16, Philippe Mathieu-Daudé wrote: Straight forward conversion. Since SBSA_FLASH files are not tarballs, use lzma_uncompress() method. Avocado used to set a timeout of 11 tests * 180s = 1980s. Hopefully 600s should be sufficient. Running on macOS Sonoma / Apple silicon M1: $

Re: Issue with QEMU Live Migration

"Arisetty, Chakri" writes: > Hello, > > Here is more data if my earlier mail did not provide enough details. I > apologize for not providing the critical data points in my previous mail. > > - Created a file (dd if=/dev/urandom of=/orig.img bs=1M count=1000) before > starting live migration > -

Re: [PATCH RESEND v4 0/3] Upgrade ACPI SPCR table to support SPCR table revision 4 format

Hi Jee Heng, On Fri, Aug 23, 2024 at 04:31:39AM -0700, Sia Jee Heng wrote: > Update the SPCR table to accommodate the SPCR Table revision 4 [1]. > The SPCR table has been modified to adhere to the revision 4 format [2]. > > Meanwhile, the virt SPCR golden reference file for RISC-V have been update

[PULL 2/3] system/vl.c: Print machine name, not "(null)", for unknown machine types

From: Peter Maydell In commit 412d294ffdc we tried to improve the error message printed when the machine type is unknown, but we used the wrong variable, resulting in: $ ./build/x86/qemu-system-aarch64 -M bang qemu-system-aarch64: unsupported machine type: "(null)" Use -machine help to list supp

[PULL 1/3] hw/x86: add a couple of comments explaining how the kernel image is parsed

From: Ani Sinha Cosmetic: add comments in x86_load_linux() pointing to the kernel documentation so that users can better understand the code. CC: qemu-triv...@nongnu.org Signed-off-by: Ani Sinha Reviewed-by: Zhao Liu Reviewed-by: Michael Tokarev Signed-off-by: Michael Tokarev --- hw/i386/x8

[PULL for-9.1 0/3] Trivial patches for 2024-08-23

The following changes since commit 407f9a4b121eb65166375c410e14d7b704bc1106: Update version for v9.1.0-rc3 release (2024-08-22 15:07:32 +1000) are available in the Git repository at: https://gitlab.com/mjt0k/qemu.git tags/pull-trivial-patches for you to fetch changes up to d6192f3f7593536a4

[PULL 3/3] hw/display/vhost-user-gpu.c: fix vhost_user_gpu_chr_read()

From: Haoran Zhang fix vhost_user_gpu_chr_read() where `size` was incorrectly passed to `msg->flags`. Fixes: 267f664658 ("hw/display: add vhost-user-vga & gpu-pci") Signed-off-by: Haoran Zhang Reviewed-by: Marc-André Lureau Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Michael Tokarev Si

Re: Issue with QEMU Live Migration

Hello, Here is more data if my earlier mail did not provide enough details. I apologize for not providing the critical data points in my previous mail. - Created a file (dd if=/dev/urandom of=/orig.img bs=1M count=1000) before starting live migration - Started migration with block-job-cancel co

Re: Issue with QEMU Live Migration

Hi, Thank you once again! > It's still not entirely clear to me what the situation is here. When the > migration reaches pre-switchover state the VM is stopped, so there would > be no more IO happening. Is this a matter of a race condition (of sorts) > because pre-switchover happens while the blo

Re: [PATCH RESEND v4 3/3] tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V

On Fri, Aug 23, 2024 at 04:31:42AM -0700, Sia Jee Heng wrote: > Update the virt SPCR golden reference file for RISC-V to accommodate the > SPCR Table revision 4 [1], utilizing the iasl binary compiled from the > latest ACPICA repository. The SPCR table has been modified to > adhere to the revision

Creating a vhost-user-vsock backend

I've been studying the example given in `contrib/vhost-user-blk`, and trying to match the code to what is in the standard (https://docs.oasis-open.org/virtio/virtio/v1.3/csd01/virtio-v1.3-csd01.html#x1-3050002), so I can use the code to create my own vhost-user-vsock server. I think I almost u

RE: [PATCH RFC V3 17/29] arm/virt: Release objects for *disabled* possible vCPUs after init

Hi Gavin, > From: Gavin Shan > Sent: Friday, August 23, 2024 11:52 AM > To: Salil Mehta ; qemu-devel@nongnu.org; > qemu-...@nongnu.org; m...@redhat.com > > Hi Sail, > > On 8/22/24 8:58 PM, Salil Mehta wrote: > >> On 8/21/24 8:23 PM, Salil Mehta wrote: > >> >> > >> >> On 8/21/

Re: [PATCH v3] tests/functional: Convert Aarch64 SBSA-Ref avocado tests

On 23/8/24 15:16, Philippe Mathieu-Daudé wrote: Straight forward conversion. Since SBSA_FLASH files are not tarballs, use lzma_uncompress() method. Avocado used to set a timeout of 11 tests * 180s = 1980s. Hopefully 600s should be sufficient. Running on macOS Sonoma / Apple silicon M1: $ QE

[PATCH v3] tests/functional: Convert Aarch64 SBSA-Ref avocado tests

Straight forward conversion. Since SBSA_FLASH files are not tarballs, use lzma_uncompress() method. Avocado used to set a timeout of 11 tests * 180s = 1980s. Hopefully 600s should be sufficient. Running on macOS Sonoma / Apple silicon M1: $ QEMU_TEST_TIMEOUT_EXPECTED=1 make check-functional-aa

Re: [PATCH RESEND v4 2/3] hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format

On Fri, Aug 23, 2024 at 04:31:41AM -0700, Sia Jee Heng wrote: > Update the SPCR table to accommodate the SPCR Table revision 4 [1]. > The SPCR table has been modified to adhere to the revision 4 format [2]. > > [1]: > https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port

Re: [PATCH v2] tests/functional: Convert Aarch64 SBSA-Ref avocado tests

On 22/8/24 16:06, Marcin Juszkiewicz wrote: On 22.08.2024 13:41, Philippe Mathieu-Daudé wrote:   # Timeouts for individual tests that can be slow e.g. with debugging enabled   test_timeouts = { +  'aarch64_sbsaref' : 180, What kind of machine is able to run those tests in 180s? I bumped them

Re: [PATCH RESEND v4 1/3] qtest: allow SPCR acpi table changes

On Fri, Aug 23, 2024 at 04:31:40AM -0700, Sia Jee Heng wrote: > Signed-off-by: Sia Jee Heng > --- > tests/qtest/bios-tables-test-allowed-diff.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/tests/qtest/bios-tables-test-allowed-diff.h > b/tests/qtest/bios-tables-test-allowed-diff.h >

[PATCH 2/2] hw/acpi: add cache hierarchy node to pptt table

Specify which layer (core/cluster/socket) caches found at in the CPU topology. Example: Here, 2 sockets (packages), and 2 clusters, 4 cores and 2 threads created, in aggregate 2*2*4*2 logical cores. In the smp-cache object, cores will have l1d and l1i (threads will share these caches by default.

[PATCH 1/2] target/arm/tcg: increase cache level for cpu=max

This patch addresses cache description in the `aarch64_max_tcg_initfn` function. It introduces three layers of caches and modifies the cache description registers accordingly. Additionally, a new function is added to handle cache description when CCIDX is disabled. The CCIDX remains disabled for cp

[RFC PATCH 0/2] Specifying cache topology on ARM

Specifying the cache layout in virtual machines is useful for applications and operating systems to fetch accurate information about the cache structure and make appropriate adjustments. Enforcing correct sharing information can lead to better optimizations. This patch enables the specification of

Re: [PATCH v4 11/35] tests/functional: Prepare the meson build system for the functional tests

On 21/8/24 10:27, Thomas Huth wrote: Provide a meson.build file for the upcoming python-based functional tests, and add some wrapper glue targets to the tests/Makefile.include file. We are going to use two "speed" modes for the functional tests: The "quick" tests can be run at any time (i.e. also

Re: [PATCH for-9.2 v6 03/12] hw/riscv: add RISC-V IOMMU base emulation

On 8/20/24 12:16 PM, Jason Chien wrote: Hi Daniel, On 2024/8/1 下午 11:43, Daniel Henrique Barboza wrote: From: Tomasz Jeznach The RISC-V IOMMU specification is now ratified as-per the RISC-V international process. The latest frozen specifcation can be found at: https://github.com/riscv-non

Re: [PATCH v4 1/7] migration: Free removed SaveStateEntry

Akihiko Odaki writes: > This fixes LeakSanitizer warnings. > > Signed-off-by: Akihiko Odaki > Reviewed-by: Peter Xu > Reviewed-by: Michael S. Tsirkin > --- > migration/savevm.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/migration/savevm.c b/migration/savevm.c > index deb57833f

[PATCH RESEND v4 3/3] tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V

Update the virt SPCR golden reference file for RISC-V to accommodate the SPCR Table revision 4 [1], utilizing the iasl binary compiled from the latest ACPICA repository. The SPCR table has been modified to adhere to the revision 4 format [2]. [1]: https://learn.microsoft.com/en-us/windows-hardwar

[PATCH RESEND v4 0/3] Upgrade ACPI SPCR table to support SPCR table revision 4 format

Update the SPCR table to accommodate the SPCR Table revision 4 [1]. The SPCR table has been modified to adhere to the revision 4 format [2]. Meanwhile, the virt SPCR golden reference file for RISC-V have been updated to accommodate the SPCR Table revision 4. [1]: https://learn.microsoft.com/en-u

[PATCH RESEND v4 2/3] hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format

Update the SPCR table to accommodate the SPCR Table revision 4 [1]. The SPCR table has been modified to adhere to the revision 4 format [2]. [1]: https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port-console-redirection-table [2]: https://github.com/acpica/acpica/pull/93

[PATCH RESEND v4 1/3] qtest: allow SPCR acpi table changes

Signed-off-by: Sia Jee Heng --- tests/qtest/bios-tables-test-allowed-diff.h | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8b..aae973048a 100644 --- a/tests/qtest/bios-tables-test-allowed

[PATCH v4 0/3] Upgrade ACPI SPCR table to support SPCR table revision 4 format

Update the SPCR table to accommodate the SPCR Table revision 4 [1]. The SPCR table has been modified to adhere to the revision 4 format [2]. Meanwhile, the virt SPCR golden reference file for RISC-V have been updated to accommodate the SPCR Table revision 4. [1]: https://learn.microsoft.com/en-u

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