On Thu, Aug 15, 2024 at 1:37 AM Pierrick Bouvier
wrote:
> Contrib plugins have been built out of tree so far, thanks to a Makefile.
> However, it is quite inconvenient for maintenance, as we may break them,
> especially for specific architectures.
>
> First patches are fixing warnings for existing
On 8/14/24 22:48, Pierrick Bouvier wrote:
On 8/14/24 20:04, Akihiko Odaki wrote:
SimPoint is a widely used tool to find the ideal microarchitecture
simulation points so Valgrind[2] and Pin[3] support generating basic
block vectors for use with them. Let's add a corresponding plugin to
QEMU too.
>-Original Message-
>From: Liu, Yi L
>Subject: Re: [PATCH v2 04/17] intel_iommu: Flush stage-2 cache in PASID-
>selective PASID-based iotlb invalidation
>
>On 2024/8/5 14:27, Zhenzhong Duan wrote:
>> Per spec 6.5.2.4, PADID-selective PASID-based iotlb invalidation will
>> flush stage-2 i
On 8/14/24 20:04, Akihiko Odaki wrote:
SimPoint is a widely used tool to find the ideal microarchitecture
simulation points so Valgrind[2] and Pin[3] support generating basic
block vectors for use with them. Let's add a corresponding plugin to
QEMU too.
Note that this plugin has a different goal
>-Original Message-
>From: Liu, Yi L
>Subject: Re: [PATCH v2 16/17] intel_iommu: Introduce a property to control
>FS1GP cap bit setting
>
>On 2024/8/5 14:27, Zhenzhong Duan wrote:
>> When host IOMMU doesn't support FS1GP but vIOMMU does, host
>IOMMU
>> can't translate stage-1 page table
>-Original Message-
>From: Liu, Yi L
>Subject: Re: [PATCH v2 14/17] intel_iommu: Set default aw_bits to 48 in
>scalable modren mode
>
>On 2024/8/5 14:27, Zhenzhong Duan wrote:
>> According to VTD spec, stage-1 page table could support 4-level and
>> 5-level paging.
>>
>> However, 5-level
SimPoint is a widely used tool to find the ideal microarchitecture
simulation points so Valgrind[2] and Pin[3] support generating basic
block vectors for use with them. Let's add a corresponding plugin to
QEMU too.
Note that this plugin has a different goal with tests/plugin/bb.c.
This plugin cre
This series fixes: https://gitlab.com/qemu-project/qemu/-/issues/2114
This converts the RISC-C charecter device callers of qemu_chr_fe_write()
to either use qemu_chr_fe_write_all() or to call qemu_chr_fe_write() async
and act on the return value.
Alistair Francis (2):
hw/char: riscv_htif: Use b
The current approach of using qemu_chr_fe_write() and ignoring the
return values results in dropped charecters [1].
Let's update the SiFive UART to use a async sifive_uart_xmit() function
to transmit the charecters and apply back preassure to the guest with
the SIFIVE_UART_TXFIFO_FULL status.
Thi
The current approach of using qemu_chr_fe_write() and ignoring the
return values results in dropped charecters [1]. Ideally we want to
report FIFO status to the guest, but the HTIF isn't a real UART, so we
don't really have a way to do that.
Instead let's just use qemu_chr_fe_write_all() so at lea
Hi Tommy,
> -Original Message-
> From: qemu-riscv-bounces+alvinga=andestech@nongnu.org
> On Behalf Of
> Tommy Wu
> Sent: Friday, August 9, 2024 4:12 PM
> To: qemu-devel@nongnu.org; qemu-ri...@nongnu.org
> Cc: frank.ch...@sifive.com; pal...@dabbelt.com; alistair.fran...@wdc.com;
> alis
Bah, s/PATCH/PULL/
r~
On 8/15/24 11:05, Richard Henderson wrote:
The following changes since commit c4d062885529a84928ddd260dab419b7d8dd4f90:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
(2024-08-15 07:41:16 +1000)
are available in the Git repository at:
ht
The following changes since commit c4d062885529a84928ddd260dab419b7d8dd4f90:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
(2024-08-15 07:41:16 +1000)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-lu-20240815
for you to fet
Do not pass guest_base to the host mmap instead of zero hint.
Cc: qemu-sta...@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2353
Signed-off-by: Richard Henderson
---
linux-user/mmap.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/lin
On 8/15/24 02:44, Paolo Bonzini wrote:
The following changes since commit 3ef11c991e501768f2fa646e8438f075be1cd2f5:
po: update Italian translation (2024-08-13 19:01:42 +0200)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstream
for you to fetch c
On Wed, 2024-08-14 at 20:15 +0200, Bernhard Beschow wrote:
> hw/char/serial currently contains the implementation of both TYPE_SERIAL and
> TYPE_SERIAL_MM. According to serial_class_init(), TYPE_SERIAL is an internal
> class while TYPE_SERIAL_MM is used by numerous machine types directly. Let's
> m
On Wed, 14 Aug 2024, Edgar E. Iglesias wrote:
> On Tue, Aug 13, 2024 at 03:52:32PM -0700, Stefano Stabellini wrote:
> > On Tue, 13 Aug 2024, Edgar E. Iglesias wrote:
> > > On Mon, Aug 12, 2024 at 06:47:17PM -0700, Stefano Stabellini wrote:
> > > > On Mon, 12 Aug 2024, Edgar E. Iglesias wrote:
> > >
On Wed, 14 Aug 2024, Edgar E. Iglesias wrote:
> On Mon, Aug 12, 2024 at 06:48:37PM -0700, Stefano Stabellini wrote:
> > On Mon, 12 Aug 2024, Edgar E. Iglesias wrote:
> > > From: "Edgar E. Iglesias"
> > >
> > > Add support for optionally creating a PCIe/GPEX controller.
> > >
> > > Signed-off-by:
From: Yuan Liu
add Intel QATzip compression method introduction
Signed-off-by: Yuan Liu
Reviewed-by: Nanhai Zou
Reviewed-by: Peter Xu
Reviewed-by: Yichen Wang
---
docs/devel/migration/features.rst | 1 +
docs/devel/migration/qatzip-compression.rst | 165
2 f
From: Bryan Zhang
Adds support for migration parameters to control QATzip compression
level and to enable/disable software fallback when QAT hardware is
unavailable. This is a preparatory commit for a subsequent commit that
will actually use QATzip compression.
Signed-off-by: Bryan Zhang
Signed
From: Bryan Zhang
Adds support for 'qatzip' as an option for the multifd compression
method parameter, and implements using QAT for 'qatzip' compression and
decompression.
Signed-off-by: Bryan Zhang
Signed-off-by: Hao Xiang
Signed-off-by: Yichen Wang
Acked-by: Markus Armbruster
---
hw/core/
From: Bryan Zhang
Add a 'qatzip' feature, which is automatically disabled, and which
depends on the QATzip library if enabled.
Signed-off-by: Bryan Zhang
Signed-off-by: Hao Xiang
Signed-off-by: Yichen Wang
---
meson.build | 10 ++
meson_options.txt | 2
From: Bryan Zhang
Adds an integration test for 'qatzip'.
Signed-off-by: Bryan Zhang
Signed-off-by: Hao Xiang
Signed-off-by: Yichen Wang
Reviewed-by: Fabiano Rosas
---
tests/qtest/migration-test.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/tests/qtest/mi
v7:
- Rebase changes on top of 0173b97a219c63062972744682eba46c560fb7f3
- Added QAT memory requirement introduction in documentations;
- Change the configuration options detection to auto in meson;
- Enhance the auto-fallback mechanism to align with QPL behavior;
v6:
- Rebase changes on top of 4ea
On Wed, 14 Aug 2024, Edgar E. Iglesias wrote:
> On Mon, Aug 12, 2024 at 06:48:52PM -0700, Stefano Stabellini wrote:
> > On Mon, 12 Aug 2024, Edgar E. Iglesias wrote:
> > > From: "Edgar E. Iglesias"
> > >
> > > This adds a Xen PVH x86 machine based on the PVH Common
> > > module used by the ARM PV
Tried to unify this meson.build with tests/tcg/plugins/meson.build but
the resulting modules are not output in the right directory.
Originally proposed by Anton Kochkov, thank you!
Solves: https://gitlab.com/qemu-project/qemu/-/issues/1710
Signed-off-by: Pierrick Bouvier
---
meson.build
Found on debian stable (i386).
../contrib/plugins/hwprofile.c: In function 'new_location':
../contrib/plugins/hwprofile.c:172:32: error: cast to pointer from integer of
different size [-Werror=int-to-pointer-cast]
172 | g_hash_table_insert(table, (gpointer) off_or_pc, loc);
|
Found on debian stable (i386).
../contrib/plugins/hotblocks.c: In function 'vcpu_tb_trans':
../contrib/plugins/hotblocks.c:117:56: error: cast to pointer from integer of
different size [-Werror=int-to-pointer-cast]
117 | cnt = (ExecCount *) g_hash_table_lookup(hotblocks, (gconstpointer)
ha
Found on debian stable (i386).
../contrib/plugins/cache.c: In function 'vcpu_tb_trans':
../contrib/plugins/cache.c:477:30: error: cast from pointer to integer of
different size [-Werror=pointer-to-int-cast]
477 | effective_addr = (uint64_t) qemu_plugin_insn_haddr(insn);
|
Sig
Found on debian stable.
../contrib/plugins/execlog.c: In function ‘vcpu_tb_trans’:
../contrib/plugins/execlog.c:236:22: error: declaration of ‘n’ shadows a
previous local [-Werror=shadow=local]
236 | for (int n = 0; n < all_reg_names->len; n++) {
| ^
../co
Contrib plugins have been built out of tree so far, thanks to a Makefile.
However, it is quite inconvenient for maintenance, as we may break them,
especially for specific architectures.
First patches are fixing warnings for existing plugins, then we add meson
support, and finally, we remove Makefi
Now replaced by meson build.
Signed-off-by: Pierrick Bouvier
---
configure| 18 -
Makefile | 10 -
contrib/plugins/Makefile | 85
3 files changed, 113 deletions(-)
delete mode 100644 contrib/plugins/Makefile
d
On Wed, 2024-08-14 at 15:41 -0700, Pierrick Bouvier wrote:
> Found on debian stable.
>
> ../target/s390x/tcg/translate.c: In function ‘get_mem_index’:
> ../target/s390x/tcg/translate.c:398:1: error: control reaches end of
> non-void function [-Werror=return-type]
> 398 | }
>
> Signed-off-by: Pi
On 8/15/24 08:41, Pierrick Bouvier wrote:
Found on debian stable.
../target/i386/kvm/kvm.c: In function ‘kvm_handle_rdmsr’:
../target/i386/kvm/kvm.c:5345:1: error: control reaches end of non-void
function [-Werror=return-type]
5345 | }
| ^
../target/i386/kvm/kvm.c: In function ‘kvm_han
Sent v2 (forgot to signoff commits).
On 8/14/24 10:11, Pierrick Bouvier wrote:
While working on a concurrency bug, I gave a try to tsan builds for QEMU. I
noticed it didn't build out of the box with recent gcc, so I fixed compilation.
In more, updated documentation to explain how to build a sani
Found on debian stable.
../target/i386/kvm/kvm.c: In function ‘kvm_handle_rdmsr’:
../target/i386/kvm/kvm.c:5345:1: error: control reaches end of non-void
function [-Werror=return-type]
5345 | }
| ^
../target/i386/kvm/kvm.c: In function ‘kvm_handle_wrmsr’:
../target/i386/kvm/kvm.c:5364:1: e
Found on debian stable.
../target/s390x/tcg/translate.c: In function ‘get_mem_index’:
../target/s390x/tcg/translate.c:398:1: error: control reaches end of non-void
function [-Werror=return-type]
398 | }
Signed-off-by: Pierrick Bouvier
---
target/s390x/tcg/translate.c | 1 -
1 file changed, 1
When building with gcc-12 -fsanitize=thread, gcc reports some
constructions not supported with tsan.
Found on debian stable.
qemu/include/qemu/atomic.h:36:52: error: ‘atomic_thread_fence’ is not supported
with ‘-fsanitize=thread’ [-Werror=tsan]
36 | #define smp_mb() ({ barr
Mention it's now possible to build with gcc, instead of clang, and
explain how to build a sanitized glib version.
Signed-off-by: Pierrick Bouvier
---
docs/devel/testing.rst | 26 ++
1 file changed, 22 insertions(+), 4 deletions(-)
diff --git a/docs/devel/testing.rst b/do
While working on a concurrency bug, I gave a try to tsan builds for QEMU. I
noticed it didn't build out of the box with recent gcc, so I fixed compilation.
In more, updated documentation to explain how to build a sanitized glib to avoid
false positives related to glib synchronisation primitives.
v
On 8/14/24 23:39, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/mips64/target_elf.h | 6 ++
1 file changed, 6 insertions(+)
Reviewed-by: Richard Henderson
And yes, this might as well go in with the others for 9.1.
r~
On 8/14/24 23:39, Philippe Mathieu-Daudé wrote:
Cc: YunQiang Su
Reported-by: Jiaxun Yang
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/mips64/target_elf.h | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 8/14/24 23:39, Philippe Mathieu-Daudé wrote:
The Octeon68XX CPU is available since commit 9a6046a655
("target/mips: introduce Cavium Octeon CPU model").
Cc: Pavel Dovgalyuk
Resolves:https://gitlab.com/qemu-project/qemu/-/issues/1722
Reported-by: Johnathan Hữu Trí
Suggested-by: Richard Henders
On 8/14/24 23:39, Philippe Mathieu-Daudé wrote:
R5900 emulation was removed in commit 823f2897bd.
Remove it from ELF parsing in order to avoid:
$ qemu-mipsn32 ./test5900
qemu-mipsn32: unable to find CPU model 'R5900'
This reverts commit 4d9e5a0eb7df6e98ac6cf5e16029f35dd05b9537.
Fixes: 82
On 8/14/24 23:12, Patrick Leis wrote:
I would go with your aio_wait_bh_oneshot suggestion. Please consider
adding it to QEMU as I pointed above. I can send a patch.
Hey - this is an important race condition to resolve, can we get some
attention back on this patchset please. It's pressi
On Wed, 14 Aug 2024, Bernhard Beschow wrote:
The serial port's frequency is set via the "baudbase" property nowadays.
Please keep it as some devices might have registers that set this freq and
this function will be needed for emulating that even if it's not emulated
currently.
Regards,
BALA
On Thu, Jun 27, 2024 at 10:55 AM Roman Kiryanov wrote:
> Paolo, thank you for your comments.
>
> On Thu, Jun 27, 2024 at 10:16 AM Paolo Bonzini
> wrote:
> > I think the easiest options would be:
> >
> > 1) if possible, allocate the timer and the callbackState statically in
> > the device.
>
> I
On Wed, 14 Aug 2024 at 15:22, Christian Borntraeger
wrote:
>
> Am 13.08.24 um 18:52 schrieb Peter Maydell:
> > The main aim of this patchseries is to remove the two remaining uses
> > of device_class_set_parent_reset() in the tree, which are virtio-ccw
> > and the s390 CPU class. Doing that lets u
On 8/12/2024 2:57 PM, Fabiano Rosas wrote:
Steve Sistare writes:
CPR preserves memory in place, so there is no need to track dirty memory.
By skipping it, CPR can support devices that do not support tracking.
Signed-off-by: Steve Sistare
---
system/memory.c | 11 +++
1 file change
From 9265233081fae546c0459792598a9f1688ddb020 Mon Sep 17 00:00:00 2001
From: Carl Hauser
Date: Sat, 10 Aug 2024 15:09:39 -0700
Subject: [PATCH v2] target/sparc: emulate floating point queue when
raising fp
traps
Sparc 32-bit machines perform floating point operations in an
asynchronous co-p
On Mon, Aug 12, 2024 at 04:43:23PM GMT, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Avoid a maybe-uninitialized warning in raw_refresh_zoned_limits()
> by initializing zoned.
>
> With GCC 14.1.0:
> In function ‘raw_refresh_zoned_limits’,
> inlined from ‘raw_refresh_limits’ at ..
Signed-off-by: Bernhard Beschow
---
hw/char/riscv_htif.c | 1 -
hw/ppc/prep.c| 1 -
hw/riscv/sifive_e.c | 1 -
hw/riscv/sifive_u.c | 1 -
4 files changed, 4 deletions(-)
diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
index 9bef60def1..54fd55c3e6 100644
--- a/hw/char/riscv_hti
The includes where updated based on compile errors. Now, the inclusion of the
header roughly matches Kconfig dependencies:
# grep -r -e "select SERIAL_ISA"
hw/ppc/Kconfig:select SERIAL_ISA
hw/isa/Kconfig:select SERIAL_ISA
hw/sparc64/Kconfig:select SERIAL_ISA
hw/i386/Kconfig:
The serial port's frequency is set via the "baudbase" property nowadays.
Signed-off-by: Bernhard Beschow
---
include/hw/char/serial.h | 2 --
hw/char/serial.c | 7 ---
2 files changed, 9 deletions(-)
diff --git a/include/hw/char/serial.h b/include/hw/char/serial.h
index 6e14099ee7..
hw/char/serial currently contains the implementation of both TYPE_SERIAL and
TYPE_SERIAL_MM. According to serial_class_init(), TYPE_SERIAL is an internal
class while TYPE_SERIAL_MM is used by numerous machine types directly. Let's
move the latter into its own module which makes the dependencies mor
The machine calls serial_hds_isa_init() which is provided by serial-isa.c,
guarded by SERIAL_ISA.
Signed-off-by: Bernhard Beschow
---
hw/ppc/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index c235519881..5addad1124 100644
--- a/hw/ppc/Kconfig
+++ b/
This series extracts TYPE_SERIAL_MM into its own module and introduces a
dedicated header for TYPE_SERIAL_ISA. The result is that no board directly
depends on CONFIG_SERIAL or includes hw/char/serial.h any more.
Bernhard Beschow (5):
hw: Remove unused inclusion of hw/char/serial.h
hw/char/seri
"Michael S. Tsirkin" writes:
> On Wed, Aug 14, 2024 at 04:05:34PM +1000, Nicholas Piggin wrote:
>> On Wed Aug 14, 2024 at 6:48 AM AEST, Michael S. Tsirkin wrote:
>> > On Tue, Aug 13, 2024 at 09:23:24PM +0100, Alex Bennée wrote:
>> > > From: Nicholas Piggin
>> > >
>> > > The regular qemu_bh_sche
Em Wed, 14 Aug 2024 14:53:22 +0100
Jonathan Cameron escreveu:
> On Wed, 14 Aug 2024 01:23:26 +0200
> Mauro Carvalho Chehab wrote:
>
> > Creates a QMP command to be used for generic ACPI APEI hardware error
> > injection (HEST) via GHESv2.
> >
> > The actual GHES code will be added at the follo
Mention it's now possible to build with gcc, instead of clang, and
explain how to build a sanitized glib version.
---
docs/devel/testing.rst | 26 ++
1 file changed, 22 insertions(+), 4 deletions(-)
diff --git a/docs/devel/testing.rst b/docs/devel/testing.rst
index af73d3d
Found on debian stable.
../target/s390x/tcg/translate.c: In function ‘get_mem_index’:
../target/s390x/tcg/translate.c:398:1: error: control reaches end of non-void
function [-Werror=return-type]
398 | }
---
target/s390x/tcg/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/
Found on debian stable.
../target/i386/kvm/kvm.c: In function ‘kvm_handle_rdmsr’:
../target/i386/kvm/kvm.c:5345:1: error: control reaches end of non-void
function [-Werror=return-type]
5345 | }
| ^
../target/i386/kvm/kvm.c: In function ‘kvm_handle_wrmsr’:
../target/i386/kvm/kvm.c:5364:1: e
When building with gcc-12 -fsanitize=thread, gcc reports some
constructions not supported with tsan.
Found on debian stable.
qemu/include/qemu/atomic.h:36:52: error: ‘atomic_thread_fence’ is not supported
with ‘-fsanitize=thread’ [-Werror=tsan]
36 | #define smp_mb() ({ barr
While working on a concurrency bug, I gave a try to tsan builds for QEMU. I
noticed it didn't build out of the box with recent gcc, so I fixed compilation.
In more, updated documentation to explain how to build a sanitized glib to avoid
false positives related to glib synchronisation primitives.
P
The following changes since commit 3ef11c991e501768f2fa646e8438f075be1cd2f5:
po: update Italian translation (2024-08-13 19:01:42 +0200)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstream
for you to fetch changes up to a6e65975c3fac1b2f067fef8eeed92
From: Anthony Harivel
Snapshot of the stat utime and stime for each thread, taken before and
after the pause, must be stored in separate locations
Signed-off-by: Anthony Harivel
Link: https://lore.kernel.org/r/20240807124320.1741124-2-ahari...@redhat.com
Signed-off-by: Paolo Bonzini
---
targe
Apologies. Please ignore this patchset.
Something seems to have gone wrong during the preparation and merge to current;
I am working on a replacement, and will send v2 once I am happy with it.
Ian Brockbank C.Eng.
Senior Staff Software Engineer
Cirrus Logic | cirrus.com | t: +44 131 272 7145 | m
On Mon, Aug 12, 2024 at 06:48:52PM -0700, Stefano Stabellini wrote:
> On Mon, 12 Aug 2024, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias"
> >
> > This adds a Xen PVH x86 machine based on the PVH Common
> > module used by the ARM PVH machine.
> >
> > Signed-off-by: Edgar E. Iglesias
> >
On Mon, Aug 12, 2024 at 06:48:37PM -0700, Stefano Stabellini wrote:
> On Mon, 12 Aug 2024, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias"
> >
> > Add support for optionally creating a PCIe/GPEX controller.
> >
> > Signed-off-by: Edgar E. Iglesias
> > ---
> > hw/xen/xen-pvh-common.c
On 8/13/24 23:32, Akihiko Odaki wrote:
On 2024/08/14 14:41, Pierrick Bouvier wrote:
On 8/13/24 21:56, Akihiko Odaki wrote:
On 2024/08/14 4:20, Pierrick Bouvier wrote:
Hi Akihiko, and thanks for contributing this new plugin.
Hi,
Thanks for reviewing
Recently, plugins documentation has bee
Am 13.08.24 um 18:52 schrieb Peter Maydell:
The main aim of this patchseries is to remove the two remaining uses
of device_class_set_parent_reset() in the tree, which are virtio-ccw
and the s390 CPU class. Doing that lets us do some followup cleanup.
(The diffstat looks alarming but is almost all
When physical address range in the input payload of scan media command
exceeds static_mem_size but does not exceed the sum of static and dynamic
memory, the scan media mailbox command unexpectedly returns an invalid input.
It is handled differently depending on whether dynamic memory is present
or
On Wed, 14 Aug 2024 01:23:26 +0200
Mauro Carvalho Chehab wrote:
> Creates a QMP command to be used for generic ACPI APEI hardware error
> injection (HEST) via GHESv2.
>
> The actual GHES code will be added at the followup patch.
>
> Signed-off-by: Mauro Carvalho Chehab
> Signed-off-by: Shiju J
On Wed, 14 Aug 2024 01:23:25 +0200
Mauro Carvalho Chehab wrote:
> From: Jonathan Cameron
>
> As a GED error device is now defined, add another type
> of notification.
>
> Add error notification to GHES v2 using a GED error device GED
> triggered via interrupt.
>
> [mchehab: do some cleanups a
On 13/8/24 18:52, Peter Maydell wrote:
Directly invoking the DeviceClass::reset method is a bad idea,
because if the device is using three-phase reset then it relies on
transitional reset machinery which is likely to disappear at some
point.
This seems like fix-for-9.1 material.
Reset the dev
Cc: YunQiang Su
Reported-by: Jiaxun Yang
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/mips64/target_elf.h | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/linux-user/mips64/target_elf.h b/linux-user/mips64/target_elf.h
index ce6fb6541e..a3a8b2e385 100644
--- a/l
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/mips64/target_elf.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/linux-user/mips64/target_elf.h b/linux-user/mips64/target_elf.h
index a3a8b2e385..502af9d278 100644
--- a/linux-user/mips64/target_elf.h
+++ b/linux-user/mips64/targe
R5900 emulation was removed in commit 823f2897bd.
Remove it from ELF parsing in order to avoid:
$ qemu-mipsn32 ./test5900
qemu-mipsn32: unable to find CPU model 'R5900'
This reverts commit 4d9e5a0eb7df6e98ac6cf5e16029f35dd05b9537.
Fixes: 823f2897bd ("target/mips: Disable R5900 support")
Sign
Improve CPU type selection:
- Remove R5900
- Cover Octeon / R2 / Loongson*
Philippe Mathieu-Daudé (4):
linux-user/mips: Do not try to use removed R5900 CPU
linux-user/mips: Select Octeon68XX CPU for Octeon binaries
linux-user/mips: Select MIPS64R2-generic for Rel2 binaries
linux-user/mips:
The Octeon68XX CPU is available since commit 9a6046a655
("target/mips: introduce Cavium Octeon CPU model").
Cc: Pavel Dovgalyuk
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1722
Reported-by: Johnathan Hữu Trí
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
On Wed, 14 Aug 2024 at 05:35, Michael Tokarev wrote:
>
> 18.06.2024 16:55, Zheyu Ma wrote:
> > This commit adds validation checks for the MCOPRE and MCOSEL values in
> > the rcc_update_cfgr_register function. If the MCOPRE value exceeds
> > 0b100 or the MCOSEL value exceeds 0b111, an error is logg
On Wed, 14 Aug 2024 at 01:53, Richard Henderson
wrote:
>
> On 8/14/24 02:52, Peter Maydell wrote:
> > Currently we have transitional machinery between legacy reset
> > and three phase reset that works in two directions:
> > * if you invoke three phase reset on a device which has set
> > theD
On Wed, 14 Aug 2024 01:23:24 +0200
Mauro Carvalho Chehab wrote:
> Adds support to ARM virtualization to allow handling
> generic error ACPI Event via GED & error source device.
>
> It is aligned with Linux Kernel patch:
> https://lore.kernel.org/lkml/1272350481-27951-8-git-send-email-ying.hu...@
On Tue, Aug 13, 2024 at 6:37 PM Peter Maydell wrote:
>
> On Tue, 13 Aug 2024 at 16:39, Juraj Marcin wrote:
> >
> > Some devices need to distinguish cold start reset from waking up from a
> > suspended state. This patch adds new value to the enum, and updates the
> > i386 wakeup method to use this
On Wed, 14 Aug 2024 01:23:23 +0200
Mauro Carvalho Chehab wrote:
> Adds a generic error device to handle generic hardware error
> events as specified at ACPI 6.5 specification at 18.3.2.7.2:
> https://uefi.org/specs/ACPI/6.5/18_Platform_Error_Interfaces.html#event-notification-for-generic-error-so
On 2024/8/5 14:27, Zhenzhong Duan wrote:
Per spec 6.5.2.4, PADID-selective PASID-based iotlb invalidation will
flush stage-2 iotlb entries with matching domain id and pasid.
With scalable modern mode introduced, guest could send PASID-selective
PASID-based iotlb invalidation to flush both stage-
On 2024/8/5 14:27, Zhenzhong Duan wrote:
According to VTD spec, stage-1 page table could support 4-level and
5-level paging.
However, 5-level paging translation emulation is unsupported yet.
That means the only supported value for aw_bits is 48.
So default aw_bits to 48 in scalable modern mode.
On 2024/8/5 14:27, Zhenzhong Duan wrote:
When host IOMMU doesn't support FS1GP but vIOMMU does, host IOMMU
can't translate stage-1 page table from guest correctly.
this series is for emulated devices, so the above statement does not
belong to this series. Is there any other reason to have this
On Mon, Aug 12, 2024 at 06:47:51PM -0700, Stefano Stabellini wrote:
> On Mon, 12 Aug 2024, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias"
> >
> > Break out a common Xen PVH module in preparation for
> > adding a x86 Xen PVH Machine.
> >
> > Signed-off-by: Edgar E. Iglesias
> > ---
> >
On 2024/8/5 14:27, Zhenzhong Duan wrote:
From: Clément Mathieu--Drif
First stage translation must fail if the address to translate is
not canonical.
Signed-off-by: Clément Mathieu--Drif
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu_internal.h | 2 ++
hw/i386/intel_iommu.c
Today for x86 the _PRT() table is computed in runtime.
Under some configurations, computing the _PRT table can take more than
30 seconds and the ACPI timeout is violated.
This patchset modifies _PRT() to return a pre-computed table.
Changelog v3->v4 Thanks Richard:
- Make link_name struct static
When qemu runs without kvm acceleration the ACPI executions take a great
amount of time. If they take more than the default time (30sec), the
ACPI calls fail and the system might not behave correctly.
Now the _PRT table is computed on the fly. We can drastically reduce the
execution of the _PRT me
Signed-off-by: Ricardo Ribalda
---
tests/data/acpi/x86/pc/DSDT | Bin 6830 -> 8527 bytes
tests/data/acpi/x86/pc/DSDT.acpierst| Bin 6741 -> 8438 bytes
tests/data/acpi/x86/pc/DSDT.acpihmat| Bin 8155 -> 9852 bytes
tests/data/acpi/x86/pc/DSDT.bridge | Bin 13
Signed-off-by: Ricardo Ribalda
---
tests/qtest/bios-tables-test-allowed-diff.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..f81f4e2469 100644
--- a/tests/qtest/bios
This bug looks specific to the RedHat SELinux configuration.
Is this any reason to move LOGFILE except this?
Best Regards,
Konstantin Kostiuk.
On Tue, Aug 13, 2024 at 6:11 AM Dehan Meng wrote:
> Since '/var/log/qga-fsfreeze-hook.log' is not included to proper
> selinux context 'system_u:object
On Tue, Aug 13, 2024 at 03:52:32PM -0700, Stefano Stabellini wrote:
> On Tue, 13 Aug 2024, Edgar E. Iglesias wrote:
> > On Mon, Aug 12, 2024 at 06:47:17PM -0700, Stefano Stabellini wrote:
> > > On Mon, 12 Aug 2024, Edgar E. Iglesias wrote:
> > > > From: "Edgar E. Iglesias"
> > > >
> > > > Add SMP
On 8/14/2024 3:54 PM, Xiaoyao Li wrote:
> The whole ECX of CPUID 0x8008 is reserved for Intel.
>
> Signed-off-by: Xiaoyao Li
> ---
> target/i386/cpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 5bee84333089..7a48
On 2024/8/5 14:27, Zhenzhong Duan wrote:
From: Clément Mathieu--Drif
Signed-off-by: Clément Mathieu--Drif
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu_internal.h | 3 +++
hw/i386/intel_iommu.c | 24
2 files changed, 27 insertions(+)
diff --git
On Wed, 14 Aug 2024 12:08, Junjie Mao wrote:
The official way to specify Rust edition in meson is the rust_std build option
[1]. It is used for generating --edition rustc options and filling
rust-project.json which provides project layout information to
rust-analyzer. Specifying Rust edition by
On 14/08/2024 01.03, Richard Henderson wrote:
On 8/14/24 02:52, Peter Maydell wrote:
static void sigp_cpu_reset(CPUState *cs, run_on_cpu_data arg)
{
- S390CPU *cpu = S390_CPU(cs);
- S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
SigpInfo *si = arg.host_ptr;
cpu_synchronize_st
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