Hi Richard,
Thanks for your feedback.
I think it is reasonable. I will drop this patchset.
Regards,
Jim Shu
On Fri, Jul 26, 2024 at 1:28 PM Richard Henderson
wrote:
>
> On 7/26/24 14:32, Jim Shu wrote:
> > Let gen-vdso tool to use QEMU's internal ELF header. It could avoid
> > compatibility is
Hi Cedric,
> Subject: Re: [PATCH v1 12/15] aspeed/soc: introduce a new API to get the INTC
> orgate information
>
> On 7/18/24 08:49, Jamin Lin wrote:
> > Currently, users can set the intc mapping table with enumerated device
> > id and device irq to get the INTC orgate input pins. However, some
>
On Jul 25 19:42, 卢长奇 wrote:
> Hi,
>
> ```
> 2685 nvme_status->regctl_ds[i].cntlid = nvme_ctrl(req)->cntlid;
> 2686 nvme_status->regctl_ds[i].rkey = keys_info->keys[i];
> 2687 nvme_status->regctl_ds[i].rcsts = keys_info->keys[i] ==
> 2688 reservation->key ? 1 : 0;
> 2689 /* hostid is not supported
On 7/25/2024 10:04 PM, David Hildenbrand wrote:
>> Open
>>
>> Implementing a RamDiscardManager to notify VFIO of page conversions
>> causes changes in semantics: private memory is treated as discarded (or
>> hot-removed) memory. This isn't aligned with the expectation of current
>> RamDisca
On Thu, Jul 25, 2024 at 06:18:20PM -0400, Peter Xu wrote:
> On Tue, Aug 01, 2023 at 01:31:48AM +0300, Yuri Benditovich wrote:
> > USO features of virtio-net device depend on kernel ability
> > to support them, for backward compatibility by default the
> > features are disabled on 8.0 and earlier.
>
On Thu, Jul 25, 2024 at 11:20:56PM +0100, David Woodhouse wrote:
> We're rolling out the AMZNVCLK device for internal use cases, and plan
> to add it in public instances some time later.
Let's be real. If amazon does something in its own hypervisor, and the
only way to use that is to expose the in
The purpose of this patch is customize refresh rate and resolution
for the guest VM instead of being limited by the actual resolution
of the host.
Although it is possible to configure the VM kernel cmdline to set the
EDID, such as with drm.edid_firmware=edid/1920x1080.bin, this approach
is very
customize refresh rate and resolution for the guest VM
instead of being limited by the actual resolution of the host.
add edid info and modify conf like:
"-device", "virtio-vga-gl,edid=on,max_outputs=2,
refresh_rate0=12,maxx0=7680,maxy0=1080,refresh_rate1=75000,
maxx1=3840,maxy1=960"
Change-I
Hi Cedric,
> Subject: Re: [PATCH v1 04/15] hw/i2c/aspeed: support discontinuous register
> memory region of I2C bus
>
> On 7/18/24 11:44, Jamin Lin wrote:
> > Hi Cedric,
> >
> >> Subject: Re: [PATCH v1 04/15] hw/i2c/aspeed: support discontinuous
> >> register memory region of I2C bus
> >>
> >> On
Fix txlen value in the descriptor status field, DMA error handling,
and ethernet/DMA reset flow.
*** BLURB HERE ***
Jim Shu (4):
hw/dma: xilinx_axidma: Correct the txlen value in the descriptor
hw/dma: xilinx_axidma: Send DMA error IRQ if any memory access is
failed
hw/dma: xilinx_axidm
The memory transactions from DMA could have bus-error in some cases. If
it is failed, DMA device should send error IRQs.
Signed-off-by: Jim Shu
---
hw/dma/trace-events| 1 +
hw/dma/xilinx_axidma.c | 69 ++
2 files changed, 50 insertions(+), 20 deletio
Current DMA/Stream reset will clear interrupt pending bit of DMA device.
The qemu_irq of device should be updated at the same time.
Signed-off-by: Jim Shu
---
hw/dma/xilinx_axidma.c | 25 +
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/hw/dma/xilinx_axid
When AXI ethernet RX is disabled, it shouldn't send packets to AXI DMA,
which may let AXI DMA to send RX full IRQs. It is aligned with real AXI
DMA/ethernet IP behavior in the FPGA.
Also, now ethernet RX blocks the RX packets when it is disabled. It
should send and clear the remaining RX packets w
Currently, txlen is always decremented to 0 before filling to the
descriptor. Keep the origin txlen value to have the correct value of
descriptor status field.
It will fix the 'tx_bytes' statistic value in linux axi-ethernet driver.
Signed-off-by: Jim Shu
---
hw/dma/xilinx_axidma.c | 5 +++--
1
On Fri, Jul 26, 2024 at 01:09:24AM -0400, Michael S. Tsirkin wrote:
> On Thu, Jul 25, 2024 at 10:29:18PM +0100, David Woodhouse wrote:
> > > > > Then can't we fix it by interrupting all CPUs right after LM?
> > > > >
> > > > > To me that seems like a cleaner approach - we then compartmentalize
> >
On 7/26/24 14:32, Jim Shu wrote:
Add include path to 'gen-vdso.c' to get ELF header in QEMU source.
Signed-off-by: Jim Shu
---
linux-user/meson.build | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/linux-user/meson.build b/linux-user/meson.build
index bc41e8c3bc..ccce
On 7/26/24 14:32, Jim Shu wrote:
Let gen-vdso tool to use QEMU's internal ELF header. It could avoid
compatibility issue of glibc version in the environment. QEMU RISC-V
zicfiss/lp extension patchset will add "EM_RISCV" symbol to it. This
symbol is not supported in the legacy glibc.
I see EM_RI
On 7/26/24 14:32, Jim Shu wrote:
Rename DT_BINDNOW to DT_BIND_NOW to align with glibc header: "elf/elf.h"
Signed-off-by: Jim Shu
---
include/elf.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On Wed, Jul 24, 2024 at 6:33 PM Atish Patra wrote:
>
> Coverity complained about the possible out-of-bounds access with
> counter_virt/counter_virt_prev because these two arrays are
> accessed with privilege mode. However, these two arrays are accessed
> only when virt is enabled. Thus, the privil
On 7/26/24 06:12, Stefan Hajnoczi wrote:
The following changes since commit 029e13a8a56a2931e7c24c0db52ae7256b932cb0:
Merge tag 'bsd-user-for-9.1-pull-request' ofgitlab.com:bsdimp/qemu into
staging (2024-07-25 09:53:57 +1000)
are available in the Git repository at:
https://gitlab.com/st
On Thu, Jul 25, 2024 at 10:29:18PM +0100, David Woodhouse wrote:
> > > > Then can't we fix it by interrupting all CPUs right after LM?
> > > >
> > > > To me that seems like a cleaner approach - we then compartmentalize
> > > > the ABI issue - kernel has its own ABI against userspace,
> > > > devic
> From: David Hildenbrand
> Sent: Thursday, July 25, 2024 10:04 PM
>
> > Open
> >
> > Implementing a RamDiscardManager to notify VFIO of page conversions
> > causes changes in semantics: private memory is treated as discarded (or
> > hot-removed) memory. This isn't aligned with the expectati
Add include path to 'gen-vdso.c' to get ELF header in QEMU source.
Signed-off-by: Jim Shu
---
linux-user/meson.build | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/linux-user/meson.build b/linux-user/meson.build
index bc41e8c3bc..ccce4f7e70 100644
--- a/linux-user/meson.
Let gen-vdso tool to use QEMU's internal ELF header. It could avoid
compatibility issue of glibc version in the environment. QEMU RISC-V
zicfiss/lp extension patchset will add "EM_RISCV" symbol to it. This
symbol is not supported in the legacy glibc.
Jim Shu (2):
include/elf.h: align ELF macro
Rename DT_BINDNOW to DT_BIND_NOW to align with glibc header: "elf/elf.h"
Signed-off-by: Jim Shu
---
include/elf.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/elf.h b/include/elf.h
index e7259ec366..ef47b5e2ad 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -235,
On Wed, Jul 24, 2024 at 11:08 PM Philippe Mathieu-Daudé
wrote:
>
> The 'any' CPU is deprecated since commit f57d5f8004b
> ("target/riscv: deprecate the 'any' CPU type"). Users
> are better off using the default CPUs or the 'max' CPU.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistai
Hi,
```
2685 nvme_status->regctl_ds[i].cntlid = nvme_ctrl(req)->cntlid;
2686 nvme_status->regctl_ds[i].rkey = keys_info->keys[i];
2687 nvme_status->regctl_ds[i].rcsts = keys_info->keys[i] ==
2688 reservation->key ? 1 : 0;
2689 /* hostid is not supported currently */
2670 memset(&nvme_status->regct
On Wed, Jul 24, 2024 at 8:02 PM David Woodhouse wrote:
>
> On Tue, 2024-07-09 at 15:46 +0300, Michael Tokarev wrote:
> > 09.07.2024 15:34, David Woodhouse wrote:
> > > From: David Woodhouse
> > >
> > > While refactoring the NIC initialization code, I broke '-net
> > > nic,model=help'
> > > which
On Thu, Jul 25, 2024 at 2:49 PM Laurent Vivier wrote:
>
> On 04/07/2024 14:48, Laurent Vivier wrote:
> > Add the description of "-netdev stream" and "-netdev dgram" in the QEMU
> > manpage.
> >
> > Add some examples on how to use them, including a way to use
> > "-netdev stream" and "passt" in pla
On Fri, Jul 26, 2024 at 6:19 AM Peter Xu wrote:
>
> On Tue, Aug 01, 2023 at 01:31:48AM +0300, Yuri Benditovich wrote:
> > USO features of virtio-net device depend on kernel ability
> > to support them, for backward compatibility by default the
> > features are disabled on 8.0 and earlier.
> >
> >
Hi Cedric,
> Subject: Re: [PATCH v1 08/15] hw/i2c/aspeed: introduce a new
> dma_dram_offset attribute in AspeedI2Cbus
>
> On 7/18/24 08:49, Jamin Lin wrote:
> > The "Current DMA Operating Address Status(0x50)" register of I2C new
> > mode has been removed in AST2700.
> > This register is used for
> On Wed, Jul 24, 2024 at 10:09 AM Lei Wang wrote:
> > Because the index value of the VMCS field encoding of Secondary
> > VM-exit controls, 0x44, is larger than any existing index value, raise
> > the highest index value used for any VMCS encoding to 0x44.
> >
> > Because the index value of the V
On 7/26/24 12:51 AM, Salil Mehta wrote:
Loop should exit prematurely on successfully finding out the parked vCPU (struct
KVMParkedVcpu) in the 'struct KVMState' maintained 'kvm_parked_vcpus' list of
parked vCPUs.
Fixes: Coverity CID 1558552
Fixes: 08c3286822 ("accel/kvm: Extract common KVM vCPU
> -Original Message-
> From: Peter Maydell
> Sent: Thursday, July 25, 2024 11:14 PM
> To: Yao, Xingtao/姚 幸涛
> Cc: Philippe Mathieu-Daudé ; qemu-devel@nongnu.org
> Subject: Re: [PATCH 00/13] make range overlap check more readable
>
> On Mon, 22 Jul 2024 at 08:00, Xingtao Yao (Fujitsu) v
OpenSBI has support for domains, which are partitions of CPUs and memory into
isolated compartments. Domains can be specified in the device tree according to
a standardized format [1], which OpenSBI parses at boot time to initialize all
system domains. This patch enables simply specifying domains (
From: Chinmay Rath
Moving the following instructions to decodetree specification:
lxv{b16, d2, h8, w4, ds, ws}x : X-form
stxv{b16, d2, h8, w4}x : X-form
The changes were verified by validating that the tcg-ops generated for those
instructions remain the same, which were captured
From: Chinmay Rath
Updated instructions {l, st}vx to use tcg_gen_qemu_ld/st_i128,
instead of using 64 bits loads/stores in succession.
Introduced functions {get, set}_avr_full in vmx-impl.c.inc to
facilitate the above, and potential future usage.
Reviewed-by: Richard Henderson
Suggested-by: Ric
From: Chinmay Rath
Moving the following instructions to decodetree specification :
{l, st}xvl(l) : X-form
The changes were verified by validating that the tcg-ops generated by those
instructions remain the same, which were captured using the '-d in_asm,op' flag.
Also added a
From: BALATON Zoltan
Pass raddr and prot in function parameters instead
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/target/ppc/mmu_c
From: BALATON Zoltan
This function is a simple shared function, move it to other similar
static inline functions in the header.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu-hash32.c | 7 ---
target/ppc/mmu-hash32.h | 6 +
From: BALATON Zoltan
The ppc_hash64_hpt_base() and ppc_hash64_hpt_mask() functions are
mostly used by mmu-hash64.c only but there is one call to
ppc_hash64_hpt_mask() in hw/ppc/spapr_vhyp_mmu.c.in a helper function
that can be moved to mmu-hash64.c which allows these functions to be
removed from
From: Frederic Barrat
Moving xive2_nvp_pic_print_info() to align with the other "pic_print_info"
functions.
Signed-off-by: Frederic Barrat
Signed-off-by: Michael Kowal
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/intc/pnv_xive2.c | 27 -
From: BALATON Zoltan
In ppc6xx_tlb_pte_check() the pp variable is used only once to pass it
to a function parameter with the same name. Remove the local and
inline the value. Also use named constant for the hex value to make it
clearer.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
From: Chalapathi V
In this commit target specific dependency from include/hw/ppc/pnv_xscom.h
has been removed so that pnv_xscom.h can be included outside hw/ppc.
Signed-off-by: Chalapathi V
Reviewed-by: Cédric Le Goater
Reviewed-by: Caleb Schlossin
Signed-off-by: Nicholas Piggin
---
include
From: BALATON Zoltan
Move the parts not needed outside of mmu-radix64.c from the header to
the C file to leave only parts in the header that need to be exported.
Also drop unneded include of this header.
Signed-off-by: BALATON Zoltan
Acked-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
--
From: Chalapathi V
SPI controller device model supports a connection to a single SPI responder.
This provide access to SPI seeproms, TPM, flash device and an ADC controller.
All SPI function control is mapped into the SPI register space to enable full
control by firmware. In this commit SPI conf
From: Chinmay Rath
No need for a full comparison; xor produces non-zero bits for QC just fine.
Suggested-by: Richard Henderson
Signed-off-by: Chinmay Rath
Reviewed-by: Richard Henderson
Signed-off-by: Nicholas Piggin
---
target/ppc/translate/vmx-impl.c.inc | 14 +++---
1 file change
From: BALATON Zoltan
This function is only called once and we can make the caller simpler
by inlining it.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 71 +
1 file changed, 22 i
Power CPUs have an execution control facility that can pause, resume,
and cause NMIs, among other things. Add a function that will nmi a CPU
and resume it if it was paused, in preparation for implementing the
control facility.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/
From: BALATON Zoltan
Replace some BAT related constants with defines from mmu-hash32.h
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
dif
The PC unit in the processor core contains xscom registers that provide
low level status and control of the CPU.
This implements "direct controls", sufficient for skiboot firmware,
which uses it to send NMI IPIs between CPUs.
POWER10 is sufficiently different from POWER9 (particularly with respec
From: BALATON Zoltan
Drop includes from header that is not needed by the header itself and
only include them from C files that really need it.
Signed-off-by: BALATON Zoltan
Acked-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu-book3s-v3.h | 3 ---
target/ppc/mmu-hash64.
From: BALATON Zoltan
The ppc6xx_tlb_check() relies on the caller to initialise raddr field
in ctx. Move this init from the only caller into the function.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 4 ++--
1 file cha
From: BALATON Zoltan
Invert conditions to avoid deep nested ifs and return early instead.
Remove some obvious comments that don't add more clarity.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 43 ++---
From: BALATON Zoltan
This is used only once and can be inlined.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu-hash32.c | 19 ---
1 file changed, 4 insertions(+), 15 deletions(-)
diff --git a/target/ppc/mmu-hash32
Power9 CPUs have a core thread state register accessible via SPRC/SPRD
indirect registers. This register includes a bit for big-core mode,
which skiboot requires.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/misc_helper.c | 17 +
1 file changed, 17
From: BALATON Zoltan
Reorganise ppc_hash32_pp_prot() swapping the if legs so it does not
test for negative first and clean up to make it shorter. Also rename
it to ppc_hash32_prot().
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu-
From: Frederic Barrat
The cache watch facility uses the same register interface to handle
entries in the NVP, NVG and NVC tables. A bit-field in the 'watchX
specification' register tells the table type. So far, that bit-field
was not read and the code assumed a read/write to the NVP table.
This
From: Chinmay Rath
Those functions are used to ld/st data to and from Altivec registers,
in 64 bits chunks, and are only used in vmx-impl.c.inc file,
hence the clean-up movement.
Reviewed-by: Richard Henderson
Signed-off-by: Chinmay Rath
Signed-off-by: Nicholas Piggin
---
target/ppc/translat
From: Frederic Barrat
Additional END state 'info pic' information as added. The 'ignore',
'crowd' and 'precluded escalation control' bits of an Event Notification
Descriptor are all used when delivering an interrupt targeting a VP-group
or crowd.
Signed-off-by: Frederic Barrat
Signed-off-by: M
From: BALATON Zoltan
Pass raddr and prot in function parameters instead.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/targ
From: BALATON Zoltan
Add a function to get key bit from SR and use it instead of open coded
version.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu-hash32.c | 9 ++---
target/ppc/mmu-hash32.h | 5 +
target/ppc/mmu_common.c
From: Chinmay Rath
Moving the following instructions to decodetree specification :
xxl{and, andc, or, orc, nor, xor, nand, eqv}: XX3-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm
The POWER8 LPC ISA device irqs all get combined and reported to the line
connected the PSI LPCHC irq. POWER9 changed this so only internal LPC
host controller irqs use that line, and the device irqs get routed to
4 new lines connected to PSI SERIRQ0-3.
POWER9 also introduced a new feature that aut
Recent POWER CPUs can operate in "LPAR per core" or "LPAR per thread"
modes. In per-core mode, some SPRs and IPI doorbells are shared between
threads in a core. In per-thread mode, supervisor and user state is
not shared between threads.
OpenPOWER systems after POWER8 use LPAR per thread mode, and
From: Frederic Barrat
Enable NVG and NVC VST tables for index compression which indicates the number
of bits the address is shifted to the right for the table accesses.
The compression values are defined as:
- No compression
0001 - 1 bit shift
0010 - 2 bit shift
1000 - 8
From: Frederic Barrat
Fail VST entry address computation if firmware doesn't define a descriptor
for one of the Virtualization Structure Tables (VST), there's no point in
trying to compute the address of its entry. Abort the operation and log
an error.
Signed-off-by: Frederic Barrat
Signed-off
From: Frederic Barrat
Both the virtualization layer (VC) and presentation layer (PC) need to
be configured to access the VSTs. Since the information is redundant,
the xive model combines both into one set of tables and only the
definitions going through the VC are kept. The definitions through th
From: Chinmay Rath
Moving the following instructions to decodetree specification:
x{s, v}{add, sub, mul, div}{s, d}p : XX3-form
xs{max, min}dp, xv{max, min}{s, d}p : XX3-form
The changes were verfied by validating that the tcg ops generated by those
instructions remain
From: BALATON Zoltan
Instead of passing around ptem in context use it once in the same
function so it can be removed from mmu_ctx_t.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 23 ++-
1 file chan
From: BALATON Zoltan
The ptev variable in ppc6xx_tlb_pte_check() is used only once and just
obfuscates an otherwise clear value. Get rid of it.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 5 ++---
1 file changed, 2 i
From: BALATON Zoltan
The eaddr field of mmu_ctx_t is set once but never used so can be
removed.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/ppc/mmu_common.c b
From: BALATON Zoltan
There is already a hash32_bat_prot() function that does most if this
and the rest can be inlined. Export hash32_bat_prot() and rename it to
ppc_hash32_bat_prot() to match other functions and use it in
get_bat_6xx_tlb().
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Pi
From: BALATON Zoltan
In ppc6xx_tlb_pte_check() the pteh variable is used only once to
compare to the h parameter of the function. Inline its value and use
pteh name for the function parameter which is more descriptive.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: N
From: BALATON Zoltan
In mmu6xx_get_physical_address() the switch handles all cases so the
default is never reached and can be dropped. Also group together cases
which just return -4.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_
From: BALATON Zoltan
This function is used only once and does not add more clarity than
doing it inline.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu-hash32.c | 18 +-
1 file changed, 5 insertions(+), 13 deletion
From: BALATON Zoltan
Instead of using a local ret variable return directly and remove the
local.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git
From: Chinmay Rath
Updated many VSX instructions to use tcg_gen_qemu_ld/st_i128, instead of using
tcg_gen_qemu_ld/st_i64 consecutively.
Introduced functions {get,set}_vsr_full to facilitate the above & for future
use.
Reviewed-by: Richard Henderson
Suggested-by: Richard Henderson
Signed-off-b
The chip_pir chip class method allows the platform to set the PIR
processor identification register. Extend this to a more general
ID function which also allows the TIR to be set. This is in
preparation for "big core", which is a more complicated topology
of cores and threads.
Reviewed-by: Cédric
From: Chinmay Rath
Moving the following instructions to decodetree specification:
xvcmp{eq, gt, ge, ne}{s, d}p: XX3-form
The changes were verified by validating that the tcg-ops generated for those
instructions remain the same which were captured using the '-d in_asm,op' flag.
Sign
POWER9 and POWER10 machines come in two variants, big-core and
small-core. Big-core machines are SMT8 from software's point of view,
but the low level platform topology ("xscom registers and pervasive
addressing"), these look more like a pair of small cores ganged
together.
Presently the way this
From: BALATON Zoltan
Pass it as a parameter instead. Also use named constants instead of
hex values when extracting bits from SR.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 24
1 file change
From: BALATON Zoltan
The ptem variable in ppc6xx_tlb_pte_check() is used only once,
simplify by removing it as the value is already clear itself without
adding a local name for it.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_co
From: BALATON Zoltan
Completely get rid of mmu_ctx_t after converting the remaining
functions to pass raddr and prot without the context struct.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 25 +++-
From: BALATON Zoltan
Rename parameter of get_bat_6xx_tlb() from virtual to eaddr to match
other functions.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 18 +-
1 file changed, 9 insertions(+), 9 deletio
From: BALATON Zoltan
Return hash value via a parameter and remove it from mmu_ctx.t.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 19 ---
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a/
Add helpers for TCG code to determine if there are SMT siblings
sharing per-core and per-lpar registers. This simplifies the
callers and makes SMT register topology simpler to modify with
later changes.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h
From: Chalapathi V
In this commit Write a qtest pnv-spi-seeprom-test to check the
SPI transactions between spi controller and seeprom device.
Signed-off-by: Chalapathi V
Acked-by: Cédric Le Goater
Reviewed-by: Caleb Schlossin
Signed-off-by: Nicholas Piggin
---
tests/qtest/meson.build
From: Frederic Barrat
XIVE offers a 'cache watch facility', which allows software to read/update
a potentially cached table entry with no software lock. There's one such
facility in the Virtualization Controller (VC) to update the ESB and END
entries and one in the Presentation Controller (PC) to
POWER8 (ISA v2.07S) introduced the doorbell facility, the msgsnd
instruction behaved mostly like msgsndp, it was addressed by TIR
and could only send interrupts between threads on the core.
ISA v3.0 changed msgsnd to be addressed by PIR and can interrupt
any thread in the system.
msgsnd only impl
Adds support for writing a completion notification byte in memory
whenever a cache flush or queue sync inject operation is requested by
software. QEMU does not cache any of the XIVE data that is in memory and
therefore it simply writes the completion notification byte at the time
that the operatio
From: Akihiko Odaki
This fixes LeakSanitizer warnings.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_vof.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/spapr_vof.
From: BALATON Zoltan
In mmu6xx_get_physical_address() tagtet_page_bits local is declared
only to use TARGET_PAGE_BITS once. Drop the unneeded variable.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 4 +---
1 file chang
From: BALATON Zoltan
Pass it as a function parameter and remove it from mmu_ctx_t.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 26 ++
1 file changed, 14 insertions(+), 12 deletions(-)
diff --
From: BALATON Zoltan
The mmask local variable is a less descriptive local name for a
constant. Drop it and use the constant directly in the two places it
is needed.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 5 ++---
From: Frederic Barrat
In XIVE Gen 2 there were some minor changes to the TIMA header that were
updated when printed.
Signed-off-by: Frederic Barrat
Signed-off-by: Michael Kowal
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 12 +---
1 file changed,
The timebase state machine is per per-core state and can be driven
by any thread in the core. It is currently implemented as a hack
where the state is in a CPU structure and only thread 0's state is
accessed by the chiptod, which limits programming the timebase
side of the state machine to thread 0
From: Chinmay Rath
Moving the following instructions to decodetree specification :
v{add,sub}{u,s}{b,h,w}s : VX-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Revie
The way SMT thread siblings are matched is clunky, using hard-coded
logic that checks the PIR SPR.
Change that to use a new core_index variable in the CPUPPCState,
where all siblings have the same core_index. CPU realize routines have
flexibility in setting core/sibling topology.
Reviewed-by: Céd
From: BALATON Zoltan
This function is used only once, its return value is ignored and one
of its parameter is a return value from a previous call. It is better
to inline it in the caller and remove it.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
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