On 2024/07/16 15:38, Philippe Mathieu-Daudé wrote:
On 16/7/24 08:07, Akihiko Odaki wrote:
On 2024/07/16 6:06, Phil Dennis-Jordan wrote:
Date: Mon, 15 Jul 2024 21:07:12 +0200
Subject: [PATCH 00/26] hw/display/apple-gfx: New macOS PV Graphics
device
MIME-Version: 1.0
Content-Type: text/plain; c
On 16/7/24 00:01, Mark Cave-Ayland wrote:
On 15/07/2024 07:48, Philippe Mathieu-Daudé wrote:
On 14/7/24 00:42, Mark Cave-Ayland wrote:
The transfer size check was originally added to prevent consecutive
DMA TI
commands from causing an assert() due to an existing SCSI request
being in
progres
When ram_block_discard_require() fails, errno is passed to error_setg_errno().
It's a stale value or 0 which is unrelated to ram_block_discard_require().
As ram_block_discard_require() already returns -EBUSY in failure case,
use it as errno for error_setg_errno().
Fixes: 852f0048f3ea ("make guest
On 16/7/24 03:29, maobibo wrote:
On 2024/7/16 上午9:04, maobibo wrote:
On 2024/7/15 下午11:17, Philippe Mathieu-Daudé wrote:
On 4/7/24 05:37, Bibo Mao wrote:
Now loongson ipi and loongarch ipi share the same code with different
macro, loongson ipi has its separate function such mmio region,
lo
On 16/07/2024 01.00, Richard Henderson wrote:
Hi guys,
CI currently failing FreeBSD:
https://gitlab.com/qemu-project/qemu/-/jobs/7347517439
pkg: No packages available to install matching 'py39-pillow' have been
found in the repositories
pkg: No packages available to install matching 'py39-pip
On 16/7/24 08:07, Akihiko Odaki wrote:
On 2024/07/16 6:06, Phil Dennis-Jordan wrote:
Date: Mon, 15 Jul 2024 21:07:12 +0200
Subject: [PATCH 00/26] hw/display/apple-gfx: New macOS PV Graphics device
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This seq
On Tue, 2 Jul 2024 at 15:09, Jason Wang wrote:
>
> On Tue, Jul 2, 2024 at 10:00 AM Cindy Lu wrote:
> >
> > The crash was reported in MAC OS and NixOS, here is the link for this bug
> > https://gitlab.com/qemu-project/qemu/-/issues/2334
> > https://gitlab.com/qemu-project/qemu/-/issues/2321
> >
>
On 2024/07/15 20:47, Daniel P. Berrangé wrote:
On Sun, Jul 14, 2024 at 02:11:02PM +0900, Akihiko Odaki wrote:
DEFINE_PROP_ON_OFF_AUTO_BIT64() corresponds to DEFINE_PROP_ON_OFF_AUTO()
as DEFINE_PROP_BIT64() corresponds to DEFINE_PROP_BOOL(). The difference
is that DEFINE_PROP_ON_OFF_AUTO_BIT64()
On 2024/7/11 上午10:44, Song Gao wrote:
GDB already support LoongArch vector extension[1], QEMU gdb adds
LoongArch vector registers support, so that users can use 'info all-registers'
to get all vector registers values.
[1]:
https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=1e9569f
On 2024/07/15 20:38, Daniel P. Berrangé wrote:
On Sun, Jul 14, 2024 at 02:11:01PM +0900, Akihiko Odaki wrote:
Accept bool literals for OnOffAuto properties for consistency with bool
properties.
Signed-off-by: Akihiko Odaki
---
hw/core/qdev-properties.c | 17 -
1 file changed
Collin Walling writes:
> On 7/12/24 1:23 AM, Markus Armbruster wrote:
>> Collin Walling writes:
>>
>>> It is beneficial to provide an interface to retrieve *all* deprecated
>>> features in one go. Management applications will need this information
>>> to determine which features need to be disa
On Tue, 16 Jul 2024 at 13:37, Jason Wang wrote:
>
> On Tue, Jul 16, 2024 at 9:14 AM Cindy Lu wrote:
> >
> > When using a VDPA device, it is important to ensure that the MAC address
> > in the hardware matches the MAC address from the QEMU command line.
> >
> > There are only two acceptable situat
On 2024/07/16 6:06, Phil Dennis-Jordan wrote:
Date: Mon, 15 Jul 2024 21:07:12 +0200
Subject: [PATCH 00/26] hw/display/apple-gfx: New macOS PV Graphics device
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This sequence of patches integrates the paravirt
On Tue, 16 Jul 2024 at 09:56, Lei Yang wrote:
>
> Hi Cindy
>
> If needed, QE can help test this MR before merging into the master branch.
>
> Best Regards
> Lei
>
sure， Really thanks for your help
thanks
cindy
>
> On Tue, Jul 16, 2024 at 9:14 AM Cindy Lu wrote:
> >
> > When using a VDPA device, i
On Tue, Jul 16, 2024 at 9:14 AM Cindy Lu wrote:
>
> When using a VDPA device, it is important to ensure that the MAC address
> in the hardware matches the MAC address from the QEMU command line.
>
> There are only two acceptable situations:
> 1. The hardware MAC address is the same as the MAC addr
On 11 Jul 2024, at 5:22 PM, Sandesh Patel wrote:
Thanks David for all the analysis.
Looking at the Linux guest support, it seems to look just at the HyperV
CPUID leaves 0x4081 and 0x4082. QEMU knows of those only for
SYNDBG; Sandesh do you want to try setting the
HYPERV_VS_PROPERTIES_E
Ping !
在 2024/7/11 上午10:44, Song Gao 写道:
GDB already support LoongArch vector extension[1], QEMU gdb adds
LoongArch vector registers support, so that users can use 'info all-registers'
to get all vector registers values.
[1]:
https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=1e9569f
Hi Igor,
On 15/07/2024 15:11, Igor Mammedov wrote:
On Mon, 15 Jul 2024 14:19:12 +
Salil Mehta wrote:
From: qemu-arm-bounces+salil.mehta=huawei@nongnu.org On Behalf Of Salil
Mehta via
Sent: Monday, July 15, 2024 3:14 PM
To: Igor Mammedov
Hi Igor,
> From: Igor Mam
Signed-off-by: Song Gao
---
include/qemu/timer.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/include/qemu/timer.h b/include/qemu/timer.h
index 5ce83c7911..fa56ec9481 100644
--- a/include/qemu/timer.h
+++ b/include/qemu/timer.h
@@ -1016,6 +1016,15 @@ static inline int64_t cpu_get_
Hi Zide,
On Mon, Jul 15, 2024 at 03:18:07PM -0700, Chen, Zide wrote:
> Date: Mon, 15 Jul 2024 15:18:07 -0700
> From: "Chen, Zide"
> Subject: Re: [PATCH v3 7/8] target/i386/kvm: Clean up return values of MSR
> filter related functions
>
> On 7/14/2024 9:49 PM, Zhao Liu wrote:
> > @@ -5274,13 +52
On Mon, Jul 15, 2024 at 11:01:08PM +0200, Eugenio Perez Martin wrote:
> Date: Mon, 15 Jul 2024 23:01:08 +0200
> From: Eugenio Perez Martin
> Subject: Re: [PATCH] hw/virtio/vdpa-dev: Check returned value instead of
> dereferencing @errp
>
> On Mon, Jul 15, 2024 at 11:45 AM Zhao Liu wrote:
> >
>
> -Original Message-
> From: Yichen Wang
> Sent: Tuesday, July 16, 2024 6:13 AM
> To: Peter Xu ; Fabiano Rosas ; Paolo
> Bonzini ; Daniel P. Berrangé ;
> Eduardo Habkost ; Marc-André Lureau
> ; Thomas Huth ; Philippe
> Mathieu-Daudé ; Eric Blake ; Markus
> Armbruster ; Laurent Vivier ; qem
> -Original Message-
> From: Yichen Wang
> Sent: Tuesday, July 16, 2024 6:13 AM
> To: Peter Xu ; Fabiano Rosas ; Paolo
> Bonzini ; Daniel P. Berrangé ;
> Eduardo Habkost ; Marc-André Lureau
> ; Thomas Huth ; Philippe
> Mathieu-Daudé ; Eric Blake ; Markus
> Armbruster ; Laurent Vivier ; qem
On Tue, Jul 16, 2024 at 7:01 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Hi guys,
>
> CI currently failing FreeBSD:
>
> https://gitlab.com/qemu-project/qemu/-/jobs/7347517439
>
> > pkg: No packages available to install matching 'py39-pillow' have been
> found in the repositories
Hi Cindy
If needed, QE can help test this MR before merging into the master branch.
Best Regards
Lei
On Tue, Jul 16, 2024 at 9:14 AM Cindy Lu wrote:
>
> When using a VDPA device, it is important to ensure that the MAC address
> in the hardware matches the MAC address from the QEMU command line
On 2024/7/16 上午9:04, maobibo wrote:
On 2024/7/15 下午11:17, Philippe Mathieu-Daudé wrote:
On 4/7/24 05:37, Bibo Mao wrote:
Now loongson ipi and loongarch ipi share the same code with different
macro, loongson ipi has its separate function such mmio region,
loongarch ipi has other requirement
> -Original Message-
> From: Michael S. Tsirkin
> Sent: Tuesday, July 16, 2024 12:24 AM
> To: Liu, Yuan1
> Cc: Wang, Yichen ; Paolo Bonzini
> ; Marc-André Lureau ;
> Daniel P. Berrangé ; Thomas Huth ;
> Philippe Mathieu-Daudé ; Peter Xu ;
> Fabiano Rosas ; Eric Blake ; Markus
> Armbruster
> -Original Message-
> From: Michael S. Tsirkin
> Sent: Tuesday, July 16, 2024 12:09 AM
> To: Liu, Yuan1
> Cc: Wang, Yichen ; Paolo Bonzini
> ; Marc-André Lureau ;
> Daniel P. Berrangé ; Thomas Huth ;
> Philippe Mathieu-Daudé ; Peter Xu ;
> Fabiano Rosas ; Eric Blake ; Markus
> Armbruster
On Fri, Jul 12, 2024 at 2:47 PM Michael S. Tsirkin wrote:
>
> On Fri, Jul 12, 2024 at 11:06:49AM +0900, David Stevens wrote:
> > On Thu, Jul 11, 2024 at 7:56 PM Alyssa Ross wrote:
> > >
> > > Adding David Stevens, who implemented SHMEM_MAP and SHMEM_UNMAP in
> > > crosvm a couple of years ago.
>
When using a VDPA device, it is important to ensure that the MAC address
in the hardware matches the MAC address from the QEMU command line.
There are only two acceptable situations:
1. The hardware MAC address is the same as the MAC address specified in the QEMU
command line, and both MAC address
On 2024/7/15 下午11:31, Philippe Mathieu-Daudé wrote:
On 4/7/24 05:37, Bibo Mao wrote:
Loongson ipi common class and instance is created here, it comes
from file loongson_ipi mostly. For the new added loongson ipi
common class, there is four interfaces defined here:
1. Interfaces pre_save/pos
On 2024/7/15 下午11:17, Philippe Mathieu-Daudé wrote:
On 4/7/24 05:37, Bibo Mao wrote:
Now loongson ipi and loongarch ipi share the same code with different
macro, loongson ipi has its separate function such mmio region,
loongarch ipi has other requirement such as irqchip in kernel.
Interrupt
On 7/16/24 03:32, John Snow wrote:
The following changes since commit 4469bee2c529832d762af4a2f89468c926f02fe4:
Merge tag 'nvme-next-pull-request' ofhttps://gitlab.com/birkelund/qemu into
staging (2024-07-11 14:32:51 -0700)
are available in the Git repository at:
https://gitlab.com/jsn
On Mon, Jul 15, 2024 at 7:05 PM Daniel Henrique Barboza
wrote:
>
> Commit b1f1e9dcfa renamed 'riscv,delegate' to 'riscv,delegation' since
> it is the correct name as per dt-bindings, and the absence of the
> correct name will result in validation fails when dumping the dtb and
> using dt-validate.
On 7/15/24 01:15, Simon Hamelin wrote:
This new plugin allows to stop emulation using conditions on the
emulation state. By setting this plugin arguments, it is possible
to set an instruction count limit and/or trigger address(es) to stop at.
The code returned at emulation exit can be customized.
On 7/15/24 01:09, Simon Hamelin wrote:
Hello Pierrick,
Could you share a bit more information on the final goal, if possible?
Is that used for fuzzing binaries, security analysis, or other things?
I'm currently using this plugin for security analysis purposes.
Basically my goal is to simulate
Hi guys,
CI currently failing FreeBSD:
https://gitlab.com/qemu-project/qemu/-/jobs/7347517439
pkg: No packages available to install matching 'py39-pillow' have been found in
the repositories
pkg: No packages available to install matching 'py39-pip' have been found in
the repositories
pkg: No
On 7/16/24 07:39, Gustavo Romero wrote:
Capstone v6 made major changes, such as renaming for AArch64, which
broke programs using the old headers, like QEMU. However, Capstone v6
provides the CAPSTONE_AARCH64_COMPAT_HEADER compatibility definition
allowing to build against v6 with the old definiti
On 7/14/2024 9:49 PM, Zhao Liu wrote:
> @@ -5274,13 +5272,13 @@ void kvm_arch_update_guest_debug(CPUState *cpu,
> struct kvm_guest_debug *dbg)
> }
> }
>
> -static bool kvm_install_msr_filters(KVMState *s)
> +static int kvm_install_msr_filters(KVMState *s)
> {
> uint64_t zero = 0;
From: Yuan Liu
add Intel QATzip compression method introduction
Signed-off-by: Yuan Liu
Reviewed-by: Nanhai Zou
Reviewed-by: Peter Xu
Reviewed-by: Yichen Wang
---
docs/devel/migration/features.rst | 1 +
docs/devel/migration/qatzip-compression.rst | 251
2 f
From: Bryan Zhang
Adds support for 'qatzip' as an option for the multifd compression
method parameter, and implements using QAT for 'qatzip' compression and
decompression.
Signed-off-by: Bryan Zhang
Signed-off-by: Hao Xiang
Signed-off-by: Yichen Wang
---
hw/core/qdev-properties-system.c |
From: Bryan Zhang
Adds an integration test for 'qatzip'.
Signed-off-by: Bryan Zhang
Signed-off-by: Hao Xiang
Signed-off-by: Yichen Wang
Reviewed-by: Fabiano Rosas
---
tests/qtest/migration-test.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/tests/qtes
From: Bryan Zhang
Adds support for migration parameters to control QATzip compression
level and to enable/disable software fallback when QAT hardware is
unavailable. This is a preparatory commit for a subsequent commit that
will actually use QATzip compression.
Signed-off-by: Bryan Zhang
Signed
v6:
- Rebase changes on top of 4ea7e9cd882f1574c129d67431784fecc426d23b
- Address comments, typos, and styling issues
- Re-factor QAT setup()/cleanup() logic
v5:
- Rebase changes on top of 59084feb256c617063e0dbe7e64821ae8852d7cf
- Add documentations about migration with qatzip accerlation
- Remov
From: Bryan Zhang
Add a 'qatzip' feature, which is automatically disabled, and which
depends on the QATzip library if enabled.
Signed-off-by: Bryan Zhang
Signed-off-by: Hao Xiang
Signed-off-by: Yichen Wang
---
meson.build | 10 ++
meson_options.txt | 2
On 15/07/2024 07:48, Philippe Mathieu-Daudé wrote:
On 14/7/24 00:42, Mark Cave-Ayland wrote:
The transfer size check was originally added to prevent consecutive DMA TI
commands from causing an assert() due to an existing SCSI request being in
progress, but since the last set of updates
[*]
On 7/15/24 17:06, Max Chou wrote:
+/* Probe nonfault on subsequent elements. */
+flags = probe_access_flags(env, addr, offset, MMU_DATA_LOAD,
+ mmu_index, true, &host, 0);
+if (flags) {
According to the sec
Capstone v6 made major changes, such as renaming for AArch64, which
broke programs using the old headers, like QEMU. However, Capstone v6
provides the CAPSTONE_AARCH64_COMPAT_HEADER compatibility definition
allowing to build against v6 with the old definitions, so fix the QEMU
build using it.
We c
Hi Phil,
On 15/7/24 23:06, Phil Dennis-Jordan wrote:
This change ensures that the MMIO write calls into the PVG
framework are performed asynchronously on a background dispatch
queue. Without this, we rapidly run into re-entrant MMIO issues.
This problem only seems to exist on x86-64 hosts. Conv
On Mon, Jul 15, 2024 at 11:45 AM Zhao Liu wrote:
>
> As the comment in qapi/error, dereferencing @errp requires
> ERRP_GUARD():
>
> * = Why, when and how to use ERRP_GUARD() =
> *
> * Without ERRP_GUARD(), use of the @errp parameter is restricted:
> * - It must not be dereferenced, because it may
From: Frederic Barrat
XIVE offers a 'cache watch facility', which allows software to read/update
a potentially cached table entry with no software lock. There's one such
facility in the Virtualization Controller (VC) to update the ESB and END
entries and one in the Presentation Controller (PC) to
From: Frederic Barrat
The cache watch facility uses the same register interface to handle
entries in the NVP, NVG and NVC tables. A bit-field in the 'watchX
specification' register tells the table type. So far, that bit-field
was not read and the code assumed a read/write to the NVP table.
This
Made changes to some structure and define elements to ease review in
next patchset.
Signed-off-by: Michael Kowal
---
hw/intc/pnv_xive2.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
index f6a735cca5
From: Nicholas Piggin
Adds support for writing a completion notification byte in memory
whenever a cache flush or queue sync inject operation is requested by
software. QEMU does not cache any of the XIVE data that is in memory and
therefore it simply writes the completion notification byte at th
From: Frederic Barrat
Set Translation Table for the NVC port space is missing. The xive model
doesn't take into account the remapping of IO operations via the Set
Translation Table but firmware is allowed to define it for the Notify
Virtual Crowd (NVC), like it's already done for the other VST t
From: Frederic Barrat
Both the virtualization layer (VC) and presentation layer (PC) need to
be configured to access the VSTs. Since the information is redundant,
the xive model combines both into one set of tables and only the
definitions going through the VC are kept. The definitions through th
From: Frederic Barrat
Fail VST entry address computation if firmware doesn't define a descriptor
for one of the Virtualization Structure Tables (VST), there's no point in
trying to compute the address of its entry. Abort the operation and log
an error.
Signed-off-by: Frederic Barrat
Signed-off
These changes provide enhanced support of the External Interrupt Virtualization
Engine. The changes are focused on the following areas:
- Cache Watch, Cache Flush and Sync Injection
- Virtual Structure Tables
- Set Translation Table
- 'info pic' command data that is dumped
Frederic Barrat (7)
From: Frederic Barrat
Enable NVG and NVC VST tables for index compression which indicates the number
of bits the address is shifted to the right for the table accesses.
The compression values are defined as:
- No compression
0001 - 1 bit shift
0010 - 2 bit shift
1000 - 8
From: Frederic Barrat
Moving xive2_nvp_pic_print_info() align with the other "pic_print_info"
functions and allows us to call functions internal to xive2.c.
In XIVE Gen 2 there were some minor changes to the TIMA header that were
updated when printed.
Additional END state 'info pic' information
Steve Sistare writes:
> Allocate anonymous memory using mmap MAP_ANON or memfd_create depending
> on the value of the anon-alloc machine property. This affects
> memory-backend-ram objects, guest RAM created with the global -m option
> but without an associated memory-backend object and without
On 7/15/2024 4:59 AM, Michael Tokarev wrote:
06.07.2024 00:50, Brian Cain wrote:
On 7/4/2024 3:47 AM, Zhao Liu wrote:
Fix the superfluous trailing semicolon in
target/hexagon/imported/mmvec/
ext.idef.
Cc: Brian Cain
Signed-off-by: Zhao Liu
Reviewed-by: Brian Cain
Brian, is it okay t
The following changes since commit 4469bee2c529832d762af4a2f89468c926f02fe4:
Merge tag 'nvme-next-pull-request' of https://gitlab.com/birkelund/qemu into
staging (2024-07-11 14:32:51 -0700)
are available in the Git repository at:
https://gitlab.com/jsnow/qemu.git tags/python-pull-request
f
Python 3.13 isn't out yet, but it's in beta and Fedora is ramping up to
make it the default system interpreter for Fedora 41.
They moved our cheese for where ContextManager lives; add a conditional
to locate it while we support both pre-3.9 and 3.13+.
Signed-off-by: John Snow
Message-id: 2024062
In general, the Use_SSI workaround is no longer needed, and neither is
the pre-1.6 logging shim for kerneldoc.
Signed-off-by: John Snow
Acked-by: Markus Armbruster
Reviewed-by: Thomas Huth
Message-id: 20240703175235.239004-3-js...@redhat.com
[rebased on top of origin/master. --js]
Signed-off-by
Python 3.13 is in beta and Fedora 41 is preparing to make it the default
system interpreter; enable testing for it.
(In the event problems develop prior to release, it should only impact
the check-python-tox job, which is not run by default and is allowed to
fail.)
Signed-off-by: John Snow
Revie
With RHEL 8 support retired (It's been two years since RHEL9 released),
our very oldest build platform version of Sphinx is now 3.4.3; and
keeping backwards compatibility for versions as old as v1.6 when using
domain extensions is a lot of work we don't need to do.
This patch is motivated by my wo
New bleeding edge versions, new nits to iron out. This addresses the
'check-python-tox' optional GitLab test, while 'check-python-minreqs'
saw no regressions, since it's frozen on an older version of pylint.
Fixes:
qemu/machine/machine.py:345:52: E0606: Possibly using variable 'sock' before
assig
There is a bug in this version,
see: https://github.com/pylint-dev/pylint/issues/9751
Signed-off-by: John Snow
Reviewed-by: Alex Bennée
Message-id: 20240626232230.408004-3-js...@redhat.com
Signed-off-by: John Snow
---
python/setup.cfg | 1 +
1 file changed, 1 insertion(+)
diff --git a/python/
Add basic ACPI table test case for RISC-V.
Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
Reviewed-by: Igor Mammedov
---
tests/qtest/bios-tables-test.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tabl
The requirement ACPI_060 in the RISC-V BRS specification [1], requires
NS16550 compatible UART to have the HID RSCV0003. So, update the HID for
the UART.
[1] - https://github.com/riscv-non-isa/riscv-brs/commits/main/acpi.adoc
(commit: 7bfa87e86ad5658283731207dbfc8ab3744d3265)
Signed-off-by:
so that CI tests don't fail when those ACPI tables are updated in the
next patch. This is as per the documentation in bios-tables-tests.c.
Signed-off-by: Sunil V L
Reviewed-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 6 ++
1 file changed, 6 insertions(+)
diff --git
As per process documented (steps 1-3) in bios-tables-test.c, add empty
AML data files for RISC-V ACPI tables and add the entries in
bios-tables-test-allowed-diff.h.
Signed-off-by: Sunil V L
Acked-by: Alistair Francis
Reviewed-by: Igor Mammedov
---
tests/data/acpi/riscv64/virt/APIC |
Currently, PCI link devices (PNP0C0F) are always created within the
scope of the PCI root bridge. However, RISC-V needs these link devices
to be created outside to ensure the probing order in the OS. This
matches the example given in the ACPI specification [1] as well. Hence,
create these link devi
This series adds few updates to RISC-V ACPI namespace for virt platform.
Additionally, it has patches to enable ACPI table testing for RISC-V.
1) PCI Link devices need to be created outside the scope of the PCI root
complex to ensure correct probe ordering by the OS. This matches the
example given
After PCI link devices are moved out of the scope of PCI root complex,
the DSDT files of machines which use GPEX, will change. So, update the
expected AML files with these changes for these machines.
Mainly, there are 2 changes.
1) Since the link devices are created now directly under _SB for all
As per the requirement ACPI_080 in the RISC-V Boot and Runtime Services
(BRS) specification [1], PLIC and APLIC should be in namespace as well.
So, add them using the defined HID.
[1] - https://github.com/riscv-non-isa/riscv-brs/blob/main/acpi.adoc
(commit : 241575b3189c5d9e60b5e55e78cf0443
The expected ACPI AML files are moved now under ${arch}/{machine} path.
Hence, there is no need to search in old path which didn't have ${arch}.
Remove the code which searches for the expected AML files under old path
as well.
Suggested-by: Igor Mammedov
Signed-off-by: Sunil V L
Acked-by: Alista
As per the step 5 in the process documented in bios-tables-test.c,
generate the expected ACPI AML data files for RISC-V using the
rebuild-expected-aml.sh script and update the
bios-tables-test-allowed-diff.h.
These are all new files being added for the first time. Hence, iASL diff
output is not ad
On 7/12/24 1:23 AM, Markus Armbruster wrote:
> Collin Walling writes:
>
>> It is beneficial to provide an interface to retrieve *all* deprecated
>> features in one go. Management applications will need this information
>> to determine which features need to be disabled regardless of the
>> host-m
Yichen Wang writes:
> On Fri, Jul 12, 2024 at 7:17 AM Fabiano Rosas wrote:
>>
>> Yichen Wang writes:
>>
>> > From: Bryan Zhang
>> >
>> > Adds support for 'qatzip' as an option for the multifd compression
>> > method parameter, and implements using QAT for 'qatzip' compression and
>> > decompre
On Mon, Jul 15, 2024 at 03:57:42PM +, Liu, Yuan1 wrote:
> > > > > > > > that is 23% total CPU usage savings.
> > > > > > >
> > > > > > >
> > > > > > > Here the DSA was mostly idle.
> > > > > > >
> > > > > > > Sounds good but a question: what if several qemu instances are
> > > > > > > migrated
On Mon, Jul 15, 2024 at 03:23:13PM +, Liu, Yuan1 wrote:
> > -Original Message-
> > From: Michael S. Tsirkin
> > Sent: Monday, July 15, 2024 10:43 PM
> > To: Liu, Yuan1
> > Cc: Wang, Yichen ; Paolo Bonzini
> > ; Marc-André Lureau ;
> > Daniel P. Berrangé ; Thomas Huth ;
> > Philippe Ma
On 7/11/24 5:10 PM, David Hildenbrand wrote:
> On 11.07.24 22:32, Collin Walling wrote:
>> It is beneficial to provide an interface to retrieve *all* deprecated
>> features in one go. Management applications will need this information
>> to determine which features need to be disabled regardless of
> -Original Message-
> From: Liu, Yuan1
> Sent: Monday, July 15, 2024 11:23 PM
> To: Michael S. Tsirkin
> Cc: Wang, Yichen ; Paolo Bonzini
> ; Marc-André Lureau ;
> Daniel P. Berrangé ; Thomas Huth ;
> Philippe Mathieu-Daudé ; Peter Xu ;
> Fabiano Rosas ; Eric Blake ; Markus
> Armbruster ;
On 4/7/24 05:37, Bibo Mao wrote:
Loongson ipi common class and instance is created here, it comes
from file loongson_ipi mostly. For the new added loongson ipi
common class, there is four interfaces defined here:
1. Interfaces pre_save/post_load are used for future kvm child class
2. Interfac
> -Original Message-
> From: Michael S. Tsirkin
> Sent: Monday, July 15, 2024 10:43 PM
> To: Liu, Yuan1
> Cc: Wang, Yichen ; Paolo Bonzini
> ; Marc-André Lureau ;
> Daniel P. Berrangé ; Thomas Huth ;
> Philippe Mathieu-Daudé ; Peter Xu ;
> Fabiano Rosas ; Eric Blake ; Markus
> Armbruster
On 4/7/24 05:37, Bibo Mao wrote:
Now loongson ipi and loongarch ipi share the same code with different
macro, loongson ipi has its separate function such mmio region,
loongarch ipi has other requirement such as irqchip in kernel.
Interrupt irqchip has strong relationship with architecture, since
On Mon, 15 Jul 2024 14:19:12 +
Salil Mehta wrote:
> > From: qemu-arm-bounces+salil.mehta=huawei@nongnu.org > arm-bounces+salil.mehta=huawei@nongnu.org> On Behalf Of Salil
> > Mehta via
> > Sent: Monday, July 15, 2024 3:14 PM
> > To: Igor Mammedov
> >
> > Hi Igor,
> >
> >
> -Original Message-
> From: Yichen Wang
> Sent: Friday, July 12, 2024 5:53 AM
> To: Paolo Bonzini ; Marc-André Lureau
> ; Daniel P. Berrangé ;
> Thomas Huth ; Philippe Mathieu-Daudé
> ; Peter Xu ; Fabiano Rosas
> ; Eric Blake ; Markus Armbruster
> ; Michael S. Tsirkin ; Cornelia Huck
> ;
On Fri, 12 Jul 2024 12:08:14 +0100
Jonathan Cameron wrote:
> These are very similar to the recently added Generic Initiators
> but instead of representing an initiator of memory traffic they
> represent an edge point beyond which may lie either targets or
> initiators. Here we add these ports su
On Mon, Jul 15, 2024 at 01:09:59PM +, Liu, Yuan1 wrote:
> > -Original Message-
> > From: Michael S. Tsirkin
> > Sent: Monday, July 15, 2024 8:24 PM
> > To: Liu, Yuan1
> > Cc: Wang, Yichen ; Paolo Bonzini
> > ; Marc-André Lureau ;
> > Daniel P. Berrangé ; Thomas Huth ;
> > Philippe Mat
On Fri, 12 Jul 2024 12:08:13 +0100
Jonathan Cameron wrote:
> Reduce the direct use of PCI internals inside ACPI table creation.
>
> Suggested-by: Igor Mammedov
> Tested-by: "Huang, Ying"
> Signed-off-by: Jonathan Cameron
Reviewed-by: Igor Mammedov
> ---
> v5: Similar to previous, use bus n
On Fri, 12 Jul 2024 12:08:12 +0100
Jonathan Cameron wrote:
> Rather than relying on PCI internals, use the new acpi_property
> to obtain the ACPI _UID values. These are still the same
> as the PCI Bus numbers so no functional change.
>
> Suggested-by: Igor Mammedov
> Tested-by: "Huang, Ying"
On Fri, 12 Jul 2024 12:08:11 +0100
Jonathan Cameron wrote:
> Enable ACPI table creation for PCI Expander Bridges to be independent
> of PCI internals. Note that the UID is currently the PCI bus number.
> This is motivated by the forthcoming ACPI Generic Port SRAT entries
> which can be made comp
On Fri, 12 Jul 2024 12:08:10 +0100
Jonathan Cameron wrote:
> Whilst ACPI SRAT Generic Initiator Afinity Structures are able to refer to
> both PCI and ACPI Device Handles, the QEMU implementation only implements
> the PCI Device Handle case. For now move the code into the existing
> hw/acpi/pci.
On Fri, 12 Jul 2024 12:08:10 +0100
Jonathan Cameron wrote:
> Whilst ACPI SRAT Generic Initiator Afinity Structures are able to refer to
> both PCI and ACPI Device Handles, the QEMU implementation only implements
> the PCI Device Handle case. For now move the code into the existing
> hw/acpi/pci.
> From: qemu-arm-bounces+salil.mehta=huawei@nongnu.org arm-bounces+salil.mehta=huawei@nongnu.org> On Behalf Of Salil
> Mehta via
> Sent: Monday, July 15, 2024 3:14 PM
> To: Igor Mammedov
>
> Hi Igor,
>
> > From: Igor Mammedov
> > Sent: Monday, July 15, 2024 2:55 PM
> > To
Hi Igor,
> From: Igor Mammedov
> Sent: Monday, July 15, 2024 2:55 PM
> To: Salil Mehta
>
> On Sat, 13 Jul 2024 19:25:09 +0100
> Salil Mehta wrote:
>
> > [Note: References are present at the last after the revision history]
> >
> > Virtual CPU hotplug support is being added across va
On Mon, 15 Jul 2024 16:21:53 +0800
Zhao Liu wrote:
> For qemu_open_old(), osdep.h said:
>
> > Don't introduce new usage of this function, prefer the following
> > qemu_open/qemu_create that take an "Error **errp".
>
> So replace qemu_open_old() with qemu_open().
>
> Cc: David Hildenbrand
>
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