On 15/7/24 07:25, Akihiko Odaki wrote:
CGImageCreate | Apple Developer Documentation
https://developer.apple.com/documentation/coregraphics/1455149-cgimagecreate
The color space is retained; on return, you may safely release it.
Signed-off-by: Akihiko Odaki
Tested-by: Phil Dennis-Jordan
---
On 15/7/24 07:25, Akihiko Odaki wrote:
Reviewed-by: Marc-André Lureau
Tested-by: Phil Dennis-Jordan
Signed-off-by: Akihiko Odaki
---
include/ui/console.h| 4 ++--
hw/display/ati.c| 2 +-
hw/display/virtio-gpu.c | 3 +--
hw/display/vmware_vga.c | 2 +-
ui/console.c
On 14/7/24 00:42, Mark Cave-Ayland wrote:
The transfer size check was originally added to prevent consecutive DMA TI
commands from causing an assert() due to an existing SCSI request being in
progress, but since the last set of updates
[*]
this is no longer required.
Remove the transfer size
On 15/7/24 07:58, Richard Henderson wrote:
From: Daniyal Khan
We made a copy above because the fp exception flags
are not propagated back to the FPST register, but
then failed to use the copy.
Cc: qemu-sta...@nongnu.org
Fixes: 558e956c719 ("target/arm: Implement FMOPA, FMOPS (non-widening)")
S
On Sat Jul 13, 2024 at 5:24 PM AEST, Cédric Le Goater wrote:
> On 7/12/24 14:02, Nicholas Piggin wrote:
> > Big-core implementation is complete, so expose it as a machine
> > property that may be set with big-core=on option on powernv9 and
> > powernv10 machines.
> >
> > Signed-off-by: Nicholas Pi
On Sat Jul 13, 2024 at 5:19 PM AEST, Cédric Le Goater wrote:
> On 7/12/24 14:02, Nicholas Piggin wrote:
> > POWER9 and POWER10 machines come in two variants, big-core and
> > small-core. Big-core machines are SMT8 from software's point of view,
> > but the low level platform topology ("xscom regist
On Fri Jul 12, 2024 at 11:40 PM AEST, Cédric Le Goater wrote:
> On 7/12/24 14:02, Nicholas Piggin wrote:
> > diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c
> > index 39d397416e..52f9e6669c 100644
> > --- a/target/ppc/timebase_helper.c
> > +++ b/target/ppc/timebase_helper.c
On 7/15/24 22:58, Richard Henderson wrote:
This operation has float16 inputs and thus must use
the FZ16 control not the FZ control.
Cc: qemu-sta...@nongnu.org
Reported-by: Daniyal Khan
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2374
Signed-off-by: Richard Henderson
---
target/ar
Hi Daniyal,
Your fix for sme_fmopa_s is correct, but not the FZ16 fix.
We represent FZ16 with a separate float_status structure,
so all that is needed is to use that.
Thanks for the test cases. I cleaned them up a little,
and wired them into the Makefile.
r~
Supercedes: 172090222034.13953.168
This operation has float16 inputs and thus must use
the FZ16 control not the FZ control.
Cc: qemu-sta...@nongnu.org
Reported-by: Daniyal Khan
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2374
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-sme.c | 12
1 fil
From: Daniyal Khan
We made a copy above because the fp exception flags
are not propagated back to the FPST register, but
then failed to use the copy.
Cc: qemu-sta...@nongnu.org
Fixes: 558e956c719 ("target/arm: Implement FMOPA, FMOPS (non-widening)")
Signed-off-by: Daniyal Khan
[rth: Split from
From: Daniyal Khan
Signed-off-by: Daniyal Khan
Message-Id: 172090222034.13953.1688870870882292209...@git.sr.ht
[rth: Split test cases to separate patch, tidy assembly.]
Signed-off-by: Richard Henderson
---
tests/tcg/aarch64/sme-fmopa-1.c | 63 +++
tests/tcg/aarch6
Hi Salil,
I ran the unit tests again on x86 platform, and everything looks good.
Please feel free to keep my tested-by tag.
Regards,
Zhao
On Sat, Jul 13, 2024 at 07:25:09PM +0100, Salil Mehta via wrote:
> Date: Sat, 13 Jul 2024 19:25:09 +0100
> From: Salil Mehta via
> Subject: [PATCH V15 0/7]
From: Maxim Mikityanskiy
qemu_chr_open_fd() sets stdout into non-blocking mode. Restore the old
fd flags on exit to avoid breaking unsuspecting applications that run on
the same terminal after qemu and don't expect to get EAGAIN.
While at at, also ensure term_exit is called once (at the moment i
From: Stefano Garzarella
Commit d152cdd6f6 ("virtio: use virtio accessor to access packed event")
switched using of address_space_read_cached() to virito_lduw_phys_cached()
to access packed descriptor event.
When we used address_space_read_cached(), we needed to call
virtio_tswap16s() to handle
The following patches are queued for QEMU stable v7.2.13:
https://gitlab.com/qemu-project/qemu/-/commits/staging-7.2
Patch freeze is 2024-07-14 (frozen), and the release is planned for 2024-07-16:
https://wiki.qemu.org/Planning/7.2
Please respond here or CC qemu-sta...@nongnu.org on any add
On 2024/07/07 5:43, Phil Dennis-Jordan wrote:
This reduces the incidental complexity of the screen update draw and
cursor conversion functions and minimally reduces overall code size.
Signed-off-by: Phil Dennis-Jordan
---
ui/cocoa.m | 85 +++---
Remove dpy_cursor_define_supported() as it brings no benefit today and
it has a few inherent problems.
All graphical displays except egl-headless support cursor composition
without DMA-BUF, and egl-headless is meant to be used in conjunction
with another graphical display, so dpy_cursor_define_sup
Reviewed-by: Marc-André Lureau
Tested-by: Phil Dennis-Jordan
Signed-off-by: Akihiko Odaki
---
include/ui/console.h| 4 ++--
hw/display/ati.c| 2 +-
hw/display/virtio-gpu.c | 3 +--
hw/display/vmware_vga.c | 2 +-
ui/console.c| 5 +++--
ui/dbus-listener.c | 2 +
Add accelerated cursor composition to ui/cocoa. This does not only
improve performance for display devices that exposes the capability to
the guest according to dpy_cursor_define_supported(), but fixes the
cursor display for devices that unconditionally expects the availability
of the capability (e
Add accelerated cursor composition to ui/cocoa. This does not only
improve performance for display devices that exposes the capability to
the guest according to dpy_cursor_define_supported(), but fixes the
cursor display for devices that unconditionally expects the availability
of the capability (e
CGImageCreate | Apple Developer Documentation
https://developer.apple.com/documentation/coregraphics/1455149-cgimagecreate
> The color space is retained; on return, you may safely release it.
Signed-off-by: Akihiko Odaki
Tested-by: Phil Dennis-Jordan
---
ui/cocoa.m | 5 -
1 file changed, 4
A virtio-net device can be added as a SR-IOV VF to another virtio-pci
device that will be the PF.
Signed-off-by: Akihiko Odaki
---
hw/virtio/virtio-net-pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/virtio/virtio-net-pci.c b/hw/virtio/virtio-net-pci.c
index e03543a70a75..dba4987d6e
Allow user to attach SR-IOV VF to a virtio-pci PF.
Signed-off-by: Akihiko Odaki
---
include/hw/virtio/virtio-pci.h | 1 +
hw/virtio/virtio-pci.c | 20 +++-
2 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/include/hw/virtio/virtio-pci.h b/include/hw/virtio/
Signed-off-by: Akihiko Odaki
---
MAINTAINERS | 1 +
docs/system/index.rst | 1 +
docs/system/sriov.rst | 36
3 files changed, 38 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6725913c8b3a..ca0222e5528b 100644
--- a/MAINTAINERS
+++ b/M
A user can create a SR-IOV device by specifying the PF with the
sriov-pf property of the VFs. The VFs must be added before the PF.
A user-creatable VF must have PCIDeviceClass::sriov_vf_user_creatable
set. Such a VF cannot refer to the PF because it is created before the
PF.
A PF that user-creata
pci_config_get_bar_addr() had a division by vf_stride. vf_stride needs
to be non-zero when there are multiple VFs, but the specification does
not prohibit to make it zero when there is only one VF.
Do not perform the division for the first VF to avoid division by zero.
Signed-off-by: Akihiko Odak
A device cannot be a SR-IOV PF and a VF at the same time.
Signed-off-by: Akihiko Odaki
---
hw/pci/pcie_sriov.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c
index 56523ab4e833..ec8fc0757b92 100644
--- a/hw/pci/pcie_sriov.c
+++ b/hw/pci/pcie_sr
SR-IOV requires PCI Express.
Signed-off-by: Akihiko Odaki
---
hw/pci/pcie_sriov.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c
index ec8fc0757b92..3af0cc7d560a 100644
--- a/hw/pci/pcie_sriov.c
+++ b/hw/pci/pcie_sriov.c
@@ -42,6 +42,11 @@ bool
Based-on: <20240714-rombar-v2-0-af1504ef5...@daynix.com>
("[PATCH v2 0/4] hw/pci: Convert rom_bar into OnOffAuto")
Introduction
This series is based on the RFC series submitted by Yui Washizu[1].
See also [2] for the context.
This series enables SR-IOV emulation fo
A SR-IOV VF cannot have a ROM BAR.
Co-developed-by: Yui Washizu
Signed-off-by: Akihiko Odaki
---
hw/pci/pci.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index ca8fb5383765..497a057b79f9 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -2412,6 +2412,14
On 2024/05/16 11:00, Yui Washizu wrote:
On 2024/04/28 18:05, Akihiko Odaki wrote:
Based-on: <20240315-reuse-v9-0-67aa69af4...@daynix.com>
("[PATCH for 9.1 v9 00/11] hw/pci: SR-IOV related fixes and
improvements")
Introduction
This series is based on the RFC series submitted by
These 2 MSRs have been already defined in kvm_para.h (standard-headers/
asm-x86/kvm_para.h).
Remove QEMU local definitions to avoid duplication.
Reviewed-by: Xiaoyao Li
Signed-off-by: Zhao Liu
---
target/i386/kvm/kvm.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/target/i386/kvm/kvm.c
Currently, there're following incorrect error handling cases in
kvm_arch_init():
* Missed to handle failure of kvm_get_supported_feature_msrs().
* Missed to return when KVM_CAP_X86_DISABLE_EXITS enabling fails.
* MSR filter related cases called exit() directly instead of returning
to kvm_init().
MSR_KVM_SYSTEM_TIME_NEW and MSR_KVM_WALL_CLOCK_NEW are bound to
kvmclock2 (KVM_FEATURE_CLOCKSOURCE2).
Add the save/load support for these 2 MSRs just like kvmclock MSRs.
Signed-off-by: Zhao Liu
---
target/i386/cpu.h | 2 ++
target/i386/kvm/kvm.c | 16
2 files changed, 18 i
Update the comment to match the X86ConfidentialGuestClass
implementation.
Reported-by: Xiaoyao Li
Signed-off-by: Zhao Liu
Reviewed-by: Pankaj Gupta
---
target/i386/confidential-guest.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/confidential-guest.h b/target
The KVM_X86_DISABLE_EXITS_HTL typo has been fixed in commit
77d361b13c19 ("linux-headers: Update to kernel mainline commit
b357bf602").
Drop the related workaround.
Signed-off-by: Zhao Liu
---
target/i386/kvm/kvm.c | 4
1 file changed, 4 deletions(-)
diff --git a/target/i386/kvm/kvm.c b/t
MSR_KVM_SYSTEM_TIME and MSR_KVM_WALL_CLOCK are attached with the (old)
kvmclock feature (KVM_FEATURE_CLOCKSOURCE).
So, just save/load them only when kvmclock (KVM_FEATURE_CLOCKSOURCE) is
enabled.
Signed-off-by: Zhao Liu
---
target/i386/kvm/kvm.c | 12
1 file changed, 8 insertions(+
Add feature definitions for KVM_CPUID_FEATURES in CPUID (
CPUID[4000_0001].EAX and CPUID[4000_0001].EDX), to get rid of lots of
offset calculations.
Signed-off-by: Zhao Liu
---
v3: Resolved a rebasing conflict.
v2: Changed the prefix from CPUID_FEAT_KVM_* to CPUID_KVM_*. (Xiaoyao)
---
hw/i386/kv
Hi,
This is my v3 cleanup series. Compared with v2 [1],
* v3 resolved the rebasing conflict (now based on 37fbfda8f414).
* Added 2 more patches (patch 7&8) to clean up error handling in
kvm_arch_init().
Background and Introduction
===
This series picks cleanup from
At present, the error code of MSR filter enablement is attempted to be
printed in error_report().
Unfortunately, this behavior doesn't work because the MSR filter-related
functions return the boolean and current error_report() use the wrong
return value.
So fix this by making MSR filter related f
On Fri, Jul 12, 2024 at 1:48 PM Michael S. Tsirkin wrote:
>
> On Fri, Jul 12, 2024 at 11:06:49AM +0900, David Stevens wrote:
> > On Thu, Jul 11, 2024 at 7:56 PM Alyssa Ross wrote:
> > >
> > > Adding David Stevens, who implemented SHMEM_MAP and SHMEM_UNMAP in
> > > crosvm a couple of years ago.
>
in the Git repository at:
https://gitlab.com/jeuk20.kim/qemu.git tags/pull-ufs-20240714
for you to fetch changes up to 50475f1511964775ff73c2b07239c3ff571f75cd:
hw/ufs: Fix mcq register range check logic (2024-07-14 17:11:21 +0900)
-
On 2024/7/12 17:57, Daniel Henrique Barboza wrote:
On 7/9/24 11:24 PM, LIU Zhiwei wrote:
From: 甲一
This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus
qemu-system-riscv64 can directly boot a RV32 Linux.
This patch set has been tested with 6.9.0 Linux Image.
And add an avocad
On 2024/7/12 17:52, Daniel Henrique Barboza wrote:
On 7/9/24 11:24 PM, LIU Zhiwei wrote:
From: TANG Tiancheng
To regularly test booting Linux with rv32 on QEMU RV64,
we have added a test to boot_linux_console.py to retrieve
cpuinfo and verify if it shows 'rv32' when using RV64 to
boot rv32
On Fri, Jul 12, 2024 at 8:33 AM Atish Patra wrote:
>
> This patch series adds the support for RISC-V ISA extension smcntrpmf (cycle
> and
> privilege mode filtering) [1]. It is based on Kevin's earlier work but
> improves
> it by actually implement privilege mode filtering by tracking the privil
On Fri, Jul 12, 2024 at 8:34 AM Atish Patra wrote:
>
> Create a new config for Smcntrpmf extension so that it can be enabled/
> disabled from the qemu commandline.
>
> Signed-off-by: Atish Patra
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 1 +
> 1 file changed, 1 inserti
From: Yu-Ming Chang
Both CSRRS and CSRRC always read the addressed CSR and cause any read side
effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
holding a zero value other than x0, the instruction will still attempt to write
the unmodified value back to the CSR and wi
On Fri, Jul 12, 2024 at 8:34 AM Atish Patra wrote:
>
> Currently, the INH fields are set in mhpmevent uncoditionally
> without checking if a particular priv mode is supported or not.
>
> Suggested-by: Alistair Francis
> Signed-off-by: Atish Patra
Thanks!
Acked-by: Alistair Francis
Alistair
On Fri, Jul 12, 2024 at 8:34 AM Atish Patra wrote:
>
> From: Kaiwen Xue
>
> QEMU only calculates dummy cycles and instructions, so there is no
> actual means to stop the icount in QEMU. Hence this patch merely adds
> the functionality of accessing the cfg registers, and cause no actual
> effects
On Fri, Jul 12, 2024 at 8:33 AM Atish Patra wrote:
>
> From: Kaiwen Xue
>
> This adds the properties for ISA extension smcntrpmf. Patches
> implementing it will follow.
>
> Signed-off-by: Kaiwen Xue
> Reviewed-by: Daniel Henrique Barboza
> Signed-off-by: Atish Patra
Reviewed-by: Alistair Fran
On Sun, Jul 14, 2024 at 3:44 AM Daniel Henrique Barboza
wrote:
>
> Commit b1f1e9dcfa renamed 'riscv,delegate' to 'riscv,delegation' since
> it is the correct name as per dt-bindings, and the absence of the
> correct name will result in validation fails when dumping the dtb and
> using dt-validate.
On Sun, Jul 14, 2024 at 3:44 AM Daniel Henrique Barboza
wrote:
>
> Commit b1f1e9dcfa renamed 'riscv,delegate' to 'riscv,delegation' since
> it is the correct name as per dt-bindings, and the absence of the
> correct name will result in validation fails when dumping the dtb and
> using dt-validate.
On 7/14/24 04:10, Paolo Bonzini wrote:
The following changes since commit 23901b2b721c0576007ab7580da8aa855d6042a9:
Merge tag 'pull-target-arm-20240711' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-07-11
12:00:00 -0700)
are available in the Git repository at:
h
https://wiki.qemu.org/Planning/9.1
Just a friendly reminder that soft freeze is coming up soon.
r~
From: Richard Henderson
This truncation is now handled by MMU_*32_IDX. The introduction of
MMU_*32_IDX in fact applied correct 32-bit wraparound to 16-bit accesses
with a high segment base (e.g. big real mode or vm86 mode), which did
not use SEG_ADDL.
Signed-off-by: Richard Henderson
Link:
h
This fixes a bug wherein i386/tcg assumed an interrupt return using
the IRET instruction was always returning from kernel mode to either
kernel mode or user mode. This assumption is violated when IRET is used
as a clever way to restore thread state, as for example in the dotnet
runtime. There, IRET
This takes care of probing the vaddr range in advance, and is also faster
because it avoids repeated TLB lookups. It also matches the Intel manual
better, as it says "Checks that the current (old) TSS, new TSS, and all
segment descriptors used in the task switch are paged into system memory";
note
From: Michael Roth
Currently if the 'legacy-vm-type' property of the sev-guest object is
'on', QEMU will attempt to use the newer KVM_SEV_INIT2 kernel
interface in conjunction with the newer KVM_X86_SEV_VM and
KVM_X86_SEV_ES_VM KVM VM types.
This can lead to measurement changes if, for instance,
This is how the steps are ordered in the manual. EFLAGS.NT is
overwritten after the fact in the saved image.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/seg_helper.c | 85 +++-
1 file changed, 45 insertions(+), 40 deletions(-)
The following changes since commit 23901b2b721c0576007ab7580da8aa855d6042a9:
Merge tag 'pull-target-arm-20240711' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-07-11
12:00:00 -0700)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for
From: Richard Henderson
Disconnect mmu index computation from the current pl
as stored in env->hflags.
Signed-off-by: Richard Henderson
Link:
https://lore.kernel.org/r/20240617161210.4639-2-richard.hender...@linaro.org
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.h | 11 ++-
targ
From: Richard Henderson
Interrupts and call gates should use accesses with the DPL as
the privilege level. While computing the applicable MMU index
is easy, the harder thing is how to plumb it in the code.
One possibility could be to add a single argument to the PUSH* macros
for the privilege l
Add the MMU index to the StackAccess struct, so that it can be cached
or (in the next patch) computed from information that is not in
CPUX86State.
Co-developed-by: Richard Henderson
Signed-off-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/seg_helper.c | 35
From: Sergey Dyasli
This reverts commit 2b316774f60291f57ca9ecb6a9f0712c532cae34.
After 038b4217884c ("Revert "chardev: use a child source for qio input
source"") we've been observing the "iwp->src == NULL" assertion
triggering periodically during the initial capabilities querying by
libvirtd. O
This fixes a bug wherein i386/tcg assumed an interrupt return using
the CALL or JMP instructions were always going from kernel or user mode to
kernel mode, when using a call gate. This assumption is violated if
the call gate has a DPL that is greater than 0.
In addition, the stack accesses should
This step is listed in the Intel manual: "Checks that the new task is available
(call, jump, exception, or interrupt) or busy (IRET return)".
The AMD manual lists the same operation under the "Preventing recursion"
paragraph of "12.3.4 Nesting Tasks", though it is not clear if the processor
checks
In long mode, POP to memory will write a full 64-bit value. However,
the call to gen_writeback() in gen_POP will use MO_32 because the
decoding table is incorrect.
The bug was latent until commit aea49fbb01a ("target/i386: use gen_writeback()
within gen_POP()", 2024-06-08), and then became visibl
Do not pre-decrement esp, let the macros subtract the appropriate
operand size.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/seg_helper.c | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/target/i386/tcg/seg_helper.c b/target
cpu);
g_array_free(cpu->gdb_regs, TRUE);
qemu_lockcnt_destroy(&cpu->in_ioctl_lock);
qemu_mutex_destroy(&cpu->work_mutex);
---
base-commit: f2cb4026fccfe073f84a4b440e41d3ed0c3134f6
change-id: 20240714-cpu-c4d28823b4c2
Best regards,
--
Akihiko Odaki
upported_features), FALSE);
}
}
---
base-commit: f2cb4026fccfe073f84a4b440e41d3ed0c3134f6
change-id: 20240714-arm-045665f1c2ef
Best regards,
--
Akihiko Odaki
-extra-cflags=-fno-sanitize-recover=undefined
- --extra-cflags=-fno-sanitize=function
TARGETS: alpha-softmmu arm-softmmu m68k-softmmu mips64-softmmu
s390x-softmmu
MAKE_CHECK_ARGS: check-qtest check-tcg
---
base-commit: f2cb4026fccfe073f84a4b440e41d3ed0c3134f6
change-id: 20240714-
From: Jeuk Kim
The function ufs_is_mcq_reg() and ufs_is_mcq_op_reg() only evaluated
the range of the mcq_reg and mcq_op_reg offset, which is defined as
a constant. Therefore, it was possible for them to return true
even though the ufs device is configured to not support the mcq.
This could cause
gitlab.com/jeuk20.kim/qemu.git tags/pull-ufs-20240714
for you to fetch changes up to 50475f1511964775ff73c2b07239c3ff571f75cd:
hw/ufs: Fix mcq register range check logic (2024-07-14 17:11:21 +0900)
hw/ufs:
- Fix invalid address acc
Consuming a value when visit_type_enum() fails makes it impossible to
reinterpret the value with a different type.
Signed-off-by: Akihiko Odaki
---
include/qapi/visitor.h | 5 -
qapi/opts-visitor.c| 5 -
qapi/qapi-visit-core.c | 4 +++-
3 files changed, 3 insertions(+), 11 deletions(
rom_bar is tristate but was defined as uint32_t so convert it into
OnOffAuto to clarify that. For compatibility, a uint32 value set via
QOM will be converted into OnOffAuto.
Signed-off-by: Akihiko Odaki
---
docs/about/deprecated.rst | 7 +
docs/igd-assign.txt | 2 +-
It is no longer used.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Markus Armbruster
---
include/hw/qdev-core.h | 4
hw/core/qdev.c | 1 -
system/qdev-monitor.c | 12 +++-
3 files changed, 7 insertions(+), 10 deletions(-)
diff --git a/i
visit_type_str_preserving() is mostly indentical with visit_type_str()
but leaves the value intact. This is useful when the caller may
interpret the value with a different type.
Signed-off-by: Akihiko Odaki
---
include/qapi/visitor-impl.h | 3 ++-
include/qapi/visitor.h| 20 ++
rom_bar is tristate but was defined as uint32_t so convert it into
OnOffAuto to clarify that. For compatibility, a uint32 value set via
QOM will be converted into OnOffAuto.
Signed-off-by: Akihiko Odaki
---
Changes in v2:
- Documented in docs/about/deprecated.rst (Daniel P. Berrangé)
- Link to v1
On Fri, Jul 12, 2024 at 03:50:10PM +0200, Igor Mammedov wrote:
> On Fri, 12 Jul 2024 13:51:04 +0100
> Daniel P. Berrangé wrote:
>
> > On Fri, Jul 12, 2024 at 02:43:19PM +0200, Igor Mammedov wrote:
> > > On Mon, 8 Jul 2024 17:17:32 +0530
> > > Sunil V L wrote:
> > >
> > > > This series adds f
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