On 27/6/24 06:13, Jiaxun Yang wrote:
Signed-off-by: Jiaxun Yang
---
Jiaxun Yang (2):
hw/intc/loongson_ipi: Gate MMIO regions creation with property
MAINTAINERS: Add myself as a reviewer of LoongArch virt machine
Maybe s/has-mmio/use-mmio/? Otherwise series:
Reviewed-by: Philippe
On Thu, Jun 27, 2024, 2:25 AM Markus Armbruster wrote:
> John Snow writes:
>
> > Change get_doc_indented() to preserve indentation on all subsequent text
> > lines, and create a compatibility dedent() function for qapidoc.py that
> > removes indentation the same way get_doc_indented() did.
> >
>
On 27/6/24 08:10, Philippe Mathieu-Daudé wrote:
On 27/6/24 06:13, Gustavo Romero wrote:
Make the gdb_first_attached_cpu and gdb_hextomem non-internal so they
are not confined to use only in gdbstub.c.
Signed-off-by: Gustavo Romero
Reviewed-by: Richard Henderson
---
gdbstub/internals.h
On 26/6/24 21:49, Richard Henderson wrote:
Richard Henderson (3):
target/i386/sev: Cast id_auth_uaddr through uintptr_t
target/i386/sev: Use size_t for object sizes
target/i386/sev: Fix printf formats
Series:
Reviewed-by: Philippe Mathieu-Daudé
On Thu, Jun 27, 2024, 2:02 AM Markus Armbruster wrote:
> John Snow writes:
>
> > This function has been unused since fd62bff901b.
> >
> > Signed-off-by: John Snow
>
> Reviewed-by: Markus Armbruster
>
> I assume you won't mind me adding a bit of polish: "since commit
> fd62bff901b (sphinx/qapid
Hi, Gregor
>
> The read() syscall is not guaranteed to return all data from a file. The
> default ROM loader implementation currently does not take this into account,
> instead failing if all bytes are not read at once. This change wraps the
> read() syscall in a do/while loop to ensure all bytes
rom_bar is tristate but was defined as uint32_t so convert it into
OnOffAuto.
Signed-off-by: Akihiko Odaki
---
docs/igd-assign.txt | 2 +-
include/hw/pci/pci_device.h | 2 +-
hw/pci/pci.c | 4 ++--
hw/vfio/pci-quirks.c | 2 +-
hw/vfio/pci
pcie_sriov doesn't have code to restore its state after migration, but
igb, which uses pcie_sriov, naively claimed its migration capability.
Add code to register VFs after migration and fix igb migration.
Fixes: 3a977deebe6b ("Intrdocue igb device emulation")
Signed-off-by: Akihiko Odaki
---
in
On 27/6/24 06:13, Gustavo Romero wrote:
Make the gdb_first_attached_cpu and gdb_hextomem non-internal so they
are not confined to use only in gdbstub.c.
Signed-off-by: Gustavo Romero
Reviewed-by: Richard Henderson
---
gdbstub/internals.h| 2 --
include/exec/gdbstub.h | 5 +
pci_new() aborts when creating a VF with a function number equals to or
is greater than PCI_DEVFN_MAX.
Signed-off-by: Akihiko Odaki
---
docs/pcie_sriov.txt | 8 +---
include/hw/pci/pcie_sriov.h | 5 +++--
hw/net/igb.c| 13 ++---
hw/nvme/ctrl.c |
It is no longer used.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Markus Armbruster
---
include/hw/qdev-core.h | 4
hw/core/qdev.c | 1 -
system/qdev-monitor.c | 12 +++-
3 files changed, 7 insertions(+), 10 deletions(-)
diff --git a/i
romsize is an uint32_t variable. Specifying -1 as an uint32_t value is
obscure way to denote UINT32_MAX.
Worse, if int is wider than 32-bit, it will change the behavior of a
construct like the following:
romsize = -1;
if (romsize != -1) {
...
}
When -1 is assigned to romsize, -1 will be impli
The renamed state will not only represent powering state of PFs, but
also represent SR-IOV VF enablement in the future.
Signed-off-by: Akihiko Odaki
---
include/hw/pci/pci.h| 7 ++-
include/hw/pci/pci_device.h | 2 +-
hw/pci/pci.c| 14 +++---
hw/pci/pci_host
num_vfs is not migrated so use PCI_SRIOV_CTRL_VFE and PCI_SRIOV_NUM_VF
instead.
Signed-off-by: Akihiko Odaki
---
include/hw/pci/pcie_sriov.h | 1 -
hw/pci/pcie_sriov.c | 28
hw/pci/trace-events | 2 +-
3 files changed, 21 insertions(+), 10 deletions
Release VFs failed to realize just as we do in unregister_vfs().
Fixes: 7c0fa8dff811 ("pcie: Add support for Single Root I/O Virtualization
(SR/IOV)")
Signed-off-by: Akihiko Odaki
---
hw/pci/pcie_sriov.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sri
A device gets automatically unrealized when being unparented.
Signed-off-by: Akihiko Odaki
---
hw/pci/pcie_sriov.c | 4
1 file changed, 4 deletions(-)
diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c
index e9b23221d713..499becd5273f 100644
--- a/hw/pci/pcie_sriov.c
+++ b/hw/pci/pcie_
Disabled means it is a disabled SR-IOV VF or it is powered off, and
hidden from the guest.
Signed-off-by: Akihiko Odaki
---
hw/ppc/spapr_pci.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index 7cf9904c3546..f63182a03c41 100644
--- a/hw/ppc/spap
A PF may automatically create VFs and the PF may be function 0.
Signed-off-by: Akihiko Odaki
---
hw/ppc/spapr_pci.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index f63182a03c41..ed4454bbf79e 100644
--- a/hw/ppc/spapr_pci.c
+++
Disable SR-IOV VF devices by reusing code to power down PCI devices
instead of removing them when the guest requests to disable VFs. This
allows to realize devices and report VF realization errors at PF
realization time.
Signed-off-by: Akihiko Odaki
---
include/hw/pci/pci.h| 5 ---
incl
I submitted a RFC series[1] to add support for SR-IOV emulation to
virtio-net-pci. During the development of the series, I fixed some
trivial bugs and made improvements that I think are independently
useful. This series extracts those fixes and improvements from the RFC
series.
[1]: https://patche
On 27/6/24 06:13, Gustavo Romero wrote:
Factor out the code used for setting the MTE TCF0 field from the prctl
code into a convenient function. Other subsystems, like gdbstub, need to
set this field as well, so keep it as a separate function to avoid
duplication and ensure consistency in how this
> -Original Message-
> From: Pierrick Bouvier
> Sent: Thursday, June 27, 2024 1:29 PM
> To: Yao, Xingtao/姚 幸涛 ; qemu-devel@nongnu.org
> Cc: Alexandre Iooss ; Philippe Mathieu-Daudé
> ; Mahmoud Mandour ; Paolo
> Bonzini ; Eduardo Habkost ;
> Richard Henderson ; Alex Bennée
>
> Subject: R
On 27/6/24 06:13, Gustavo Romero wrote:
Move GdbCmdParseEntry and its associated types into a separate header
file to allow the use of GdbCmdParseEntry and other gdbstub command
functions outside of gdbstub.c.
Since GdbCmdParseEntry and get_param are now public, kdoc
GdbCmdParseEntry and rename
On 27/6/24 06:13, Gustavo Romero wrote:
Make the MTE helpers allocation_tag_mem_probe, load_tag1, and store_tag1
available to other subsystems.
Signed-off-by: Gustavo Romero
Reviewed-by: Richard Henderson
---
target/arm/tcg/mte_helper.c | 45 -
target/arm/tcg/mte_hel
Hi Xingtao,
On 6/26/24 20:17, Xingtao Yao (Fujitsu) wrote:
Hi, Pierrick
+static void print_access(unsigned int cpu_index, qemu_plugin_meminfo_t
meminfo,
+ uint64_t vaddr, void *udata)
+{
+unsigned size = 8 << qemu_plugin_mem_size_shift(meminfo);
+const char *typ
On 27/06/2024 07:08, Yuke Peng wrote:
On Wed, Jun 26, 2024 at 2:15 PM cmd
wrote:
Hi,
On 25/06/2024 13:28, Yuke Peng wrote:
> According to Intel VT-d specification 5.1.4, CFI must be blocked
when
> Extended Interrupt Mode is enabled or Compatibility format
interrupts
On Wed, Jun 26, 2024 at 2:15 PM cmd
wrote:
> Hi,
>
> On 25/06/2024 13:28, Yuke Peng wrote:
> > According to Intel VT-d specification 5.1.4, CFI must be blocked when
> > Extended Interrupt Mode is enabled or Compatibility format interrupts
> > are disabled.
> >
> > Signed-off-by: Yuke Peng
> > --
Hi Phil, Richard
On 6/24/24 4:47 AM, Philippe Mathieu-Daudé wrote:
Hi Gustavo,
On 24/6/24 07:30, Gustavo Romero wrote:
Make the MTE helpers allocation_tag_mem_probe, load_tag1, and store_tag1
available to other subsystems.
Again, you can make them available externally by removing the
static
The read() syscall is not guaranteed to return all data from a file. The
default ROM loader implementation currently does not take this into account,
instead failing if all bytes are not read at once. This change wraps the
read() syscall in a do/while loop to ensure all bytes of the ROM are read.
tcg/riscv: Fix building on OpenBSD/riscv64
Use ucontext_t/struct sigcontext member name from machine/signal.h
instead of Linux specific name.
Signed-off-by: Brad Smith
---
tcg/riscv/tcg-target.c.inc | 5 +
1 file changed, 5 insertions(+)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/
June 25, 2024 at 1:46 AM, "Huang, Ying" wrote:
Hi Huang, Ying,
I'm working on the v2 according to Andrew's and your feedback.
Thank you for your confirmation.
>
> "Ho-Ren Chuang" writes:
>
> >
> > June 24, 2024 at 1:27 AM, "Huang, Ying" wrote:
> >
> > Hi Huang, Ying,
> >
> > Thanks fo
Move GdbCmdParseEntry and its associated types into a separate header
file to allow the use of GdbCmdParseEntry and other gdbstub command
functions outside of gdbstub.c.
Since GdbCmdParseEntry and get_param are now public, kdoc
GdbCmdParseEntry and rename get_param to gdb_get_cmd_param.
This comm
Currently, it's not possible to have stubs specific to a given target,
even though there are GDB features which are target-specific, like, for
instance, memory tagging.
This commit introduces gdb_extend_qsupported_features,
gdb_extend_query_table, and gdb_extend_set_table functions as interfaces
t
Make the gdb_first_attached_cpu and gdb_hextomem non-internal so they
are not confined to use only in gdbstub.c.
Signed-off-by: Gustavo Romero
Reviewed-by: Richard Henderson
---
gdbstub/internals.h| 2 --
include/exec/gdbstub.h | 5 +
include/gdbstub/commands.h | 6 ++
3 fil
Make the MTE helpers allocation_tag_mem_probe, load_tag1, and store_tag1
available to other subsystems.
Signed-off-by: Gustavo Romero
Reviewed-by: Richard Henderson
---
target/arm/tcg/mte_helper.c | 45 -
target/arm/tcg/mte_helper.h | 66 +
Signed-off-by: Jiaxun Yang
---
Jiaxun Yang (2):
hw/intc/loongson_ipi: Gate MMIO regions creation with property
MAINTAINERS: Add myself as a reviewer of LoongArch virt machine
MAINTAINERS| 1 +
hw/intc/loongson_ipi.c | 23 ++-
hw/mips/l
Factor out the code used for setting the MTE TCF0 field from the prctl
code into a convenient function. Other subsystems, like gdbstub, need to
set this field as well, so keep it as a separate function to avoid
duplication and ensure consistency in how this field is set across the
board.
Signed-of
If page in 'ptr_access' is inaccessible and probe is 'true'
allocation_tag_mem_probe should not throw an exception, but currently it
does, so fix it.
Signed-off-by: Gustavo Romero
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
---
target/arm/tcg/mte_helper.c | 3 +++
1 file changed, 3
This patchset adds the stubs necessary to support GDB memory tagging
commands on QEMU aarch64 user mode.
These new stubs handle the qIsAddressTagged, qMemTag, and QMemTag
packets, which allow GDB memory tagging subcommands 'check',
'print-allocation-tag', and 'set-allocation-tag' to work. The rema
Add tests to exercise the MTE stubs. The tests will only run if a
version of GDB that supports MTE is available in the test environment.
Signed-off-by: Gustavo Romero
---
configure | 4 ++
tests/tcg/aarch64/Makefile.target | 14 +++-
tests/tcg/aarch64/gdbstub/tes
Commit 49eba52a52fe ("hw/intc/loongson_ipi: Provide per core MMIO address
spaces") implemented per core MMIO spaces for IPI registers.
However on LoongArch system emulation with high core count it may exhaust
QDEV_MAX_MMIO and trigger assertion.
Given that MMIO region is unused for LoongArch syst
This commit implements the stubs to handle the qIsAddressTagged,
qMemTag, and QMemTag GDB packets, allowing all GDB 'memory-tag'
subcommands to work with QEMU gdbstub on aarch64 user mode. It also
implements the get/set functions for the special GDB MTE register
'tag_ctl', used to control the MTE f
Change 'process_string_cmd' to return true on success and false on
failure, instead of 0 and -1.
Signed-off-by: Gustavo Romero
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
---
gdbstub/gdbstub.c | 40
1 file changed, 20 insertions(+), 20 delet
I would like to be informed on changes made to the LoongArch virt machine.
I'm fairly familiar with Loongson-3 series platform hardware and doing
firmwre (U-Boot) development as hobbyist on LoongArch virt platform,
so I believe I can give positive review input to changes on that machine.
Signed-o
On 6/21/2024 5:21, Fabiano Rosas wrote:> Multifd currently has a simple
scheduling mechanism that distributes
> work to the various channels by providing the client (producer) with a
> memory slot and swapping that slot with free slot from the next idle
> channel (consumer). Or graphically:
>
> []
Hi, Pierrick
> +static void print_access(unsigned int cpu_index, qemu_plugin_meminfo_t
> meminfo,
> + uint64_t vaddr, void *udata)
> +{
> +unsigned size = 8 << qemu_plugin_mem_size_shift(meminfo);
> +const char *type = qemu_plugin_mem_is_store(meminfo) ? "store" : "
We have implemented trigger_common_match(), which checks if the enabled
privilege levels of the trigger match CPU's current privilege level.
Remove the related code in riscv_cpu_debug_check_watchpoint() and invoke
trigger_common_match() to check the privilege levels of the type 2 and
type 6 trigger
We have implemented trigger_common_match(), which checks if the enabled
privilege levels of the trigger match CPU's current privilege level. We
can invoke trigger_common_match() to check the privilege levels of the
type 3 triggers.
Signed-off-by: Alvin Chang
Acked-by: Alistair Francis
---
targe
According to RISC-V Debug specification ratified version 0.13 [1]
(also applied to version 1.0 [2] but it has not been ratified yet), the
enabled privilege levels of the trigger is common match conditions for
all the types of the trigger.
This series modularize the code for checking the privilege
According to RISC-V Debug specification version 0.13 [1] (also applied
to version 1.0 [2] but it has not been ratified yet), there are several
common matching conditions before firing a trigger, including the
enabled privilege levels of the trigger.
This commit adds trigger_common_match() to prepa
Hi Eric,
>-Original Message-
>From: Eric Auger
>Subject: [PATCH 4/7] HostIOMMUDevice: Introduce get_page_size_mask()
>callback
>
>This callback will be used to retrieve the page size mask supported
>along a given Host IOMMU device.
>
>Signed-off-by: Eric Auger
>---
> include/hw/vfio/vfio
> In this commit Write a qtest pnv-spi-seeprom-test to check the
> SPI transactions between spi controller and seeprom device.
>
> Signed-off-by: Chalapathi V
> Acked-by: Cédric Le Goater
Reviewed-by: Caleb Schlossin
Thanks,
Caleb Schlossin
From: Chalapathi V
Hi,
@Stefan, many thanks to you for reviewing the code.
@Klaus, the block layer code has been reviewed by Stefan.
Please help review the nvme layer code.
@Paolo, Please help review the scsi layer code and iscsi
driver code.
Thank you!
On 2024/6/13 15:13, Changqi Lu wrote:
> Hi,
>
> patch v6 has
> An existing QEMU SSI framework is used and SSI_BUS is created.
>
> Signed-off-by: Chalapathi V
Reviewed-by: Caleb Schlossin
Thanks,
Caleb Schlossin
From: Chalapathi V
Sent: Wednesday, June 26, 2024 4:05 AM
To: qemu-devel@nongnu.org
Cc: qemu-...@nongnu.org ;
在 2024/6/26 下午8:10, Philippe Mathieu-Daudé 写道:
Hi Bibo,
On 26/6/24 06:11, maobibo wrote:
On 2024/6/5 上午10:15, Jiaxun Yang wrote:
It was missed out in previous commit.
Fixes: b4a12dfc2132 ("hw/intc/loongarch_ipi: Rename as loongson_ipi")
Signed-off-by: Jiaxun Yang
---
hw/intc/loongarch_ip
> -Original Message-
> From: Alistair Francis
> Sent: Thursday, June 27, 2024 10:18 AM
> To: Alvin Che-Chia Chang(張哲嘉)
> Cc: qemu-ri...@nongnu.org; qemu-devel@nongnu.org;
> alistair.fran...@wdc.com; bin.m...@windriver.com; liwei1...@gmail.com;
> dbarb...@ventanamicro.com; zhiwei_...@linux
From: Alvin Chang via
According to RISC-V Debug specification version 0.13 [1] (also applied
to version 1.0 [2] but it has not been ratified yet), there are several
common matching conditions before firing a trigger, including the
enabled privilege levels of the trigger.
This commit adds trigger
From: Alvin Chang via
We have implemented trigger_common_match(), which checks if the enabled
privilege levels of the trigger match CPU's current privilege level. We
can invoke trigger_common_match() to check the privilege levels of the
type 3 triggers.
Signed-off-by: Alvin Chang
Acked-by: Alis
From: Alvin Chang via
We have implemented trigger_common_match(), which checks if the enabled
privilege levels of the trigger match CPU's current privilege level.
Remove the related code in riscv_cpu_debug_check_watchpoint() and invoke
trigger_common_match() to check the privilege levels of the t
From: Alvin Chang
According to RISC-V Debug specification ratified version 0.13 [1]
(also applied to version 1.0 [2] but it has not been ratified yet), the
enabled privilege levels of the trigger is common match conditions for
all the types of the trigger.
This series modularize the code for che
util: fix building on OpenBSD/powerpc
Signed-off-by: Brad Smith
---
v2: Keep headers in the same order as they originally were.
util/cpuinfo-ppc.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/util/cpuinfo-ppc.c b/util/cpuinfo-ppc.c
index b2d8893a06..
On Wed, Jun 26, 2024 at 11:25 PM Alvin Chang via wrote:
>
> From: Alvin Chang via
Something is still strange with your From
Alistair
>
> According to RISC-V Debug specification version 0.13 [1] (also applied
> to version 1.0 [2] but it has not been ratified yet), there are several
> common mat
> On Mar 28, 2024, at 12:23 AM, Liu, Yuan1 wrote:
>
>> -Original Message-
>> From: Bryan Zhang
>> Sent: Wednesday, March 27, 2024 6:42 AM
>> To: qemu-devel@nongnu.org
>> Cc: pet...@redhat.com; faro...@suse.de; Liu, Yuan1 ;
>> berra...@redhat.com; Zou, Nanhai ;
>> hao.xi...@linux.dev;
`timerlist_run_timers` provides no mechanism to
make sure the data pointed by `opaque` is valid
when calling timer's callback: there could be
another thread running which is destroying
timer's opaque data.
With this change `timer_del` becomes blocking if
timer's callback is running and it will be
mhpmeventhX CSRs are available for RV32. The predicate function
should check that first before checking sscofpmf extension.
Fixes: 14664483457b ("target/riscv: Add sscofpmf extension support")
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
---
tar
From: Kaiwen Xue
This adds the definitions for ISA extension smcntrpmf.
Signed-off-by: Kaiwen Xue
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Atish Patra
---
target/riscv/cpu.h | 6 ++
target/riscv/cpu_bits.h | 29 +
2 files changed, 35 insertion
From: Rajnesh Kanwal
In case of programmable counters configured to count inst/cycles
we often end-up with counter not incrementing at all from kernel's
perspective.
For example:
- Kernel configures hpm3 to count instructions and sets hpmcounter
to -1 and all modes except U mode are inhibi
The timer is setup function is invoked in both hpmcounter
write and mcountinhibit write path. If the OF bit set, the
LCOFI interrupt is disabled. There is no benefitting in
setting up the qemu timer until LCOFI is cleared to indicate
that interrupts can be fired again.
Signed-off-by: Atish Patra
From: Rajnesh Kanwal
Currently we start timer counter from write_mhpmcounter path only
without checking for mcountinhibit bit. This changes adds mcountinhibit
check and also programs the counter from write_mcountinhibit as well.
When a counter is stopped using mcountinhibit we simply update
the
From: Kaiwen Xue
This adds the properties for ISA extension smcntrpmf. Patches
implementing it will follow.
Signed-off-by: Atish Patra
Signed-off-by: Kaiwen Xue
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu_cfg.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/target/riscv/cpu.c b
scounteren/hcountern are also WARL registers similar to mcountern.
Only set the bits for the available counters during the write to
preserve the WARL behavior.
Signed-off-by: Atish Patra
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 12 ++--
Currently, if a counter monitoring cycle/instret is stopped via
mcountinhibit we just update the state while the value is saved
during the next read. This is not accurate as the read may happen
many cycles after the counter is stopped. Ideally, the read should
return the value saved when the counte
From: Rajnesh Kanwal
Combining riscv_cpu_set_virt_enabled() and riscv_cpu_set_mode()
functions. This is to make complete mode change information
available through a single function.
This allows to easily differentiate between HS->VS, VS->HS
and VS->VS transitions when executing state update code
Privilege mode filtering can also be emulated for cycle/instret by
tracking host_ticks/icount during each privilege mode switch. This
patch implements that for both cycle/instret and mhpmcounters. The
first one requires Smcntrpmf while the other one requires Sscofpmf
to be enabled.
The cycle/instr
From: Kaiwen Xue
QEMU only calculates dummy cycles and instructions, so there is no
actual means to stop the icount in QEMU. Hence this patch merely adds
the functionality of accessing the cfg registers, and cause no actual
effects on the counting of cycle and instret counters.
Signed-off-by: At
-
target/riscv/op_helper.c | 17 +--
target/riscv/pmu.c| 181 ---
target/riscv/pmu.h| 4 +
10 files changed, 543 insertions(+), 145 deletions(-)
---
base-commit: 842a3d79a0e37cd3d685c4728308fac0d9bfd0bb
change-id: 20240626-smcntrpmf_v7-3b275d1da117
--
Regards,
Atish patra
On 6/26/24 16:03, Alex Bennée wrote:
Re-enabling the 32 bit host build on i686 showed the recently merged
SEV code doesn't take enough care over its types. While the format
strings could use more portable types there isn't much we can do about
casting uint64_t into a pointer. The easiest solution
By using "print-accesses=true" option, mem plugin will now print every
value accessed, with associated size, type (store vs load) and symbol
where this happens.
Signed-off-by: Pierrick Bouvier
---
tests/plugin/mem.c | 28 +++-
1 file changed, 27 insertions(+), 1 deletion(
Add an explicit test to check expected memory values are read/written.
For sizes 8, 16, 32, 64 and 128, we generate a load/store operation.
For size 8 -> 64, we generate an atomic __sync_val_compare_and_swap too.
For 128bits memory access, we rely on SSE2 instructions.
By default, atomic accesses
Two functions are added to plugins API:
- qemu_plugin_mem_get_value_upper_bits
- qemu_plugin_mem_get_value_lower_bits
This value can be accessed only during a memory callback.
Signed-off-by: Pierrick Bouvier
---
include/qemu/qemu-plugin.h | 20
plugins/api.c
A v2 was sent to fix a compilation issue on aarch64.
On 6/26/24 16:12, Pierrick Bouvier wrote:
This series allows plugins to know which value is read/written during a memory
access.
For every memory access, we know copy this value before calling mem callbacks,
and those can query it using new A
Only multiarch tests are run with plugins, and we want to be able to run
per-arch test with plugins too.
Signed-off-by: Pierrick Bouvier
---
tests/tcg/Makefile.target | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target
index
Different code paths handle memory accesses:
- tcg generated code
- load/store helpers
- atomic helpers
This value is saved in cpu->plugin_state.
Atomic operations are doing read/write at the same time, so we generate
two memory callbacks instead of one, to allow plugins to access distinct
values
A specific plugin test can now read and check a plugin output, to ensure
it contains expected values.
Signed-off-by: Pierrick Bouvier
---
tests/tcg/Makefile.target | 5 +
1 file changed, 5 insertions(+)
diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target
index dc5c8b7a3b4..55
This series allows plugins to know which value is read/written during a memory
access.
For every memory access, we know copy this value before calling mem callbacks,
and those can query it using new API functions:
- qemu_plugin_mem_get_value_upper_bits
- qemu_plugin_mem_get_value_lower_bits
Mem p
data was correctly copied, but size of array was not set
(g_array_sized_new only reserves memory, but does not set size).
As a result, callbacks were not called for code path relying on
plugin_register_vcpu_mem_cb().
Found when trying to trigger mem access callbacks for atomic
instructions.
Sign
On 6/26/24 23:52, Roman Kiryanov wrote:
`timerlist_run_timers` provides no mechanism to
make sure the data pointed by `opaque` is valid
when calling timer's callback: there could be
another thread running which is destroying
timer's opaque data.
With this change `timer_del` becomes blocking if
t
Python 3.13 is in beta and Fedora 41 is preparing to make it the default
system interpreter; enable testing for it.
(In the event problems develop prior to release, it should only impact
the check-python-tox job, which is not run by default and is allowed to
fail.)
Signed-off-by: John Snow
---
There is a bug in this version,
see: https://github.com/pylint-dev/pylint/issues/9751
Signed-off-by: John Snow
---
python/setup.cfg | 1 +
1 file changed, 1 insertion(+)
diff --git a/python/setup.cfg b/python/setup.cfg
index 48668609d3e..8ebd345d7ed 100644
--- a/python/setup.cfg
+++ b/python/se
Fix some regressions in check-python-tox that have crept in since Pylint
3.x, and add Python 3.13 support to the pipeline.
GitLab pipeline (before I fixed the missing DCO, but let's be honest, it
can't possibly be worth re-running so many tests for just that):
https://gitlab.com/jsnow/qemu/-/pip
New bleeding edge versions, new nits to iron out. This addresses the
'check-python-tox' optional GitLab test, while 'check-python-minreqs'
saw no regressions, since it's frozen on an older version of pylint.
Fixes:
qemu/machine/machine.py:345:52: E0606: Possibly using variable 'sock' before
assig
Python 3.13 isn't out yet, but it's in beta and Fedora is ramping up to
make it the default system interpreter for Fedora 41.
They moved our cheese for where ContextManager lives; add a conditional
to locate it while we support both pre-3.9 and 3.13+.
Signed-off-by: John Snow
---
tests/qemu-iot
data was correctly copied, but size of array was not set
(g_array_sized_new only reserves memory, but does not set size).
As a result, callbacks were not called for code path relying on
plugin_register_vcpu_mem_cb().
Found when trying to trigger mem access callbacks for atomic
instructions.
Sign
A specific plugin test can now read and check a plugin output, to ensure
it contains expected values.
Signed-off-by: Pierrick Bouvier
---
tests/tcg/Makefile.target | 5 +
1 file changed, 5 insertions(+)
diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target
index dc5c8b7a3b4..55
Add an explicit test to check expected memory values are read/written.
For sizes 8, 16, 32, 64 and 128, we generate a load/store operation.
For size 8 -> 64, we generate an atomic __sync_val_compare_and_swap too.
For 128bits memory access, we rely on SSE2 instructions.
By default, atomic accesses
Only multiarch tests are run with plugins, and we want to be able to run
per-arch test with plugins too.
Signed-off-by: Pierrick Bouvier
---
tests/tcg/Makefile.target | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target
index
Different code paths handle memory accesses:
- tcg generated code
- load/store helpers
- atomic helpers
This value is saved in cpu->plugin_state.
Atomic operations are doing read/write at the same time, so we generate
two memory callbacks instead of one, to allow plugins to access distinct
values
By using "print-accesses=true" option, mem plugin will now print every
value accessed, with associated size, type (store vs load) and symbol
where this happens.
Signed-off-by: Pierrick Bouvier
---
tests/plugin/mem.c | 28 +++-
1 file changed, 27 insertions(+), 1 deletion(
Two functions are added to plugins API:
- qemu_plugin_mem_get_value_upper_bits
- qemu_plugin_mem_get_value_lower_bits
This value can be accessed only during a memory callback.
Signed-off-by: Pierrick Bouvier
---
include/qemu/qemu-plugin.h | 20
plugins/api.c
This series allows plugins to know which value is read/written during a memory
access.
For every memory access, we know copy this value before calling mem callbacks,
and those can query it using new API functions:
- qemu_plugin_mem_get_value_upper_bits
- qemu_plugin_mem_get_value_lower_bits
Mem p
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