Re: [PATCH 0/6] Introduce extension implied rules

Patchset resend: https://lists.gnu.org/archive/html/qemu-riscv/2024-06/msg00130.html 於 2024年6月3日 週一 下午2:07寫道： > From: Frank Chang > > Currently, the implied extensions are enabled and checked in > riscv_cpu_validate_set_extensions(). However, the order of enabling the > implied extensions must

[PATCH RESEND 6/6] target/riscv: Remove extension auto-update check statements

From: Frank Chang Remove the old-fashioned extension auto-update check statements as they are replaced by the extension implied rules. Signed-off-by: Frank Chang --- target/riscv/tcg/tcg-cpu.c | 115 - 1 file changed, 115 deletions(-) diff --git a/target/ri

[PATCH RESEND 1/6] target/riscv: Introduce extension implied rules definition

From: Frank Chang RISCVCPUImpliedExtsRule is created to store the implied rules. 'is_misa' flag is used to distinguish whether the rule is derived from the MISA or other extensions. 'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it stores the offset of the extension defined in RISCVCP

Re: [PATCH] MAINTAINERS: Add reviewers for ASPEED BMCs

On 5/6/24 08:03, Jamin Lin wrote: Add ASPEED members "Steven Lee", "Troy Lee" and "Jamin Lin" to be reviewers of ASPEED BMCs. Signed-off-by: Jamin Lin Signed-off-by: Troy Lee Signed-off-by: Steven Lee --- MAINTAINERS | 3 +++ 1 file changed, 3 insertions(+) Thanks :) Reviewed-by: Philip

[PATCH RESEND 0/6] Introduce extension implied rules

From: Frank Chang Currently, the implied extensions are enabled and checked in riscv_cpu_validate_set_extensions(). However, the order of enabling the implied extensions must follow a strict sequence, which is error-prone. This patchset introduce extension implied rule helpers to enable the impl

[PATCH RESEND 4/6] target/riscv: Add standard extension implied rules

From: Frank Chang Add standard extension implied rules to enable the implied extensions of the standard extension recursively. Signed-off-by: Frank Chang --- target/riscv/cpu.c | 340 + 1 file changed, 340 insertions(+) diff --git a/target/riscv/cpu

[PATCH RESEND 2/6] target/riscv: Introduce extension implied rule helpers

From: Frank Chang Introduce helpers to enable the extensions based on the implied rules. The implied extensions are enabled recursively, so we don't have to expand all of them manually. This also eliminates the old-fashioned ordering requirement. For example, Zvksg implies Zvks, Zvks implies Zvks

[PATCH RESEND 5/6] target/riscv: Add Zc extension implied rule

From: Frank Chang Zc extension has special implied rules that need to be handled separately. Signed-off-by: Frank Chang --- target/riscv/tcg/tcg-cpu.c | 34 ++ 1 file changed, 34 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c

[PATCH RESEND 3/6] target/riscv: Add MISA implied rules

From: Frank Chang Add MISA extension implied rules to enable the implied extensions of MISA recursively. Signed-off-by: Frank Chang --- target/riscv/cpu.c | 50 +- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/tar

Re: [PATCH 2/6] target/riscv: Introduce extension implied rule helpers

於 2024年6月3日 週一 下午2:06寫道： > > From: Frank Chang > > Introduce helpers to enable the extensions based on the implied rules. > The implied extensions are enabled recursively, so we don't have to > expand all of them manually. This also eliminates the old-fashioned > ordering requirement. For example

Re: [PATCH 5/6] target/riscv: Add CTR sctrclr instruction.

Chapter 5 describes the CTR behavior when Smstaten is enabled, but it does not talk about the CTR behavior when Smstateen is disabled, that is, there is no mstateen0 and hstateen0 CSR. The spec states: * Attempts to access sctrdepth from VS-mode or VU-mode raise a virtual-instruction excep

Re: [PATCH v4 3/3] hw/loongarch/virt: Enable extioi virt extension

On 2024/5/28 下午4:38, Song Gao wrote: This patch adds a new board attribute 'v-eiointc'. A value of true enables the virt extended I/O interrupt controller. VMs working in kvm mode have 'v-eiointc' enabled by default. Signed-off-by: Song Gao --- include/hw/loongarch/virt.h | 1 + target/l

Re: [PATCH v4 2/3] hw/loongarch/virt: Use MemTxAttrs interface for misc ops

On 2024/5/28 下午4:38, Song Gao wrote: Use MemTxAttrs interface read_with_attrs/write_with_attrs for virt_iocsr_misc_ops. Signed-off-by: Song Gao --- hw/loongarch/virt.c | 36 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/hw/loongarch/v

[PATCH] MAINTAINERS: Add reviewers for ASPEED BMCs

Add ASPEED members "Steven Lee", "Troy Lee" and "Jamin Lin" to be reviewers of ASPEED BMCs. Signed-off-by: Jamin Lin Signed-off-by: Troy Lee Signed-off-by: Steven Lee --- MAINTAINERS | 3 +++ 1 file changed, 3 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 951556224a..0f63bcdc7d 1

Re: [PATCH] MAINTAINERS: Add reviewers for ASPEED BMCs

On 6/5/24 08:03, Jamin Lin wrote: Add ASPEED members "Steven Lee", "Troy Lee" and "Jamin Lin" to be reviewers of ASPEED BMCs. Signed-off-by: Jamin Lin Signed-off-by: Troy Lee Signed-off-by: Steven Lee Reviewed-by: Cédric Le Goater Thanks, C. --- MAINTAINERS | 3 +++ 1 file changed

RE: [PATCH] MAINTAINERS: Add maintainers for ASPEED BMCs

Hi Cedric, > From: Cédric Le Goater > Sent: Wednesday, June 5, 2024 1:58 PM > To: Jamin Lin ; Philippe Mathieu-Daudé > ; Thomas Huth ; Michael S. Tsirkin > ; Peter Maydell ; open list:All > patches CC here > Cc: Steven Lee ; Troy Lee > > Subject: Re: [PATCH] MAINTAINERS: Add maintainers for ASPE

Re: [PATCH] MAINTAINERS: Add maintainers for ASPEED BMCs

On 6/5/24 05:44, Jamin Lin wrote: Add ASPEED members "Steven Lee", "Troy Lee" and "Jamin Lin" to be maintainers of ASPEED BMCs. Let's start with Reviewers. please resend. https://qemu.readthedocs.io/en/v9.0.0/devel/maintainers.html Thanks, C. Signed-off-by: Jamin Lin Signed-off-by: Troy

RE: [PATCH v4 00/16] Add AST2700 support

Hi Cedric, > From: Jamin Lin > Subject: RE: [PATCH v4 00/16] Add AST2700 support > > Hi Cedric, > > > From: Cédric Le Goater > > On 5/28/24 12:02, Jamin Lin wrote: > > > Hi Cedric, > > > > > >> -Original Message- > > >> From: Cédric Le Goater > > >> Sent: Tuesday, May 28, 2024 5:56 PM

[PATCH] MAINTAINERS: Add maintainers for ASPEED BMCs

Add ASPEED members "Steven Lee", "Troy Lee" and "Jamin Lin" to be maintainers of ASPEED BMCs. Signed-off-by: Jamin Lin Signed-off-by: Troy Lee Signed-off-by: Steven Lee --- MAINTAINERS | 3 +++ 1 file changed, 3 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 951556224a..39651be467

Re: [PATCH 0/6] target/riscv: Add support for Control Transfer Records Ext.

Ah, good catch. We removed that dependency late. I'll fix it. On Tue, Jun 4, 2024 at 8:34 PM Jason Chien wrote: > Thank you for pointing that out. CTR does not use miselect and mireg*. > There is no dependency on Smcsrind. I believe the spec needs to be > corrected. > > Chapter 1 states that:

Re: [PATCH 0/6] target/riscv: Add support for Control Transfer Records Ext.

Thank you for pointing that out. CTR does not use miselect and mireg*. There is no dependency on Smcsrind. I believe the spec needs to be corrected. Chapter 1 states that: Smctr depends on the Smcsrind extension, while Ssctr depends on the Sscsrind extension. Further, both Smctr and Ssctr depe

Re: [PATCH v3 1/4] hw/intc: Remove loongarch_ipi.c

在 2024/6/5 上午10:15, Jiaxun Yang 写道: It was missed out in previous commit. Fixes: b4a12dfc2132 ("hw/intc/loongarch_ipi: Rename as loongson_ipi") Signed-off-by: Jiaxun Yang --- Reviewed-by: Song Gao Thanks. Song Gao hw/intc/loongarch_ipi.c | 347 -

Re: [PATCH v3 4/4] hw/intc/loongson_ipi: Replace ipi_getcpu with cpu_by_arch_id

在 2024/6/5 上午10:15, Jiaxun Yang 写道: cpu_by_arch_id is doing the same thing as our ipi_getcpu logic. Signed-off-by: Jiaxun Yang --- Reviewed-by: Song Gao Thanks. Song Gao hw/intc/loongson_ipi.c | 39 +++ 1 file changed, 3 insertions(+), 36 deletions(-)

[PATCH v3 0/3] target/riscv/kvm: QEMU support for KVM Guest Debug on RISC-V

This series implements QEMU KVM Guest Debug on RISC-V, with which we could debug RISC-V KVM guest from the host side, using software breakpoints. This series is based on riscv-to-apply.next branch and is also available at: https://github.com/Du-Chao/alistair23-qemu/tree/riscv-to-apply.next.0605 T

[PATCH v3 1/3] target/riscv/kvm: add software breakpoints support

This patch implements insert/remove software breakpoint process. For RISC-V, GDB treats single-step similarly to breakpoint: add a breakpoint at the next step address, then continue. So this also works for single-step debugging. Implement kvm_arch_update_guest_debug(): Set the control flag when t

[PATCH v3 2/3] target/riscv/kvm: handle the exit with debug reason

If the breakpoint belongs to the userspace then set the ret value. Signed-off-by: Chao Du Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Acked-by: Alistair Francis --- target/riscv/kvm/kvm-cpu.c | 20 1 file changed, 20 insertions(+) diff --git a/target/r

[PATCH v3 3/3] target/riscv/kvm: define TARGET_KVM_HAVE_GUEST_DEBUG

To enable the KVM GUEST DEBUG for RISC-V at QEMU side. Signed-off-by: Chao Du Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Acked-by: Alistair Francis --- configs/targets/riscv64-softmmu.mak | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/targets/riscv64-softmmu.m

[PATCH v3 1/4] hw/intc: Remove loongarch_ipi.c

It was missed out in previous commit. Fixes: b4a12dfc2132 ("hw/intc/loongarch_ipi: Rename as loongson_ipi") Signed-off-by: Jiaxun Yang --- hw/intc/loongarch_ipi.c | 347 1 file changed, 347 deletions(-) diff --git a/hw/intc/loongarch_ipi.c b/hw/i

[PATCH v3 4/4] hw/intc/loongson_ipi: Replace ipi_getcpu with cpu_by_arch_id

cpu_by_arch_id is doing the same thing as our ipi_getcpu logic. Signed-off-by: Jiaxun Yang --- hw/intc/loongson_ipi.c | 39 +++ 1 file changed, 3 insertions(+), 36 deletions(-) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index c8a25b4eb8e2..b

[PATCH v3 3/4] hw/mips/loongson3_virt: Wire up loongson_ipi device

Wire up loongson_ipi device for loongson3_virt machine, so we can have SMP support for TCG backend as well. Signed-off-by: Jiaxun Yang --- hw/mips/Kconfig | 1 + hw/mips/loongson3_bootp.c | 2 -- hw/mips/loongson3_bootp.h | 3 +++ hw/mips/loongson3_virt.c | 39 +

[PATCH v3 2/4] hw/intc/loongson_ipi: Provide per core MMIO address spaces

The real IPI hardware have dedicated MMIO registers mapped into memory address space for every core. This is not used by LoongArch guest software but it is essential for CPU without IOCSR such as Loongson-3A1000. Implement it with existing infrastructure. Acked-by: Song Gao Signed-off-by: Jiaxun

[PATCH v3 0/4] hw/mips/loongson3_virt: Implement IPI support

Hi all, This series enabled IPI support for loongson3 virt board, loosely based on my previous work[1]. It generalized loongarch_ipi device to share among both loongarch and MIPS machines. Thanks [1]: https://lore.kernel.org/all/20230521102307.87081-1-jiaxun.y...@flygoat.com/ To: qemu-devel@no

[PATCH v2 4/4] hw/intc/loongson_ipi: Replace ipi_getcpu with cpu_by_arch_id

cpu_by_arch_id is doing the same thing as our ipi_getcpu logic. Signed-off-by: jiaxun.y...@flygoat.com --- hw/intc/loongson_ipi.c | 39 +++ 1 file changed, 3 insertions(+), 36 deletions(-) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index c8a

[PATCH v2 3/4] hw/mips/loongson3_virt: Wire up loongson_ipi device

Wire up loongson_ipi device for loongson3_virt machine, so we can have SMP support for TCG backend as well. Signed-off-by: Jiaxun Yang --- hw/mips/Kconfig | 1 + hw/mips/loongson3_bootp.c | 2 -- hw/mips/loongson3_bootp.h | 3 +++ hw/mips/loongson3_virt.c | 39 +

[PATCH v2 2/4] hw/intc/loongson_ipi: Provide per core MMIO address spaces

The real IPI hardware have dedicated MMIO registers mapped into memory address space for every core. This is not used by LoongArch guest software but it is essential for CPU without IOCSR such as Loongson-3A1000. Implement it with existing infrastructure. Acked-by: Song Gao Signed-off-by: Jiaxun

[PATCH v2 1/4] hw/intc: Remove loongarch_ipi.c

It was missed out in previous commit. Fixes: b4a12dfc2132 ("hw/intc/loongarch_ipi: Rename as loongson_ipi") Signed-off-by: jiaxun.y...@flygoat.com --- hw/intc/loongarch_ipi.c | 347 1 file changed, 347 deletions(-) diff --git a/hw/intc/loongarch_

[PATCH v2 0/4] hw/mips/loongson3_virt: Implement IPI support

Hi all, This series enabled IPI support for loongson3 virt board, loosely based on my previous work[1]. It generalized loongarch_ipi device to share among both loongarch and MIPS machines. Thanks [1]: https://lore.kernel.org/all/20230521102307.87081-1-jiaxun.y...@flygoat.com/ To: qemu-devel@no

Re: Unexpected error in rme_configure_one() at ../target/arm/kvm-rme.c:159

Hi Jean, On 6/4/24 21:15, Jean-Philippe Brucker wrote: On Tue, Jun 04, 2024 at 01:02:08PM +1000, Gavin Shan wrote: On 6/3/24 18:24, Jean-Philippe Brucker wrote: On Sat, Jun 01, 2024 at 08:14:46PM +1000, Gavin Shan wrote: ---> guest edk2 # git clone https://git.codelinaro.org/linaro/dcap/edk2

Re: [PATCH] target/loongarch: fix a wrong print in cpu dump

在 2024/6/4 下午3:38, lanyanzhi...@ict.ac.cn 写道: From: lanyanzhi description: loongarch_cpu_dump_state() want to dump all loongarch cpu state registers, but there is a tiny typographical error when printing "PRCFG2". Signed-off-by: lanyanzhi --- target/loongarch/cpu.c | 2 +- 1 file chan

[PATCH v4 4/4] iotests: Add `vvfat` tests

Added several tests to verify the implementation of the vvfat driver. We needed a way to interact with it, so created a basic `fat16.py` driver that handled writing correct sectors for us. Added `vvfat` to the non-generic formats, as its not a normal image format. Signed-off-by: Amjad Alsharafi

[PATCH v4 2/4] vvfat: Fix usage of `info.file.offset`

The field is marked as "the offset in the file (in clusters)", but it was being used like this `cluster_size*(nums)+mapping->info.file.offset`, which is incorrect. Additionally, removed the `abort` when `first_mapping_index` does not match, as this matches the case when adding new clusters for fil

[PATCH v4 3/4] vvfat: Fix reading files with non-continuous clusters

When reading with `read_cluster` we get the `mapping` with `find_mapping_for_cluster` and then we call `open_file` for this mapping. The issue appear when its the same file, but a second cluster that is not immediately after it, imagine clusters `500 -> 503`, this will give us 2 mappings one has th

[PATCH v4 1/4] vvfat: Fix bug in writing to middle of file

Before this commit, the behavior when calling `commit_one_file` for example with `offset=0x2000` (second cluster), what will happen is that we won't fetch the next cluster from the fat, and instead use the first cluster for the read operation. This is due to off-by-one error here, where `i=0x2000

[PATCH v4 0/4] vvfat: Fix write bugs for large files and add iotests

These patches fix some bugs found when modifying files in vvfat. First, there was a bug when writing to the cluster 2 or above of a file, it will copy the cluster before it instead, so, when writing to cluster=2, the content of cluster=1 will be copied into disk instead in its place. Another issue

Re: [PATCH 1/6] target/riscv: Remove obsolete sfence.vm instruction

On Thu, May 30, 2024 at 2:12 AM Rajnesh Kanwal wrote: > > Signed-off-by: Rajnesh Kanwal Reviewed-by: Alistair Francis Alistair > --- > target/riscv/insn32.decode | 1 - > target/riscv/insn_trans/trans_privileged.c.inc | 5 - > 2 files changed, 6 deletions(-) > > diff

Re: [PATCH v2 0/8] hw/riscv/virt.c: aplic/imsic DT fixes

On Sat, Jun 1, 2024 at 6:30 AM Daniel Henrique Barboza wrote: > > Hi, > > This is a series that is being spun from the reviews given on patch 1 > [1]. We'll fix some DT validation issues we have in the 'virt' machine > [2] that aren't related to missing extensions in the DT spec. > > I'll leave to

RE: [PATCH v5 00/17] Add AST2700 support

Hi Cedric, > From: Cédric Le Goater > Sent: Tuesday, June 4, 2024 7:52 PM > To: Jamin Lin ; Peter Maydell > ; Andrew Jeffery ; > Joel Stanley ; Alistair Francis ; > Cleber > Rosa ; Philippe Mathieu-Daudé ; > Wainer dos Santos Moschetta ; Beraldo Leal > ; open list:ASPEED BMCs ; open > list:All p

Re: [PATCH v3 0/6] vvfat: Fix write bugs for large files and add iotests

On Fri, May 31, 2024 at 07:22:49PM +0200, Kevin Wolf wrote: > Am 26.05.2024 um 11:56 hat Amjad Alsharafi geschrieben: > > These patches fix some bugs found when modifying files in vvfat. > > First, there was a bug when writing to the cluster 2 or above of a file, it > > will copy the cluster before

Re: [PATCH v2 7/8] hw/riscv/virt.c: imsics DT: add 'qemu, imsics' to 'compatible'

On Sat, Jun 1, 2024 at 6:31 AM Daniel Henrique Barboza wrote: > > The DT docs for riscv,imsics [1] predicts a 'qemu,imsics' enum in the > 'compatible' property. > > [1] Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml > > Reported-by: Conor Dooley > Fixes: 28d8c281200f ("h

Re: [PATCH v2 8/8] hw/riscv/virt.c: imsics DT: add '#msi-cells'

On Sat, Jun 1, 2024 at 6:31 AM Daniel Henrique Barboza wrote: > > The DT docs for riscv,imsics [1] requires a 'msi-cell' property. Add one > and set it zero. > > [1] Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml > > Reported-by: Conor Dooley > Fixes: 28d8c281200f ("hw/r

Re: [PATCH v2 6/8] hw/riscv/virt.c: change imsic nodename to 'interrupt-controller'

On Sat, Jun 1, 2024 at 6:30 AM Daniel Henrique Barboza wrote: > > The Linux DT docs for imsic [1] predicts an 'interrupt-controller@addr' > node, not 'imsic@addr', given this node inherits the > 'interrupt-controller' node. > > [1] Documentation/devicetree/bindings/interrupt-controller/riscv,imsic

Re: [PATCH v2 5/8] hw/riscv/virt.c: aplic DT: rename prop to 'riscv, delegation'

On Sat, Jun 1, 2024 at 6:31 AM Daniel Henrique Barboza wrote: > > The DT docs for riscv,aplic [1] predicts a 'riscv,delegation' property. > Not 'riscv,delegate'. > > [1] Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml > > Reported-by: Conor Dooley > Fixes: e6faee65855b ("h

Re: [PATCH-for-9.1 v2 2/3] migration: Remove RDMA protocol handling

* Michael Galaxy (mgal...@akamai.com) wrote: > One thing to keep in mind here (despite me not having any hardware to test) > was that one of the original goals here > in the RDMA implementation was not simply raw throughput nor raw latency, > but a lack of CPU utilization in kernel > space due to t

Re: [PATCH v2 4/8] hw/riscv/virt.c: aplic DT: add 'qemu, aplic' to 'compatible'

On Sat, Jun 1, 2024 at 6:31 AM Daniel Henrique Barboza wrote: > > The DT docs for riscv,aplic [1] predicts a 'qemu,aplic' enum in the > 'compatible' property. > > [1] Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml > > Reported-by: Conor Dooley > Fixes: e6faee65855b ("hw/r

Re: [PATCH v2 3/8] hw/riscv/virt.c: rename aplic nodename to 'interrupt-controller'

On Sat, Jun 1, 2024 at 6:30 AM Daniel Henrique Barboza wrote: > > The correct name of the aplic controller node, as per Linux kernel DT > docs [1], is 'interrupt-controller@addr'. > > [1] Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml > > Reported-by: Conor Dooley > Fixes

Re: [PATCH v2 2/8] hw/riscv/virt.c: add aplic nodename helper

On Sat, Jun 1, 2024 at 6:31 AM Daniel Henrique Barboza wrote: > > We'll change the aplic DT nodename in the next patch and the name is > hardcoded in 2 different functions. Create a helper to change a single > place later. > > While we're at it, in create_fdt_socket_aplic(), move 'aplic_name' > in

Re: [PATCH v2 1/8] hw/riscv/virt.c: add address-cells in create_fdt_one_aplic()

On Sat, Jun 1, 2024 at 6:31 AM Daniel Henrique Barboza wrote: > > We need #address-cells properties in all interrupt controllers that are > referred by an interrupt-map [1]. For the RISC-V machine, both PLIC and > APLIC controllers must have this property. > > PLIC already sets it in create_fdt_so

Re: [PATCH v2 06/18] monitor: Stop removing non-duplicated fds

* Fabiano Rosas (faro...@suse.de) wrote: > Peter Xu writes: > > > On Thu, May 23, 2024 at 04:05:36PM -0300, Fabiano Rosas wrote: > >> We've been up until now cleaning up any file descriptors that have > >> been passed into QEMU and never duplicated[1,2]. A file descriptor > >> without duplicates

Re: [PATCH RESEND v2 3/3] target/riscv/kvm: define TARGET_KVM_HAVE_GUEST_DEBUG

On Tue, May 28, 2024 at 6:12 PM Chao Du wrote: > > To enable the KVM GUEST DEBUG for RISC-V at QEMU side. > > Signed-off-by: Chao Du > Reviewed-by: Daniel Henrique Barboza > Reviewed-by: Andrew Jones Acked-by: Alistair Francis Alistair > --- > configs/targets/riscv64-softmmu.mak | 1 + > 1

Re: [PATCH RESEND v2 2/3] target/riscv/kvm: handle the exit with debug reason

On Tue, May 28, 2024 at 6:12 PM Chao Du wrote: > > If the breakpoint belongs to the userspace then set the ret value. > > Signed-off-by: Chao Du > Reviewed-by: Daniel Henrique Barboza > Reviewed-by: Andrew Jones Acked-by: Alistair Francis Alistair > --- > target/riscv/kvm/kvm-cpu.c | 20 ++

Re: [PATCH RESEND v2 1/3] target/riscv/kvm: add software breakpoints support

On Tue, May 28, 2024 at 6:12 PM Chao Du wrote: > > This patch implements insert/remove software breakpoint process. > > For RISC-V, GDB treats single-step similarly to breakpoint: add a > breakpoint at the next step address, then continue. So this also > works for single-step debugging. > > Implem

Re: [PATCH 3/3] hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART

On Tue, May 28, 2024 at 5:32 PM Sunil V L wrote: > > RISC-V is going to use new HID RSCV0003 for generi UART. So, update the > HID. > > Signed-off-by: Sunil V L Acked-by: Alistair Francis Alistair > --- > hw/riscv/virt-acpi-build.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > >

Re: [PATCH 2/3] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC

On Tue, May 28, 2024 at 5:32 PM Sunil V L wrote: > > PLIC and APLIC should be in namespace as well. So, add them using the > defined HID. > > Signed-off-by: Sunil V L Acked-by: Alistair Francis Alistair > --- > hw/riscv/virt-acpi-build.c | 47 ++ > 1 file

Re: [PATCH 1/3] gpex-acpi: Support PCI link devices outside the host bridge

On Tue, May 28, 2024 at 5:32 PM Sunil V L wrote: > > Currently, PCI link devices (PNP0C0F) are always created within the > scope of the PCI root complex. However, RISC-V needs PCI link devices to > be outside the scope of the PCI host bridge to properly enable the probe > order. This matches the e

Re: [PATCH 0/6] target/riscv: Add support for Control Transfer Records Ext.

There is no dependency on Smcsrind, only Sscsrind. On Tue, Jun 4, 2024 at 12:29 AM Jason Chien wrote: > Smctr depends on the Smcsrind extension, Ssctr depends on the Sscsrind > extension, and both Smctr and Ssctr depend upon implementation of S-mode. > There should be a dependency check in riscv

Re: [PULL 00/32] Misc HW / accel patches

https://github.com/philmd/qemu.git tags/hw-misc-accel-20240604 for you to fetch changes up to 7c2397643c1e025c157bab95088b3b480f0d98ae: usb: add config options for the hub and hid devices (2024-06-04 11:53:43 +0200) Following checkpatch.pl error ignored: ERROR: suspect code indent for c

Re: [PATCH 2/7] configure: Add uadk option

Shameer Kolothum via writes: > Add --enable-uadk and --disable-uadk options to enable and disable > UADK compression accelerator. This is for using UADK based hardware > accelerators for live migration. > > Signed-off-by: Shameer Kolothum Reviewed-by: Fabiano Rosas

[PATCH] hw/nvme: fix BAR size mismatch of SR-IOV VF

PF initializes SR-IOV VF BAR0 region in nvme_init_sriov() with bar_size calcaulted by Primary Controller Capability such as VQFRSM and VIFRSM rather than `max_ioqpairs` and `msix_qsize` which is for PF only. In this case, the bar size reported in nvme_init_sriov() by PF and nvme_init_pci() by VF m

Re: [PATCH 3/7] migration/multifd: add uadk compression framework

Shameer Kolothum via writes: > Adds the skeleton to support uadk compression method. > Complete functionality will be added in subsequent patches. > > Signed-off-by: Shameer Kolothum Reviewed-by: Fabiano Rosas

Re: [PATCH v3 0/4] tests/qtest/migration-test: Improve and enable on ppc64

On Thu, 30 May 2024 17:44:48 +1000, Nicholas Piggin wrote: > Since v2: > - Fixed subject typo noticed by Thomas. > - Drop the non-ppc patches from the series. > > Thanks, > Nick > > [...] Queued, thanks!

Re: [PATCH 0/7] Live migration acceleration with UADK

On Wed, May 29, 2024 at 10:44:20AM +0100, Shameer Kolothum via wrote: > Hi, > > This series adds support for UADK library based hardware acceleration > for live migration. UADK[0] is a general-purpose user space accelerator > framework that uses shared virtual addressing (SVA) to provide a unified

Re: [PATCH v2 18/18] migration/ram: Add direct-io support to precopy file migration

On Thu, May 23, 2024 at 04:05:48PM -0300, Fabiano Rosas wrote: > We've recently added support for direct-io with multifd, which brings > performance benefits, but creates a non-uniform user interface by > coupling direct-io with the multifd capability. This means that users > cannot keep the direct

Re: [PATCH v2 15/18] tests/qtest/migration: Add a test for mapped-ram with passing of fds

On Thu, May 23, 2024 at 04:05:45PM -0300, Fabiano Rosas wrote: > Add a multifd test for mapped-ram with passing of fds into QEMU. This > is how libvirt will consume the feature. > > There are a couple of details to the fdset mechanism: > > - multifd needs two distinct file descriptors (not duplic

Re: [PATCH v2 14/18] migration: Add documentation for fdset with multifd + file

On Thu, May 23, 2024 at 04:05:44PM -0300, Fabiano Rosas wrote: > With the last few changes to the fdset infrastructure, we now allow > multifd to use an fdset when migrating to a file. This is useful for > the scenario where the management layer wants to have control over the > migration file. > >

Re: [PATCH v7 1/7] docs/migration: add qpl compression feature

On Mon, Jun 03, 2024 at 11:41:00PM +0800, Yuan Liu wrote: > add Intel Query Processing Library (QPL) compression method > introduction > > Signed-off-by: Yuan Liu > Reviewed-by: Nanhai Zou Acked-by: Peter Xu -- Peter Xu

Re: [PATCH 5/6] target/riscv: Add CTR sctrclr instruction.

On Tue, Jun 4, 2024 at 10:19 AM Jason Chien wrote: > > Rajnesh Kanwal 於 2024/5/30 上午 12:09 寫道: > > CTR extension adds a new instruction sctrclr to quickly > > clear the recorded entries buffer. > > > > Signed-off-by: Rajnesh Kanwal > > --- > > target/riscv/cpu.h |

Re: [PULL 00/20] Net patches

On 6/4/24 02:37, Jason Wang wrote: The following changes since commit 3ab42e46acf867c45bc929fcc37693e327a35a24: Merge tag 'pull-ufs-20240603' ofhttps://gitlab.com/jeuk20.kim/qemu into staging (2024-06-03 08:18:14 -0500) are available in the Git repository at: https://github.com/jasowan

Re: [PATCH 0/6] refactor RDMA live migration based on rsocket API

Hi, Lei, Jialin, Thanks a lot for working on this! I think we'll need to wait a bit on feedbacks from Jinpu and his team on RDMA side, also Daniel for iochannels. Also, please remember to copy Fabiano Rosas in any relevant future posts. We'd also like to know whether he has any comments too. I

[PULL 36/46] bios-tables-test: Add data for complex numa test (GI, GP etc)

From: Jonathan Cameron Given this is a new configuration, there are affects on APIC, CEDT and DSDT, but the key elements are in SRAT (plus related data in HMAT). The configuration has node to exercise many different combinations. 0) CPUs + Memory 1) GI only 2) GP only 3) CPUS only 4) Memory onl

[PULL 23/46] hw/mem/cxl-type3: Refactor ct3_build_cdat_entries_for_mr to take mr size instead of mr as argument

From: Fan Ni The function ct3_build_cdat_entries_for_mr only uses size of the passed memory region argument, refactor the function definition to make the passed arguments more specific. Reviewed-by: Gregory Price Reviewed-by: Jonathan Cameron Signed-off-by: Fan Ni Message-Id: <20240523174651.

[PULL 46/46] hw/cxl: Fix read from bogus memory

From: Ira Weiny Peter and coverity report: We've passed '&data' to address_space_write(), which means "read from the address on the stack where the function argument 'data' lives", so instead of writing 64 bytes of data to the guest , we'll write 64 bytes which st

[PULL 45/46] virtio-pci: Fix the failure process in kvm_virtio_pci_vector_use_one()

From: Cindy Lu In function kvm_virtio_pci_vector_use_one(), the function will only use the irqfd/vector for itself. Therefore, in the undo label, the failing process is incorrect. To fix this, we can just remove this label. Fixes: f9a09ca3ea ("vhost: add support for configure interrupt") Cc: qem

[PULL 40/46] tests/qtest/pvpanic: use centralized definition of supported events

From: Thomas Weißschuh Avoid the necessity to update all tests when new events are added to the device. Acked-by: Thomas Huth Reviewed-by: Cornelia Huck Signed-off-by: Thomas Weißschuh Message-Id: <20240527-pvpanic-shutdown-v8-4-5a28ec025...@t-8ch.de> Reviewed-by: Michael S. Tsirkin Signed-o

[PULL 30/46] hw/mem/cxl_type3: Allow to release extent superset in QMP interface

From: Fan Ni Before the change, the QMP interface used for add/release DC extents only allows to release an extent whose DPA range is contained by a single accepted extent in the device. With the change, we relax the constraints. As long as the DPA range of the extent is covered by accepted ext

[PULL 42/46] pvpanic: Emit GUEST_PVSHUTDOWN QMP event on pvpanic shutdown signal

From: Alejandro Jimenez Emit a QMP event on receiving a PVPANIC_SHUTDOWN event. Even though a typical SHUTDOWN event will be sent, it will be indistinguishable from a shutdown originating from other cases (e.g. KVM exit due to KVM_SYSTEM_EVENT_SHUTDOWN) that also issue the guest-shutdown cause. A

[PULL 44/46] Revert "docs/specs/pvpanic: mark shutdown event as not implemented"

From: Thomas Weißschuh The missing functionality has been implemented now. This reverts commit e739d1935c461d0668057e9dbba9d06f728d29ec. Signed-off-by: Thomas Weißschuh Message-Id: <20240527-pvpanic-shutdown-v8-8-5a28ec025...@t-8ch.de> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S.

[PULL 22/46] hw/mem/cxl_type3: Add support to create DC regions to type3 memory devices

From: Fan Ni With the change, when setting up memory for type3 memory device, we can create DC regions. A property 'num-dc-regions' is added to ct3_props to allow users to pass the number of DC regions to create. To make it easier, other region parameters like region base, length, and block size

[PULL 06/46] virtio: Prevent creation of device using notification-data with ioeventfd

From: Jonah Palmer Prevent the realization of a virtio device that attempts to use the VIRTIO_F_NOTIFICATION_DATA transport feature without disabling ioeventfd. Due to ioeventfd not being able to carry the extra data associated with this feature, having both enabled is a functional mismatch and

[PULL 41/46] hw/misc/pvpanic: add support for normal shutdowns

From: Thomas Weißschuh Shutdown requests are normally hardware dependent. By extending pvpanic to also handle shutdown requests, guests can submit such requests with an easily implementable and cross-platform mechanism. Acked-by: Cornelia Huck Signed-off-by: Thomas Weißschuh Message-Id: <20240

[PULL 32/46] hw/acpi: Insert an acpi-generic-node base under acpi-generic-initiator

From: Jonathan Cameron This will simplify reuse when adding acpi-generic-port. Note that some error_printf() messages will now print acpi-generic-node whereas others will move to type specific cases in next patch so are left alone for now. Signed-off-by: Jonathan Cameron Message-Id: <2024052410

[PULL 14/46] vhost-user-gpu: fix import of DMABUF

From: Marc-André Lureau When using vhost-user-gpu with GL, qemu -display gtk doesn't show output and prints: qemu: eglCreateImageKHR failed Since commit 9ac06df8b ("virtio-gpu-udmabuf: correct naming of QemuDmaBuf size properties"), egl_dmabuf_import_texture() uses backing_{width,height} for the

[PULL 34/46] bios-tables-test: Allow for new acpihmat-generic-x test data.

From: Jonathan Cameron The test to be added exercises many corners of the SRAT and HMAT table generation. Signed-off-by: Jonathan Cameron Message-Id: <20240524100507.32106-5-jonathan.came...@huawei.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/qtest/bios-ta

[PULL 38/46] linux-headers: update to 6.10-rc1

From: Thomas Weißschuh Signed-off-by: Thomas Weißschuh Message-Id: <20240527-pvpanic-shutdown-v8-2-5a28ec025...@t-8ch.de> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/standard-headers/linux/ethtool.h| 55 include/standard-headers/linux/pci_regs.h

[PULL 29/46] hw/cxl/cxl-mailbox-utils: Add superset extent release mailbox support

From: Fan Ni With the change, we extend the extent release mailbox command processing to allow more flexible release. As long as the DPA range of the extent to release is covered by accepted extent(s) in the device, the release can be performed. Tested-by: Svetly Todorov Reviewed-by: Gregory Pr

[PULL 12/46] hw/virtio: Fix obtain the buffer id from the last descriptor

From: Wafer The virtio-1.3 specification writes: 2.8.6 Next Flag: Descriptor Chaining Buffer ID is included in the last descriptor in the list. If the feature (_F_INDIRECT_DESC) has been negotiated, install only one descript

[PULL 25/46] hw/mem/cxl_type3: Add DC extent list representative and get DC extent list mailbox support

From: Fan Ni Add dynamic capacity extent list representative to the definition of CXLType3Dev and implement get DC extent list mailbox command per CXL.spec.3.1:.8.2.9.9.9.2. Tested-by: Svetly Todorov Reviewed-by: Jonathan Cameron Signed-off-by: Fan Ni Message-Id: <20240523174651.1089554-10-ni

[PULL 20/46] hw/cxl/cxl-mailbox-utils: Add dynamic capacity region representative and mailbox command support

From: Fan Ni Per cxl spec r3.1, add dynamic capacity (DC) region representative based on Table 8-165 and extend the cxl type3 device definition to include DC region information. Also, based on info in 8.2.9.9.9.1, add 'Get Dynamic Capacity Configuration' mailbox support. Note: we store region de

[PULL 39/46] hw/misc/pvpanic: centralize definition of supported events

From: Thomas Weißschuh The different components of pvpanic duplicate the list of supported events. Move it to the shared header file to minimize changes when new events are added. Reviewed-by: Thomas Huth Reviewed-by: Cornelia Huck Signed-off-by: Thomas Weißschuh Message-Id: <20240527-pvpanic

[PULL 00/46] virtio: features,fixes

The following changes since commit 60b54b67c63d8f076152e0f7dccf39854dfc6a77: Merge tag 'pull-lu-20240526' of https://gitlab.com/rth7680/qemu into staging (2024-05-26 17:51:00 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_upstrea

[PULL 31/46] hw/acpi/GI: Fix trivial parameter alignment issue.

From: Jonathan Cameron Before making additional modification, tidy up this misleading indentation. Reviewed-by: Ankit Agrawal Signed-off-by: Jonathan Cameron Message-Id: <20240524100507.32106-2-jonathan.came...@huawei.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin ---

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