Re: [PATCH v5 20/24] replay: simple auto-snapshot mode for record

On 18.03.2024 18:46, Nicholas Piggin wrote: record makes an initial snapshot when the machine is created, to enable reverse-debugging. Often the issue being debugged appears near the end of the trace, so it is important for performance to keep snapshots close to the end. This implements a period

Re: [PATCH v5 10/24] virtio-net: Use replay_schedule_bh_event for bhs that affect machine state

Reviewed-by: Pavel Dovgalyuk On 18.03.2024 18:46, Nicholas Piggin wrote: The regular qemu_bh_schedule() calls result in non-deterministic execution of the bh in record-replay mode, which causes replay failure. Signed-off-by: Nicholas Piggin --- hw/net/virtio-net.c | 11 ++- 1 file

Re: [RFC PATCH-for-9.1] qapi: Do not generate commands/events/introspect code for user emulation

Philippe Mathieu-Daudé writes: > User emulation requires the QAPI types. Due to the command > line processing, some visitor code is also used. The rest > is irrelevant (no QMP socket). > > Add an option to the qapi-gen script to allow generating > the minimum when only user emulation is being bui

RE: [PATCH v2] migration/postcopy: ensure preempt channel is ready before loading states

On Friday, April 5, 2024 11:41 AM, Wang, Wei W wrote: > > Before loading the guest states, ensure that the preempt channel has been > ready to use, as some of the states (e.g. via virtio_load) might trigger page > faults that will be handled through the preempt channel. So yield to the main > thre

[PATCH v2] migration/postcopy: ensure preempt channel is ready before loading states

Before loading the guest states, ensure that the preempt channel has been ready to use, as some of the states (e.g. via virtio_load) might trigger page faults that will be handled through the preempt channel. So yield to the main thread in the case that the channel create event hasn't been dispatch

RE: [PATCH v1] migration/postcopy: ensure preempt channel is ready before loading states

On Friday, April 5, 2024 10:33 AM, Peter Xu wrote: > On Fri, Apr 05, 2024 at 01:38:31AM +, Wang, Wei W wrote: > > On Friday, April 5, 2024 4:57 AM, Peter Xu wrote: > > > On Fri, Apr 05, 2024 at 12:48:15AM +0800, Wang, Lei wrote: > > > > On 4/5/2024 0:25, Wang, Wei W wrote:> On Thursday, April 4

Re: [PATCH v1] migration/postcopy: ensure preempt channel is ready before loading states

On Fri, Apr 05, 2024 at 01:38:31AM +, Wang, Wei W wrote: > On Friday, April 5, 2024 4:57 AM, Peter Xu wrote: > > On Fri, Apr 05, 2024 at 12:48:15AM +0800, Wang, Lei wrote: > > > On 4/5/2024 0:25, Wang, Wei W wrote:> On Thursday, April 4, 2024 10:12 > > > PM, Peter Xu wrote: > > > >> On Thu, Apr

RE: [PATCH v1] migration/postcopy: ensure preempt channel is ready before loading states

On Friday, April 5, 2024 4:57 AM, Peter Xu wrote: > On Fri, Apr 05, 2024 at 12:48:15AM +0800, Wang, Lei wrote: > > On 4/5/2024 0:25, Wang, Wei W wrote:> On Thursday, April 4, 2024 10:12 > > PM, Peter Xu wrote: > > >> On Thu, Apr 04, 2024 at 06:05:50PM +0800, Wei Wang wrote: > > >>> Before loading t

Re: [PATCH v2] riscv: thead: Add th.sxstatus CSR emulation

On 2024/3/29 20:04, Christoph Müllner wrote: The th.sxstatus CSR can be used to identify available custom extension on T-Head CPUs. The CSR is documented here: https://github.com/T-head-Semi/thead-extension-spec/pull/46 An important property of this patch is, that the th.sxstatus MAEE field

[PATCH v11 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

The current implementation treats emulated memory devices, such as CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory (E820_TYPE_RAM). However, these emulated devices have different characteristics than traditional DRAM, making it important to distinguish them. Thus, we mod

[PATCH v11 1/2] memory tier: dax/kmem: introduce an abstract layer for finding, allocating, and putting memory types

Since different memory devices require finding, allocating, and putting memory types, these common steps are abstracted in this patch, enhancing the scalability and conciseness of the code. Signed-off-by: Ho-Ren (Jack) Chuang Reviewed-by: "Huang, Ying" --- drivers/dax/kmem.c | 30

[PATCH v11 0/2] Improved Memory Tier Creation for CPUless NUMA Nodes

When a memory device, such as CXL1.1 type3 memory, is emulated as normal memory (E820_TYPE_RAM), the memory device is indistinguishable from normal DRAM in terms of memory tiering with the current implementation. The current memory tiering assigns all detected normal memory nodes to the same DRAM t

[PATCH v2 16/21] plugins: Introduce PLUGIN_CB_MEM_REGULAR

Use different enumerators for vcpu_udata and vcpu_mem callbacks. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/qemu/plugin.h | 1 + accel/tcg/plugin-gen.c | 2 +- plugins/core.c | 4 ++-- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/includ

[PATCH v2 13/21] tcg: Remove TCG_CALL_PLUGIN

Since we no longer emit plugin helpers during the initial code translation phase, we don't need to specially mark plugin helpers. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 2 -- plugins/core.c| 10 -- tcg/tcg.c | 4 +--- 3 files

[PATCH v2 20/21] plugins: Inline plugin_gen_empty_callback

Each caller can use tcg_gen_plugin_cb directly. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- accel/tcg/plugin-gen.c | 19 +++ 1 file changed, 3 insertions(+), 16 deletions(-) diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index c0cbc26984..d914d64

[PATCH v2 15/21] plugins: Simplify callback queues

We have qemu_plugin_dyn_cb.type to differentiate the various callback types, so we do not need to keep them in separate queues. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/qemu/plugin.h | 35 ++-- accel/tcg/plugin-gen.c | 90 ++

[PATCH v2 17/21] plugins: Replace pr_ops with a proper debug dump flag

The DEBUG_PLUGIN_GEN_OPS ifdef is replaced with "-d op_plugin". The second pr_ops call can be obtained with "-d op". Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/qemu/log.h | 1 + include/tcg/tcg.h | 1 + accel/tcg/plugin-gen.c | 67 +++--

[PATCH v2 04/21] plugins: Zero new qemu_plugin_dyn_cb entries

Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- plugins/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plugins/core.c b/plugins/core.c index 11ca20e626..4487cb7c48 100644 --- a/plugins/core.c +++ b/plugins/core.c @@ -307,7 +307,7 @@ static struct qemu_pl

[PATCH v2 10/21] plugins: Use emit_before_op for PLUGIN_GEN_FROM_INSN

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/qemu/plugin.h | 1 - accel/tcg/plugin-gen.c | 286 ++--- plugins/api.c | 8 +- 3 files changed, 67 insertions(+), 228 deletions(-) diff --git a/include/qemu/plugin.h b/in

[PATCH v2 12/21] plugins: Remove plugin helpers

These placeholder helpers are no longer required. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- accel/tcg/plugin-helpers.h | 5 - include/exec/helper-gen-common.h | 4 include/exec/helper-proto-common.h | 4 accel/tcg/plugin-gen.c | 20

[PATCH v2 03/21] tcg: Pass function pointer to tcg_gen_call*

For normal helpers, read the function pointer from the structure earlier. For plugins, this will allow the function pointer to come from elsewhere. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 21 +--- include/exec/helper-gen.h.inc |

[PATCH v2 21/21] plugins: Update the documentation block for plugin-gen.c

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/plugin-gen.c | 31 --- 1 file changed, 4 insertions(+), 27 deletions(-) diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index d914d64de0..3db74ae9bf 100644 --- a/accel/tcg/plugi

[PATCH v2 19/21] plugins: Merge qemu_plugin_tb_insn_get to plugin-gen.c

Merge qemu_plugin_insn_alloc and qemu_plugin_tb_insn_get into plugin_gen_insn_start, since it is used nowhere else. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/qemu/plugin.h | 39 --- accel/tcg/plugin-gen.c | 39 +++

[PATCH v2 11/21] plugins: Use emit_before_op for PLUGIN_GEN_FROM_MEM

Introduce a new plugin_mem_cb op to hold the address temp and meminfo computed by tcg-op-ldst.c. Because this now has its own opcode, we no longer need PLUGIN_GEN_FROM_MEM. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/exec/plugin-gen.h | 4 - include/tcg/tcg-o

[PATCH v2 18/21] plugins: Split out common cb expanders

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/plugin-gen.c | 84 +- 1 file changed, 41 insertions(+), 43 deletions(-) diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 49d9b07438..5b63b93114 100644 --- a/acc

[PATCH v2 14/21] tcg: Remove INDEX_op_plugin_cb_{start,end}

These opcodes are no longer used. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-opc.h | 2 -- accel/tcg/plugin-gen.c | 18 -- tcg/tcg-op.c| 10 -- 4 files changed, 32 de

[PATCH v2 09/21] plugins: Add PLUGIN_GEN_AFTER_TB

Delay test of plugin_tb->mem_helper until the inject pass. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/plugin-gen.c | 37 - 1 file changed, 16 insertions(+), 21 deletions(-) diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plu

[PATCH v2 08/21] plugins: Use emit_before_op for PLUGIN_GEN_FROM_TB

By having the qemu_plugin_cb_flags be recorded in the TCGHelperInfo, we no longer need to distinguish PLUGIN_CB_REGULAR from PLUGIN_CB_REGULAR_R, so place all TB callbacks in the same queue. Signed-off-by: Richard Henderson --- accel/tcg/plugin-gen.c | 96 +---

[PATCH v2 07/21] plugins: Use emit_before_op for PLUGIN_GEN_AFTER_INSN

Introduce a new plugin_cb op and migrate one operation. By using emit_before_op, we do not need to emit opcodes early and modify them later -- we can simply emit the final set of opcodes once. Signed-off-by: Richard Henderson --- include/tcg/tcg-op-common.h | 1 + include/tcg/tcg-opc.h |

[PATCH v2 00/21] Rewrite plugin code generation

Add a (trivial) mechanism for emitting code into the middle of the opcode sequence: tcg_ctx->emit_before_op. Rip out all of the "empty" generation and "copy" to modify those sequences. Replace with regular code generation once we know what values to place. Changes for v2: * Fix TCI build failu

[PATCH v2 01/21] tcg: Add TCGContext.emit_before_op

Allow operations to be emitted via normal expanders into the middle of the opcode stream. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 6 ++ tcg/tcg.c | 14 -- 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/incl

[PATCH v2 05/21] plugins: Move function pointer in qemu_plugin_dyn_cb

The out-of-line function pointer is mutually exclusive with inline expansion, so move it into the union. Wrap the pointer in a structure named 'regular' to match PLUGIN_CB_REGULAR. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/qemu/plugin.h | 4 +++- accel/tcg/plugin-ge

[PATCH v2 02/21] tcg: Make tcg/helper-info.h self-contained

Move MAX_CALL_IARGS from tcg.h and include for the define of TCG_TARGET_REG_BITS. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/tcg/helper-info.h | 3 +++ include/tcg/tcg.h | 2 -- tcg/tci.c | 1 + 3 files changed, 4 insertions(+), 2 deletions(-)

[PATCH v2 06/21] plugins: Create TCGHelperInfo for all out-of-line callbacks

TCGHelperInfo includes the ABI for every function call. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/qemu/plugin.h | 1 + plugins/core.c| 51 ++- 2 files changed, 46 insertions(+), 6 deletions(-) diff --git a/includ

Re: [PATCH v2] sh4: mac.l: implement saturation arithmetic logic

Signed-off-by: Zack Buhman - Original message - From: "Philippe Mathieu-Daudé" To: Peter Maydell , Zack Buhman Cc: qemu-devel@nongnu.org, Yoshinori Sato Subject: Re: [PATCH v2] sh4: mac.l: implement saturation arithmetic logic Date: Friday, April 05, 2024 1:26 AM Hi Zack, Cc'ing the

Re: [PATCH-for-9.1 2/7] yank: Restrict to system emulation

On 4/4/24 09:47, Philippe Mathieu-Daudé wrote: The yank feature is not used in user emulation. Signed-off-by: Philippe Mathieu-Daudé --- util/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Richard Henderson r~

Re: [PATCH-for-9.1 1/7] ebpf: Restrict to system emulation

On 4/4/24 09:47, Philippe Mathieu-Daudé wrote: eBPF is not used in user emulation. Signed-off-by: Philippe Mathieu-Daudé --- ebpf/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Richard Henderson r~

Re: [External] Re: [PATCH v10 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

Hi Jonathan, Thank you! I will fix them and send a V11 soon. On Thu, Apr 4, 2024 at 6:37 AM Jonathan Cameron wrote: > > > > > > > @@ -858,7 +910,8 @@ static int __init memory_tier_init(void) > > > >* For now we can have 4 faster memory tiers with smaller > > > > adistance > > > >

[PATCH for-9.0] tcg/optimize: Do not attempt to constant fold neg_vec

Split out the tail of fold_neg to fold_neg_no_const so that we can avoid attempting to constant fold vector negate. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2150 Signed-off-by: Richard Henderson --- tcg/optimize.c| 17 - tests/tcg/aarch64/test-2

Re: [PATCH v1] migration/postcopy: ensure preempt channel is ready before loading states

On Fri, Apr 05, 2024 at 12:48:15AM +0800, Wang, Lei wrote: > On 4/5/2024 0:25, Wang, Wei W wrote:> On Thursday, April 4, 2024 10:12 PM, > Peter > Xu wrote: > >> On Thu, Apr 04, 2024 at 06:05:50PM +0800, Wei Wang wrote: > >>> Before loading the guest states, ensure that the preempt channel has > >>

[RFC PATCH-for-9.1] qapi: Do not generate commands/events/introspect code for user emulation

User emulation requires the QAPI types. Due to the command line processing, some visitor code is also used. The rest is irrelevant (no QMP socket). Add an option to the qapi-gen script to allow generating the minimum when only user emulation is being built. Signed-off-by: Philippe Mathieu-Daudé

[PATCH-for-9.1 2/7] yank: Restrict to system emulation

The yank feature is not used in user emulation. Signed-off-by: Philippe Mathieu-Daudé --- util/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/meson.build b/util/meson.build index 0ef9886be0..247f55a80d 100644 --- a/util/meson.build +++ b/util/meson.build @@

[PATCH-for-9.1 1/7] ebpf: Restrict to system emulation

eBPF is not used in user emulation. Signed-off-by: Philippe Mathieu-Daudé --- ebpf/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ebpf/meson.build b/ebpf/meson.build index c5bf9295a2..bff6156f51 100644 --- a/ebpf/meson.build +++ b/ebpf/meson.build @@ -1 +1 @@ -co

[PATCH-for-9.1 5/7] hw/core: Restrict reset handlers API to system emulation

Headers in include/sysemu/ are specific to system emulation and should not be used in user emulation. Signed-off-by: Philippe Mathieu-Daudé --- hw/core/reset.c | 4 1 file changed, 4 insertions(+) diff --git a/hw/core/reset.c b/hw/core/reset.c index d50da7e304..167c8bf1a9 100644 --- a/hw/c

[PATCH-for-9.1 6/7] hw/core: Move reset.c to hwcore_ss[] source set

reset.c contains core code used by any CPU, required by user emulation. Move it to hwcore_ss[] where it belongs. Signed-off-by: Philippe Mathieu-Daudé --- hw/core/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/core/meson.build b/hw/core/meson.build index e26f2

[PATCH-for-9.1 7/7] hw: Include minimal source set in user emulation build

Only the files in hwcore_ss[] are required to link a user emulation binary. Have meson process the hw/ sub-directories if system emulation is selected, otherwise directly process hw/core/ to get hwcore_ss[], which is the only set required by user emulation. Signed-off-by: Philippe Mathieu-Daudé

[PATCH-for-9.1 4/7] util/qemu-config: Extract QMP commands to qemu-config-qmp.c

QMP is irrelevant for user emulation. Extract the code related to QMP in a different source file, which won't be build for user emulation binaries. This avoid pulling pointless code. Signed-off-by: Philippe Mathieu-Daudé --- include/qemu/config-file.h | 3 + util/qemu-config-qmp.c | 206 ++

[PATCH-for-9.1 0/7] buildsys: Start shrinking qemu-user build process

Hi, While reworking include/exec/ I have to build many configs to be sure nothing breaks. qemu-user is particularly sensitive to changes in this directory (mostly because all user-specific files include "qemu.h", itself including various exec/ headers). Getting tired of this waste I had a look at

[PATCH-for-9.1 3/7] monitor: Rework stubs to simplify user emulation linking

Currently monitor stubs are scattered in 3 files. Merge these stubs in 2 files, a generic one (monitor-core) included in all builds (in particular user emulation), and a less generic one to be included by tools and system emulation. Signed-off-by: Philippe Mathieu-Daudé --- stubs/fdset.c

[PATCH-for-9.0 1/4] hw/virtio: Introduce virtio_bh_new_guarded() helper

Introduce virtio_bh_new_guarded(), similar to qemu_bh_new_guarded() but using the transport memory guard, instead of the device one (there can only be one virtio device per virtio bus). Inspired-by: Gerd Hoffmann Signed-off-by: Philippe Mathieu-Daudé --- include/hw/virtio/virtio.h | 7 +++

[PATCH-for-9.0 4/4] hw/virtio/virtio-crypto: Protect from DMA re-entrancy bugs

Replace qemu_bh_new_guarded() by virtio_bh_new_guarded() so the bus and device use the same guard. Otherwise the DMA-reentrancy protection can be bypassed. Cc: qemu-sta...@nongnu.org Suggested-by: Alexander Bulekov Signed-off-by: Philippe Mathieu-Daudé --- hw/virtio/virtio-crypto.c | 4 ++-- 1

[PATCH-for-9.0 3/4] hw/char/virtio-serial-bus: Protect from DMA re-entrancy bugs

Replace qemu_bh_new_guarded() by virtio_bh_new_guarded() so the bus and device use the same guard. Otherwise the DMA-reentrancy protection can be bypassed. Cc: qemu-sta...@nongnu.org Suggested-by: Alexander Bulekov Signed-off-by: Philippe Mathieu-Daudé --- hw/char/virtio-serial-bus.c | 3 +-- 1

[PATCH-for-9.0 2/4] hw/display/virtio-gpu: Protect from DMA re-entrancy bugs

Replace qemu_bh_new_guarded() by virtio_bh_new_guarded() so the bus and device use the same guard. Otherwise the DMA-reentrancy protection can be bypassed: $ cat << EOF | qemu-system-i386 -display none -nodefaults \ -machine q35,accel=qtest \

[PATCH-for-9.0 0/4] hw/virtio: Protect from more DMA re-entrancy bugs

Gerd suggested to use the transport guard to protect the device from DMA re-entrancy abuses. Philippe Mathieu-Daudé (4): hw/virtio: Introduce virtio_bh_new_guarded() helper hw/display/virtio-gpu: Protect from DMA re-entrancy bugs hw/char/virtio-serial-bus: Protect from DMA re-entrancy bugs

Re: Intention to work on GSoC project

Hi, On Thursday, April 4, 2024 12:07:49 AM IST Eugenio Perez Martin wrote: > On Wed, Apr 3, 2024 at 4:36 PM Sahil wrote: > [...] > > I would like to clarify one thing in the figure "Full two-entries > > descriptor table". The driver can only overwrite a used descriptor in the > > descriptor ring,

[PATCH] target/arm: Fix CNTPOFF_EL2 trap to missing EL3

EL2 accesses to CNTPOFF_EL2 should only ever trap to EL3 if EL3 is present, as described by the reference manual (for MRS): /* ... */ elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && /*...*/ then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.ECVEn == '0' then

Re: [PULL 00/17] qemu-sparc queue 20240404

ilable in the Git repository at: > > https://github.com/mcayland/qemu.git tags/qemu-sparc-20240404 > > for you to fetch changes up to d7fe931818d5e9aa70d08056c43b496ce789ba64: > > esp.c: remove explicit setting of DRQ withi

Re: [PULL for-9.0 0/1] Block patches

On Thu, 4 Apr 2024 at 14:58, Stefan Hajnoczi wrote: > > The following changes since commit 786fd793b81410fb2a28914315e2f05d2ff6733b: > > Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging > (2024-04-03 12:52:03 +0100) > > are available in the Git repository at: > > https

Re: [PATCH v2] sh4: mac.l: implement saturation arithmetic logic

Hi Zack, Cc'ing the maintainer of this file, Yoshinori: $ ./scripts/get_maintainer.pl -f target/sh4/op_helper.c Yoshinori Sato (reviewer:SH4 TCG CPUs) (https://www.qemu.org/docs/master/devel/submitting-a-patch.html#cc-the-relevant-maintainer) On 4/4/24 18:39, Peter Maydell wrote: On Thu, 4 Ap

[PATCH v2] hw/virtio: Fix packed virtqueue flush used_idx

If a virtio-net device has the VIRTIO_NET_F_MRG_RXBUF feature but not the VIRTIO_RING_F_INDIRECT_DESC feature, 'VirtIONetQueue->rx_vq' will use the merge feature to store data in multiple 'elems'. The 'num_buffers' in the virtio header indicates how many elements are merged. If the value of 'num_bu

Re: [PATCH v1] migration/postcopy: ensure preempt channel is ready before loading states

On 4/5/2024 0:25, Wang, Wei W wrote:> On Thursday, April 4, 2024 10:12 PM, Peter Xu wrote: >> On Thu, Apr 04, 2024 at 06:05:50PM +0800, Wei Wang wrote: >>> Before loading the guest states, ensure that the preempt channel has >>> been ready to use, as some of the states (e.g. via virtio_load) might

Re: [PATCH v2] sh4: mac.l: implement saturation arithmetic logic

On Thu, 4 Apr 2024 at 17:26, Zack Buhman wrote: > > The saturation arithmetic logic in helper_macl is not correct. > > I tested and verified this behavior on a SH7091, the general pattern > is a code sequence such as: > > sets > > mov.l _mach,r2 > lds r2,mach > mov.

Re: [RFC v2 1/5] virtio: Initialize sequence variables

On Thu, Apr 4, 2024 at 4:42 PM Jonah Palmer wrote: > > > > On 4/4/24 7:35 AM, Eugenio Perez Martin wrote: > > On Wed, Apr 3, 2024 at 6:51 PM Jonah Palmer wrote: > >> > >> > >> > >> On 4/3/24 6:18 AM, Eugenio Perez Martin wrote: > >>> On Thu, Mar 28, 2024 at 5:22 PM Jonah Palmer > >>> wrote: > >

[PATCH v2] sh4: mac.l: implement saturation arithmetic logic

The saturation arithmetic logic in helper_macl is not correct. I tested and verified this behavior on a SH7091, the general pattern is a code sequence such as: sets mov.l _mach,r2 lds r2,mach mov.l _macl,r2 lds r2,macl mova _n,r0 mov r0,r1

RE: [PATCH v1] migration/postcopy: ensure preempt channel is ready before loading states

On Thursday, April 4, 2024 10:12 PM, Peter Xu wrote: > On Thu, Apr 04, 2024 at 06:05:50PM +0800, Wei Wang wrote: > > Before loading the guest states, ensure that the preempt channel has > > been ready to use, as some of the states (e.g. via virtio_load) might > > trigger page faults that will be ha

Re: [PATCH] sh4: mac.l: implement saturation arithmetic logic

On Thu, 4 Apr 2024 at 16:12, Zack Buhman wrote: > > The saturation arithmetic logic in helper_macl is not correct. > > I tested and verified this behavior on a SH7091, the general pattern > is a code sequence such as: > > sets > > mov.l _mach,r2 > lds r2,mach > mov.

[PATCH] sh4: mac.l: implement saturation arithmetic logic

The saturation arithmetic logic in helper_macl is not correct. I tested and verified this behavior on a SH7091, the general pattern is a code sequence such as: sets mov.l _mach,r2 lds r2,mach mov.l _macl,r2 lds r2,macl mova _n,r0 mov r0,r1

Re: [PATCH v12 10/23] hw/arm/virt: Wire NMI and VINMI irq lines from GIC to CPU

On Wed, 3 Apr 2024 at 11:18, Jinjie Ruan wrote: > > Wire the new NMI and VINMI interrupt line from the GIC to each CPU. > > Signed-off-by: Jinjie Ruan > Reviewed-by: Richard Henderson > --- > v9: > - Rename ARM_CPU_VNMI to ARM_CPU_VINMI. > - Update the commit message. > v4: > - Add Reviewed-by.

Re: [RFC v2 1/5] virtio: Initialize sequence variables

On 4/4/24 7:35 AM, Eugenio Perez Martin wrote: On Wed, Apr 3, 2024 at 6:51 PM Jonah Palmer wrote: On 4/3/24 6:18 AM, Eugenio Perez Martin wrote: On Thu, Mar 28, 2024 at 5:22 PM Jonah Palmer wrote: Initialize sequence variables for VirtQueue and VirtQueueElement structures. A VirtQueue

Re: [PATCH v12 00/23] target/arm: Implement FEAT_NMI and FEAT_GICv3_NMI

On Wed, 3 Apr 2024 at 11:18, Jinjie Ruan wrote: > > This patch set implements FEAT_NMI and FEAT_GICv3_NMI for ARMv8. These > introduce support for a new category of interrupts in the architecture > which we can use to provide NMI like functionality. Looking through the Arm ARM pseudocode at place

[PULL 07/17] esp.c: use esp_fifo_push() instead of fifo8_push()

There are still a few places that use fifo8_push() instead of esp_fifo_push() in order to push a value into the FIFO. Update those places to use esp_fifo_push() instead. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Paolo Bonzini Message-Id: <20240324191707.62

[PULL 08/17] esp.c: change esp_fifo_pop_buf() to take ESPState

Now that all users of esp_fifo_pop_buf() operate on the main FIFO there is no need to pass the FIFO explicitly. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Paolo Bonzini Message-Id: <20240324191707.623175-9-mark.cave-ayl...@ilande.co.uk> Signed-off-by: Mark

[PULL 13/17] esp.c: move esp_set_phase() and esp_get_phase() towards the beginning of the file

This allows these functions to be used earlier in the file without needing a separate forward declaration. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Paolo Bonzini Message-Id: <20240324191707.623175-14-mark.cave-ayl...@ilande.co.uk> Signed-off-by: Mark Cave

[PULL 15/17] esp.c: update esp_fifo_{push, pop}() to call esp_update_drq()

This ensures that the DRQ line is always set correctly when reading/writing single bytes to/from the FIFO. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Paolo Bonzini Message-Id: <20240324191707.623175-16-mark.cave-ayl...@ilande.co.uk> Signed-off-by: Mark Cave

[PULL 17/17] esp.c: remove explicit setting of DRQ within ESP state machine

Now the esp_update_drq() is called for all reads/writes to the FIFO, there is no need to manually raise and lower the DRQ signal. Signed-off-by: Mark Cave-Ayland Resolves: https://gitlab.com/qemu-project/qemu/-/issues/611 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1831 Reviewed-by: P

[PULL 10/17] esp.c: don't assert() if FIFO empty when executing non-DMA SELATNS

The current logic assumes that at least 1 byte is present in the FIFO when executing a non-DMA SELATNS command, but this may not be the case if the guest executes an invalid ESP command sequence. Reported-by: Chuhong Yuan Signed-off-by: Mark Cave-Ayland Reviewed-by: Paolo Bonzini Reviewed-by: P

[PULL 03/17] esp.c: replace esp_fifo_pop_buf() with esp_fifo8_pop_buf() in do_message_phase()

The aim is to restrict the esp_fifo_*() functions so that they only operate on the hardware FIFO. When reading from cmdfifo in do_message_phase() use the underlying esp_fifo8_pop_buf() function directly. Signed-off-by: Mark Cave-Ayland Reviewed-by: Paolo Bonzini Reviewed-by: Philippe Mathieu-Dau

[PULL 16/17] esp.c: ensure esp_pdma_write() always calls esp_fifo_push()

This ensures that esp_update_drq() is called via esp_fifo_push() whenever the host uses PDMA to transfer data to a SCSI device. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Paolo Bonzini Message-Id: <20240324191707.623175-17-mark.cave-ayl...@ilande.co.uk> Sig

[PULL 02/17] esp.c: replace esp_fifo_pop_buf() with esp_fifo8_pop_buf() in do_command_phase()

The aim is to restrict the esp_fifo_*() functions so that they only operate on the hardware FIFO. When reading from cmdfifo in do_command_phase() use the underlying esp_fifo8_pop_buf() function directly. Signed-off-by: Mark Cave-Ayland Reviewed-by: Paolo Bonzini Reviewed-by: Philippe Mathieu-Dau

[PULL 14/17] esp.c: introduce esp_update_drq() and update esp_fifo_{push, pop}_buf() to use it

This new function sets the DRQ line correctly according to the current transfer mode, direction and FIFO contents. Update esp_fifo_push_buf() and esp_fifo_pop_buf() to use it so that DRQ is always set correctly when reading/writing multiple bytes to/from the FIFO. Signed-off-by: Mark Cave-Ayland

[PULL 05/17] esp.c: change esp_fifo_push() to take ESPState

Now that all users of esp_fifo_push() operate on the main FIFO there is no need to pass the FIFO explicitly. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Paolo Bonzini Message-Id: <20240324191707.623175-6-mark.cave-ayl...@ilande.co.uk> Signed-off-by: Mark Cav

Re: [PATCH v12 18/23] hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read()

On Wed, 3 Apr 2024 at 11:18, Jinjie Ruan wrote: > > Implement icv_nmiar1_read() for icc_nmiar1_read(), so add definition for > ICH_LR_EL2.NMI and ICH_AP1R_EL2.NMI bit. > > If FEAT_GICv3_NMI is supported, ich_ap_write() should consider > ICV_AP1R_EL1.NMI > bit. In icv_activate_irq() and icv_eoir_w

[PULL 11/17] esp.c: rework esp_cdb_length() into esp_cdb_ready()

The esp_cdb_length() function is only used as part of a calculation to determine whether the cmdfifo contains an entire SCSI CDB. Rework esp_cdb_length() into a new esp_cdb_ready() function which both enables us to handle the case where scsi_cdb_length() returns -1, plus simplify the logic for its

[PULL 09/17] esp.c: introduce esp_fifo_push_buf() function for pushing to the FIFO

Instead of pushing data into the FIFO directly with fifo8_push_all(), add a new esp_fifo_push_buf() function and use it accordingly. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Paolo Bonzini Message-Id: <20240324191707.623175-10-mark.cave-ayl...@ilande.co.uk

[PULL 01/17] esp.c: move esp_fifo_pop_buf() internals to new esp_fifo8_pop_buf() function

Update esp_fifo_pop_buf() to be a simple wrapper onto the new esp_fifo8_pop_buf() function. Signed-off-by: Mark Cave-Ayland Reviewed-by: Paolo Bonzini Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20240324191707.623175-2-mark.cave-ayl...@ilande.co.uk> Signed-off-by: Mark Cave-Ayland --- h

[PULL 12/17] esp.c: prevent cmdfifo overflow in esp_cdb_ready()

During normal use the cmdfifo will never wrap internally and cmdfifo_cdb_offset will always indicate the start of the SCSI CDB. However it is possible that a malicious guest could issue an invalid ESP command sequence such that cmdfifo wraps internally and cmdfifo_cdb_offset could point beyond the

[PULL 00/17] qemu-sparc queue 20240404

The following changes since commit 786fd793b81410fb2a28914315e2f05d2ff6733b: Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2024-04-03 12:52:03 +0100) are available in the Git repository at: https://github.com/mcayland/qemu.git tags/qemu-sparc-2024040

[PULL 06/17] esp.c: change esp_fifo_pop() to take ESPState

Now that all users of esp_fifo_pop() operate on the main FIFO there is no need to pass the FIFO explicitly. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Paolo Bonzini Message-Id: <20240324191707.623175-7-mark.cave-ayl...@ilande.co.uk> Signed-off-by: Mark Cave

[PULL 04/17] esp.c: replace cmdfifo use of esp_fifo_pop() in do_message_phase()

Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Paolo Bonzini Message-Id: <20240324191707.623175-5-mark.cave-ayl...@ilande.co.uk> Signed-off-by: Mark Cave-Ayland --- hw/scsi/esp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/scsi/esp

Re: [PATCH v12 17/23] hw/intc/arm_gicv3: Add NMI handling CPU interface registers

On Wed, 3 Apr 2024 at 11:17, Jinjie Ruan wrote: > > Add the NMIAR CPU interface registers which deal with acknowledging NMI. > > When introduce NMI interrupt, there are some updates to the semantics for the > register ICC_IAR1_EL1 and ICC_HPPIR1_EL1. For ICC_IAR1_EL1 register, it > should return 1

Re: [PATCH v12 12/23] target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64()

On Wed, 3 Apr 2024 at 11:18, Jinjie Ruan wrote: > > According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt > with superpriority is always IRQ, never FIQ, so the NMI exception trap entry > behave like IRQ. And VINMI(vIRQ with Superpriority) can be raised from the > GIC or come fr

Re: [PATCH v12 09/23] target/arm: Handle PSTATE.ALLINT on taking an exception

On Wed, 3 Apr 2024 at 11:17, Jinjie Ruan wrote: > > Set or clear PSTATE.ALLINT on taking an exception to ELx according to the > SCTLR_ELx.SPINTMASK bit. > > Signed-off-by: Jinjie Ruan > Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH v12 08/23] target/arm: Handle IS/FS in ISR_EL1 for NMI, VINMI and VFNMI

On Wed, 3 Apr 2024 at 11:18, Jinjie Ruan wrote: > > Add IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI or > CPU_INTERRUPT_VINMI, both CPSR_I and ISR_IS must be set. With > CPU_INTERRUPT_VFNMI, both CPSR_F and ISR_FS must be set. > > Signed-off-by: Jinjie Ruan > Reviewed-by:

Re: [PATCH v12 07/23] target/arm: Add support for NMI in arm_phys_excp_target_el()

On Wed, 3 Apr 2024 at 11:18, Jinjie Ruan via wrote: > > According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt > with superpriority is always IRQ, never FIQ, so handle NMI same as IRQ in > arm_phys_excp_target_el(). > > Signed-off-by: Jinjie Ruan > Reviewed-by: Richard Henderso

Re: [PATCH v12 04/23] target/arm: Implement ALLINT MSR (immediate)

On Wed, 3 Apr 2024 at 11:18, Jinjie Ruan wrote: > > Add ALLINT MSR (immediate) to decodetree, in which the CRm is 0b000x. The > EL0 check is necessary to ALLINT, and the EL1 check is necessary when > imm == 1. So implement it inline for EL2/3, or EL1 with imm==0. Avoid the > unconditional write to

Re: [PATCH v12 02/23] target/arm: Add PSTATE.ALLINT

On Wed, 3 Apr 2024 at 11:17, Jinjie Ruan wrote: > > When PSTATE.ALLINT is set, an IRQ or FIQ interrupt that is targeted to > ELx, with or without superpriority is masked. > > As Richard suggested, place ALLINT bit in PSTATE in env->pstate. > > With the change to pstate_read/write, exception entry

Re: [PATCH v12 03/23] target/arm: Add support for FEAT_NMI, Non-maskable Interrupt

On Wed, 3 Apr 2024 at 11:18, Jinjie Ruan wrote: > > Add support for FEAT_NMI. NMI (FEAT_NMI) is an mandatory feature in > ARMv8.8-A and ARM v9.3-A. > > Signed-off-by: Jinjie Ruan > Reviewed-by: Richard Henderson > --- > v3: > - Add Reviewed-by. > - Adjust to before the MSR patches. > --- > targ

Re: [PATCH v12 06/23] target/arm: Add support for Non-maskable Interrupt

On Wed, 3 Apr 2024 at 11:17, Jinjie Ruan wrote: > > This only implements the external delivery method via the GICv3. > > Signed-off-by: Jinjie Ruan > Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH v12 01/23] target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NMI

On Wed, 3 Apr 2024 at 11:17, Jinjie Ruan wrote: > > FEAT_NMI defines another three new bits in HCRX_EL2: TALLINT, HCRX_VINMI and > HCRX_VFNMI. When the feature is enabled, allow these bits to be written in > HCRX_EL2. > > Signed-off-by: Jinjie Ruan > Reviewed-by: Richard Henderson > --- Reviewe

Re: [PATCH v12 05/23] target/arm: Support MSR access to ALLINT

On Wed, 3 Apr 2024 at 11:17, Jinjie Ruan wrote: > > Support ALLINT msr access as follow: > mrs , ALLINT// read allint > msr ALLINT, // write allint with imm > > Signed-off-by: Jinjie Ruan > Reviewed-by: Richard Henderson > --- Reviewed-by: Peter Maydell thanks

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