On 3/21/24 20:28, Richard Henderson wrote:
Do not clobber the high bits of the address by using a 32-bit deposit.
Signed-off-by: Richard Henderson
Reviewed-by: Helge Deller
Helge
---
target/hppa/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/hppa
In case of migration, during restore operation, qemu checks config space of the
pci device with the config space in the migration stream captured during save
operation. In case of config space data mismatch, restore operation is failed.
config space check is done in function get_pci_config_device(
Justinien Bouron writes:
> Depending on your use-case, it might be inconvenient to have qemu grab
> the input device from the host immediately upon starting the guest.
>
> Added a new bool option to input-linux: grab-on-startup. If true, the
> device is grabbed as soon as the guest is started, ot
On Fri, Feb 16, 2024 at 6:50 AM Igor Lesik wrote:
>
> Hi,
>
> I have a situation when I need to use third-party 32-bit RISC-V CPU when rest
> is all 64-bit RISC-V CPUs. I have seen that some steps were already made in
> the direction to enable such configuration
> (https://riscv.org/blog/2023/0
On Thu, Mar 21, 2024 at 8:50 PM wrote:
>
> From: Frank Chang
>
> Currently, QEMU only sets the iforce register to 0 and returns early
> when claiming the iforce register. However, this may leave mip.meip
> remains at 1 if a spurious external interrupt triggered by iforce
> register is the only pe
On Fri, Mar 22, 2024 at 5:43 AM Si-Wei Liu wrote:
>
>
>
> On 3/20/2024 8:56 PM, Jason Wang wrote:
> > On Thu, Mar 21, 2024 at 5:03 AM Si-Wei Liu wrote:
> >>
> >>
> >> On 3/19/2024 8:27 PM, Jason Wang wrote:
> >>> On Tue, Mar 19, 2024 at 6:16 AM Si-Wei Liu wrote:
>
> On 3/17/2024 8:22 P
On 2024/3/22 2:28, Peter Maydell wrote:
> On Thu, 21 Mar 2024 at 15:46, Peter Maydell wrote:
>> Something somewhere needs to implement "if SCTLR_ELx.NMI is 0 then
>> we don't take EXCP_VINMI etc but instead (maybe) EXCP_VIRQ etc".
>> At the moment nothing does that:
>> * arm_cpu_update_vinmi()
On Tue, Mar 12, 2024 at 11:55 PM Fei Wu wrote:
>
> The RISC-V Server Platform specification[1] defines a standardized set
> of hardware and software capabilities, that portable system software,
> such as OS and hypervisors can rely on being present in a RISC-V server
> platform.
>
> A correspondin
21.03.2024 21:32, Helge Deller wrote:
On 3/21/24 19:25, Sven Schnelle wrote:
Michael Tokarev writes:
20.03.2024 03:32, Richard Henderson :
Richard Henderson (3):
target/hppa: Fix assemble_16 insns for wide mode
target/hppa: Fix assemble_11a insns for wide mode
target
On Thu, Mar 14, 2024 at 4:17 PM Yong-Xuan Wang wrote:
>
> The timebase-frequency of guest OS should be the same with host
> machine. The timebase-frequency value in DTS should be got from
> hypervisor when using KVM acceleration.
>
> Reviewed-by: Andrew Jones
> Signed-off-by: Yong-Xuan Wang
Tha
On Thu, Mar 14, 2024 at 4:17 PM Yong-Xuan Wang wrote:
>
> The timebase-frequency of guest OS should be the same with host
> machine. The timebase-frequency value in DTS should be got from
> hypervisor when using KVM acceleration.
>
> Reviewed-by: Andrew Jones
> Signed-off-by: Yong-Xuan Wang
Rev
On Thu, Mar 21, 2024 at 3:29 AM Irina Ryapolova
wrote:
>
> Need to convert mmu_idx to privilege mode for PMP function.
>
> Signed-off-by: Irina Ryapolova
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
On Thu, Mar 21, 2024 at 3:29 AM Irina Ryapolova
wrote:
>
> Need to convert mmu_idx to privilege mode for PMP function.
>
> Signed-off-by: Irina Ryapolova
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff
On Fri, Mar 22, 2024 at 3:16 AM Max Chou wrote:
>
> According to the Zvfbfmin definition in the RISC-V BF16 extensions spec,
> the Zvfbfmin extension only requires either the V extension or the
> Zve32f extension.
>
> Signed-off-by: Max Chou
Thanks!
Applied to riscv-to-apply.next
Alistair
> -
On Fri, Mar 22, 2024 at 3:16 AM Max Chou wrote:
>
> According to the Zvfbfmin definition in the RISC-V BF16 extensions spec,
> the Zvfbfmin extension only requires either the V extension or the
> Zve32f extension.
Yeah, the dependency has been removed
https://github.com/riscv/riscv-bfloat16/comm
On Wed, Mar 20, 2024 at 5:28 PM Max Chou wrote:
>
> When SEW is 16, we need to check whether the Zvfhmin is enabled for the
> single width operator for vector floating point widen/narrow
> instructions.
>
> The commits in this patchset fix the single width operator checking and
> remove the reduda
On Thu, Mar 21, 2024 at 8:50 PM wrote:
>
> From: Frank Chang
>
> Currently, QEMU only sets the iforce register to 0 and returns early
> when claiming the iforce register. However, this may leave mip.meip
> remains at 1 if a spurious external interrupt triggered by iforce
> register is the only pe
On Wed, Mar 20, 2024 at 7:33 PM Daniel Henrique Barboza
wrote:
>
> We're not setting (s/m)tval when triggering breakpoints of type 2
> (mcontrol) and 6 (mcontrol6). According to the debug spec section
> 5.7.12, "Match Control Type 6":
>
> "The Privileged Spec says that breakpoint exceptions that o
On 2024/3/21 23:46, Peter Maydell wrote:
> On Thu, 21 Mar 2024 at 13:10, Jinjie Ruan wrote:
>>
>> This only implements the external delivery method via the GICv3.
>>
>> Signed-off-by: Jinjie Ruan
>> Reviewed-by: Richard Henderson
>> ---
>> v9:
>> - Update the GPIOs passed in the arm_cpu_kvm_s
Depending on your use-case, it might be inconvenient to have qemu grab
the input device from the host immediately upon starting the guest.
Added a new bool option to input-linux: grab-on-startup. If true, the
device is grabbed as soon as the guest is started, otherwise it is not
grabbed until the
On 2024/3/21 21:17, Peter Maydell wrote:
> On Mon, 18 Mar 2024 at 09:38, Jinjie Ruan wrote:
>>
>> A SPI, PPI or SGI interrupt can have a superpriority property. So
>> maintain superpriority information in PendingIrq and GICR/GICD.
>>
>> Signed-off-by: Jinjie Ruan
>> Acked-by: Richard Henderson
On Wed, 20 Mar 2024 00:24:37 +0300, "Vladimir Sementsov-Ogievskiy"
wrote:
> Hi all!
>
> From fuzzing I've got a fuzz-data, which produces the following crash:
>
> qemu-fuzz-x86_64: ../hw/net/virtio-net.c:134: void
> flush_or_purge_queued_packets(NetClientState *): Assertion
> `!virtio_net_get_
On Thu, 21 Mar 2024 09:54:30 -0700, Breno Leitao wrote:
> There is a bug when setting the RSS options in virtio_net that can break
> the whole machine, getting the kernel into an infinite loop.
>
> Running the following command in any QEMU virtual machine with virtionet
> will reproduce this probl
> -Original Message-
> From: Peter Xu
> Sent: Thursday, March 21, 2024 11:28 PM
> To: Liu, Yuan1
> Cc: Daniel P. Berrangé ; faro...@suse.de; qemu-
> de...@nongnu.org; hao.xi...@bytedance.com; bryan.zh...@bytedance.com; Zou,
> Nanhai
> Subject: Re: [PATCH v5 5/7] migration/multifd: implem
On Wed, Mar 20, 2024 at 11:19 PM Peter Xu wrote:
> On Wed, Mar 20, 2024 at 07:49:07AM +0100, Cédric Le Goater wrote:
> > Now that the log_global*() handlers take an Error** parameter and
> > return a bool, do the same for memory_global_dirty_log_start() and
> > memory_global_dirty_log_stop(). The
在 2024/3/22 上午1:13, Michael Tokarev 写道:
20.03.2024 05:40, Song Gao :
On gen_ll, if a->imm is zero, make_address_x return src1,
but the load to destination may clobber src1. We use a new
destination to fix this problem.
Fixes: c5af6628f4be (target/loongarch: Extract make_address_i() helper)
Revi
Hi Phil,
I submitted revised series (v4) based on your v3 work. I tried to address 2 or
3 major issues you mentioned there and some minor corrections.
Please check it. I appreciate your help and feedback.
[PATCH v4 0/3] ui/console: Introduce helpers for creating and
> -Original Message-
From: Dongwon Kim
dpy_gl_dmabuf_get_height() and dpy_gl_dmabuf_get_width() are helpers for
retrieving width and height fields from QemuDmaBuf struct.
Cc: Philippe Mathieu-Daudé
Cc: Marc-André Lureau
Cc: Vivek Kasireddy
Signed-off-by: Dongwon Kim
---
include/ui/console.h| 2 ++
From: Dongwon Kim
dpy_gl_dmabuf_get_fd() is a helper for retrieving FD of the dmabuf
from QemuDmaBuf struct.
Cc: Philippe Mathieu-Daudé
Cc: Marc-André Lureau
Cc: Vivek Kasireddy
Signed-off-by: Dongwon Kim
---
include/ui/console.h | 1 +
hw/vfio/display.c| 8 +++-
ui/console.c
From: Dongwon Kim
dpy_gl_create_dmabuf() allocates QemuDmaBuf and initialize fields.
hw/display modules, hw/vfio and ui/dbus-listener now use this method
to create QemuDmaBuf instead of declaring and initializing it on their
own.
Cc: Philippe Mathieu-Daudé
Cc: Marc-André Lureau
Cc: Vivek Kasir
From: Dongwon Kim
QemuDmaBuf struct is defined and primarily used by ui/console/gl so it is
better to handle its creation, initialization and access within ui/console
rather than within hw modules such as hw/display/virtio-gpu,
hw/display/vhost-user-gpu and hw/vfio as well as ui/dbus-listener.
v
On 3/21/24 05:48, Philippe Mathieu-Daudé wrote:
Move APIC related code split in cpu-sysemu.c and
monitor.c to cpu-apic.c.
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/cpu-apic.c | 112 +++
target/i386/cpu-sysemu.c | 77 --
On 3/21/24 05:48, Philippe Mathieu-Daudé wrote:
Keep all HMP commands in monitor.c.
Signed-off-by: Philippe Mathieu-Daudé
---
target/m68k/cpu.h | 3 +-
target/m68k/helper.c | 222 -
target/m68k/monitor.c | 223 +++
On 3/21/24 05:48, Philippe Mathieu-Daudé wrote:
Slightly simplify dump_mmu() by passing the description as
argument to dump_ttr().
Signed-off-by: Philippe Mathieu-Daudé
---
target/m68k/helper.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
Reviewed-by: Richard Hender
On 3/21/24 05:48, Philippe Mathieu-Daudé wrote:
Replace qemu_printf() by monitor_printf() / monitor_puts() in monitor.
Signed-off-by: Philippe Mathieu-Daudé
---
target/m68k/cpu.h | 2 +-
target/m68k/helper.c | 126 +-
target/m68k/monitor.c | 4
On 3/21/24 05:48, Philippe Mathieu-Daudé wrote:
hmp_info_tlb() is specific to tcg/system, move it to
target/i386/tcg/sysemu/hmp-cmds.c, along with the functions
it depend on (except addr_canonical() which is exposed in
"cpu.h").
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/cpu.h
This update changes how virtio_snd_handle_tx_xfer handles message size
discrepancies and null streams. Instead of using error handling paths
which led to unnecessary processing and potential null pointer dereferences,
the function now continues to the next loop iteration.
ASAN log illustrating the
On 3/20/2024 8:56 PM, Jason Wang wrote:
On Thu, Mar 21, 2024 at 5:03 AM Si-Wei Liu wrote:
On 3/19/2024 8:27 PM, Jason Wang wrote:
On Tue, Mar 19, 2024 at 6:16 AM Si-Wei Liu wrote:
On 3/17/2024 8:22 PM, Jason Wang wrote:
On Sat, Mar 16, 2024 at 2:45 AM Si-Wei Liu wrote:
On 3/14/2024
On 3/21/24 3:48 PM, Dongli Zhang wrote:
Hi Jonah,
Would you mind helping explain how does VIRTIO_F_IN_ORDER improve the
performance?
https://lore.kernel.org/all/20240321155717.1392787-1-jonah.pal...@oracle.com/#t
I tried to look for it from prior discussions but could not find why.
https:
On 3/21/24 05:48, Philippe Mathieu-Daudé wrote:
Commit fd3f7d24d4 ("include/hw/core: Remove i386 conditional
on fake_user_interrupt") remove the need to check on NEED_CPU_H.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/tcg-cpu-ops.h | 2 --
1 file changed, 2 deletions(-)
Review
On 3/21/24 10:10, Sven Schnelle wrote:
Richard Henderson writes:
On 3/21/24 08:42, Sven Schnelle wrote:
Wide mode provides two more conditions, add them.
Signed-off-by: Sven Schnelle
---
target/hppa/translate.c | 25 +++--
1 file changed, 23 insertions(+), 2 deletion
On Thu, Mar 21, 2024 at 05:12:42PM -0300, Fabiano Rosas wrote:
> When the zero page detection is done in the multifd threads, we need
> to iterate the second part of the pages->offset array and clear the
> file bitmap for each zero page. The piece of code we merged to do that
> is wrong.
>
> The r
On Wed, Mar 20, 2024 at 03:38:56AM -0500, Michael Roth wrote:
>
> Testing
> ---
>
> This series has been tested against the following host kernel tree, which
> is a snapshot of the latest WIP SNP hypervisor tree at the time of this
> posting. It will likely not be kept up to date afterward, s
On Wed, Mar 20, 2024 at 09:04:52PM +0100, David Hildenbrand wrote:
> On 20.03.24 18:38, Michael Roth wrote:
> > On Wed, Mar 20, 2024 at 10:37:14AM +0100, David Hildenbrand wrote:
> > > On 20.03.24 09:39, Michael Roth wrote:
> > > > From: Xiaoyao Li
> > > >
> > > > When memory page is converted fr
When the zero page detection is done in the multifd threads, we need
to iterate the second part of the pages->offset array and clear the
file bitmap for each zero page. The piece of code we merged to do that
is wrong.
The reason this has passed all the tests is because the bitmap is
initialized wi
Richard Henderson writes:
> On 3/21/24 08:42, Sven Schnelle wrote:
>> Wide mode provides two more conditions, add them.
>> Signed-off-by: Sven Schnelle
>> ---
>> target/hppa/translate.c | 25 +++--
>> 1 file changed, 23 insertions(+), 2 deletions(-)
>> diff --git a/target/
Richard Henderson writes:
> On 3/21/24 08:42, Sven Schnelle wrote:
>> Signed-off-by: Sven Schnelle
>> ---
>> target/hppa/translate.c | 3 +++
>> 1 file changed, 3 insertions(+)
>> diff --git a/target/hppa/translate.c b/target/hppa/translate.c
>> index f493e207e1..4d2b96f876 100644
>> --- a/ta
On 3/21/24 08:42, Sven Schnelle wrote:
Wide mode provides two more conditions, add them.
Signed-off-by: Sven Schnelle
---
target/hppa/translate.c | 25 +++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
i
On 3/21/24 09:34, Philippe Mathieu-Daudé wrote:
On 21/3/24 20:28, Richard Henderson wrote:
Do not clobber the high bits of the address by using a 32-bit deposit.
Signed-off-by: Richard Henderson
---
target/hppa/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/
On 3/21/24 08:42, Sven Schnelle wrote:
Signed-off-by: Sven Schnelle
---
target/hppa/translate.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 4d2b96f876..74a9ea0cd8 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translat
On 3/21/24 08:42, Sven Schnelle wrote:
Signed-off-by: Sven Schnelle
---
target/hppa/translate.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index f493e207e1..4d2b96f876 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translat
Hi Jonah,
Would you mind helping explain how does VIRTIO_F_IN_ORDER improve the
performance?
https://lore.kernel.org/all/20240321155717.1392787-1-jonah.pal...@oracle.com/#t
I tried to look for it from prior discussions but could not find why.
https://lore.kernel.org/all/byapr18mb2791df7e6c0f61
On 21/3/24 20:28, Richard Henderson wrote:
Do not clobber the high bits of the address by using a 32-bit deposit.
Signed-off-by: Richard Henderson
---
target/hppa/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
On 240321 2208, Vladimir Sementsov-Ogievskiy wrote:
> On 21.03.24 18:01, Alexander Bulekov wrote:
> > On 240320 0024, Vladimir Sementsov-Ogievskiy wrote:
> > > Hi all!
> > >
> > > From fuzzing I've got a fuzz-data, which produces the following crash:
> > >
> > > qemu-fuzz-x86_64: ../hw/net/virti
Do not clobber the high bits of the address by using a 32-bit deposit.
Signed-off-by: Richard Henderson
---
target/hppa/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 1766a63001..f875d76a23 100644
--- a/targ
The return address comes from IA*Q_Next, and IASQ_Next
is always equal to IASQ_Back, not IASQ_Front.
Signed-off-by: Richard Henderson
---
target/hppa/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 19594f917e
Using the correct space for BE,L linkage might make the difference
for a cpu stress test. I believe triggering this would require
something like
f=(seg,ofs), b=(seg,ofs+4)
be 0(sr1,r1) f=(seg,ofs+4), b=(sr1,r1)
be,l,n 0(s
On 21.03.24 18:01, Alexander Bulekov wrote:
On 240320 0024, Vladimir Sementsov-Ogievskiy wrote:
Hi all!
From fuzzing I've got a fuzz-data, which produces the following crash:
qemu-fuzz-x86_64: ../hw/net/virtio-net.c:134: void
flush_or_purge_queued_packets(NetClientState *): Assertion
`!virt
Signed-off-by: Sven Schnelle
---
target/hppa/translate.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 4d2b96f876..74a9ea0cd8 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -1122,6 +1122,9 @@ static void do_ad
Wide mode provides two more conditions, add them.
Signed-off-by: Sven Schnelle
---
target/hppa/translate.c | 25 +++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 8a87996fc1..f493e207e1 100644
--- a/ta
Signed-off-by: Sven Schnelle
---
target/hppa/translate.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index f493e207e1..4d2b96f876 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -1213,6 +1213,9 @@ static void do_su
On 27/2/24 17:47, BALATON Zoltan wrote:
Hello,
Commit 18a536f1f8 (accel/tcg: Always require can_do_io) broke booting
MorphOS on sam460ex (this was before 8.2.0 and I thought I've verified
it before that release but apparently missed it back then). It can be
reproduced with https://www.morphos
On 3/21/24 19:25, Sven Schnelle wrote:
Michael Tokarev writes:
20.03.2024 03:32, Richard Henderson :
Richard Henderson (3):
target/hppa: Fix assemble_16 insns for wide mode
target/hppa: Fix assemble_11a insns for wide mode
target/hppa: Fix assemble_12a insns for wide
On Thu, 21 Mar 2024 at 15:46, Peter Maydell wrote:
> Something somewhere needs to implement "if SCTLR_ELx.NMI is 0 then
> we don't take EXCP_VINMI etc but instead (maybe) EXCP_VIRQ etc".
> At the moment nothing does that:
> * arm_cpu_update_vinmi() doesn't look at the NMI bit before
>deciding
Michael Tokarev writes:
> 20.03.2024 03:32, Richard Henderson :
>
>> Richard Henderson (3):
>>target/hppa: Fix assemble_16 insns for wide mode
>>target/hppa: Fix assemble_11a insns for wide mode
>>target/hppa: Fix assemble_12a insns for wide mode
>> Sven Schnelle (6):
>>
On Thu, 21 Mar 2024 at 13:10, Jinjie Ruan wrote:
>
> Add ALLINT MSR (immediate) to decodetree, in which the CRm is 0b000x. The
> EL0 check is necessary to ALLINT, and the EL1 check is necessary when
> imm == 1. So implement it inline for EL2/3, or EL1 with imm==0. Avoid the
> unconditional write t
On Thu, 21 Mar 2024 at 17:18, Richard Henderson
wrote:
>
> On 3/20/24 23:32, Michael Tokarev wrote:
> > Since commit v8.1.0-511-g399e5e7125 "target/arm: Implement FEAT_PACQARMA3",
> > pauth-qarma3 is the default pauth scheme. However this one is very slow.
>
> That patch only introduced qarma3, i
The following changes since commit fea445e8fe9acea4f775a832815ee22bdf2b0222:
Merge tag 'pull-maintainer-final-for-real-this-time-200324-1' of
https://gitlab.com/stsquad/qemu into staging (2024-03-21 10:31:56 +)
are available in the Git repository at:
https://gitlab.com/stefanha/qemu.git
Daniel P. Berrangé pointed out that the coroutine
pool size heuristic is very conservative. Instead of halving
max_map_count, he suggested reserving 5,000 mappings for non-coroutine
users based on observations of guests he has access to.
Fixes: 86a637e48104 ("coroutine: cap per-thread local pool
On 3/20/24 23:32, Michael Tokarev wrote:
Since commit v8.1.0-511-g399e5e7125 "target/arm: Implement FEAT_PACQARMA3",
pauth-qarma3 is the default pauth scheme. However this one is very slow.
That patch only introduced qarma3, it didn't make it the default:
static Property arm_cpu_pauth_proper
20.03.2024 11:36, Tao Su :
monitor_puts() doesn't check the monitor pointer, but do_inject_x86_mce()
may have a parameter with NULL monitor pointer. Revert monitor_puts() in
do_inject_x86_mce() to fix, then the fact that we send the same message to
monitor and log is again more obvious.
Fixes: b
On 21/3/24 17:01, Cédric Le Goater wrote:
Coverity detected an "Integer handling" issue with the pin value :
In expression "state >> pin", right shifting "state" by more than 7
bits always yields zero. The shift amount, "pin", is as much as 8.
In practice, this should not happen because
According to the Zvfbfmin definition in the RISC-V BF16 extensions spec,
the Zvfbfmin extension only requires either the V extension or the
Zve32f extension.
Signed-off-by: Max Chou
---
target/riscv/tcg/tcg-cpu.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/target/riscv/tcg/tcg-cpu.c
On Wed, Mar 20, 2024 at 02:12:32PM -0400, Stefan Hajnoczi wrote:
> Daniel P. Berrangé pointed out that the coroutine
> pool size heuristic is very conservative. Instead of halving
> max_map_count, he suggested reserving 5,000 mappings for non-coroutine
> users based on observations of guests he ha
20.03.2024 05:40, Song Gao :
On gen_ll, if a->imm is zero, make_address_x return src1,
but the load to destination may clobber src1. We use a new
destination to fix this problem.
Fixes: c5af6628f4be (target/loongarch: Extract make_address_i() helper)
Reviewed-by: Richard Henderson
Suggested-by:
On 3/21/24 05:48, Philippe Mathieu-Daudé wrote:
qatomic_cmpxchg__nocheck(), qatomic_read__nocheck(),
qatomic_set__nocheck() are defined in "qemu/atomic.h".
Include it in order to avoid:
In file included from include/exec/helper-proto.h:10:
In file included from include/exec/helper-proto-co
20.03.2024 05:40, Song Gao :
From: Xianglai Li
+if (unlikely((level == 0) || (level > 4))) {
+qemu_log_mask(LOG_GUEST_ERROR,
+ "Attepted LDDIR with level %"PRId64"\n", level);
Attempted. FWIW, it's applied already.
/mjt
20.03.2024 03:32, Richard Henderson :
Richard Henderson (3):
target/hppa: Fix assemble_16 insns for wide mode
target/hppa: Fix assemble_11a insns for wide mode
target/hppa: Fix assemble_12a insns for wide mode
Sven Schnelle (6):
target/hppa: ldcw,s uses static shift
On Thu, 21 Mar 2024 at 08:22, Kevin Wolf wrote:
>
> Am 20.03.2024 um 15:09 hat Daniel P. Berrangé geschrieben:
> > On Wed, Mar 20, 2024 at 09:35:39AM -0400, Stefan Hajnoczi wrote:
> > > On Tue, Mar 19, 2024 at 08:10:49PM +, Daniel P. Berrangé wrote:
> > > > On Tue, Mar 19, 2024 at 01:55:10PM -
There is a bug when setting the RSS options in virtio_net that can break
the whole machine, getting the kernel into an infinite loop.
Running the following command in any QEMU virtual machine with virtionet
will reproduce this problem:
# ethtool -X eth0 hfunc toeplitz
This is how the pr
On Thu, 21 Mar 2024 at 13:10, Jinjie Ruan wrote:
>
> This patch set implements FEAT_NMI and FEAT_GICv3_NMI for armv8. These
> introduce support for a new category of interrupts in the architecture
> which we can use to provide NMI like functionality.
>
> There are two modes for using this FEAT_NMI
On Wed, Mar 20, 2024 at 05:44:53PM -0400, pet...@redhat.com wrote:
> From: Peter Xu
>
> On current code base I can observe extremely high sync count during
> precopy, as long as one enables postcopy-ram=on before switchover to
> postcopy.
>
> To provide some context of when we decide to do a ful
On 3/21/24 17:08, Miles Glenn wrote:
On Thu, 2024-03-21 at 17:01 +0100, Cédric Le Goater wrote:
Coverity detected an "Integer handling" issue with the pin value :
In expression "state >> pin", right shifting "state" by more than 7
bits always yields zero. The shift amount, "pin", is as m
From: aidaleuc
Signed-off-by: aidaleuc
---
qga/commands-posix-ssh.c | 47 +--
qga/commands-ssh-core.c| 57
qga/commands-ssh-core.h| 8 +
qga/commands-windows-ssh.c | 66 +-
qga/meson.buil
On Thu, 2024-03-21 at 17:01 +0100, Cédric Le Goater wrote:
> Coverity detected an "Integer handling" issue with the pin value :
>
> In expression "state >> pin", right shifting "state" by more than 7
> bits always yields zero. The shift amount, "pin", is as much as 8.
>
> In practice, this s
From: aidaleuc
Signed-off-by: aidaleuc
---
qga/commands-windows-ssh.c | 848 +
qga/commands-windows-ssh.h | 26 ++
qga/meson.build| 9 +-
qga/qapi-schema.json | 22 +-
4 files changed, 892 insertions(+), 13 deletions(-)
create mode 1006
From: aidaleuc
This patch aims to implement guest-ssh-add-authorized-keys,
guest-ssh-remove-authorized-keys, and guest-ssh-get-authorized-keys
for Windows. This PR is based on Microsoft's OpenSSH implementation
https://github.com/PowerShell/Win32-OpenSSH. The guest agents
will support Kubevirt
Coverity detected an "Integer handling" issue with the pin value :
In expression "state >> pin", right shifting "state" by more than 7
bits always yields zero. The shift amount, "pin", is as much as 8.
In practice, this should not happen because the properties "pin8" and
above are not create
Define the InOrderVQElement structure for the VIRTIO_F_IN_ORDER
transport feature implementation.
The InOrderVQElement structure is used to encapsulate out-of-order
VirtQueueElement data that was processed by the host. This data
includes:
- The processed VirtQueueElement (elem)
- Length of data
Extend the virtio device property definitions to include the
VIRTIO_F_IN_ORDER feature.
The default state of this feature is disabled, allowing it to be
explicitly enabled where it's supported.
Signed-off-by: Jonah Palmer
---
include/hw/virtio/virtio.h | 4 +++-
1 file changed, 3 insertions(+),
Implements in-order handling for the virtio-net device.
Since virtio-net utilizes batching for its Rx VirtQueue, the device is
responsible for calling virtqueue_flush once it has completed its
batching operation.
Note:
-
It's unclear if this implementation is really necessary to "guarantee"
t
The goal of these patches is to add support to a variety of virtio and
vhost devices for the VIRTIO_F_IN_ORDER transport feature. This feature
indicates that all buffers are used by the device in the same order in
which they were made available by the driver.
These patches attempt to implement a g
Implements in-order handling for vhost devices using shadow virtqueues.
Since vhost's shadow virtqueues utilize batching in their
vhost_svq_flush calls, the vhost device is responsible for calling
virtqueue_flush once it has completed its batching operation.
Note:
-
It's unclear if this imple
Define order variables for their use in a VirtQueue's in-order hash
table. Also initialize current_order variables to 0 when creating or
resetting a VirtQueue. These variables are used when the device has
negotiated the VIRTIO_F_IN_ORDER transport feature.
A VirtQueue's current_order_idx represent
Define a GLib hash table (GHashTable) member in a device's VirtQueue
and add its creation, destruction, and reset functions appropriately.
Also define a function to handle the deallocation of InOrderVQElement
values whenever they're removed from the hash table or the hash table
is destroyed. This h
Add support for the VIRTIO_F_IN_ORDER feature across a variety of vhost
devices.
The inclusion of VIRTIO_F_IN_ORDER in the feature bits arrays for these
devices ensures that the backend is capable of offering and providing
support for this feature, and that it can be disabled if the backend
does n
Implements in-order handling for most virtio devices using the
VIRTIO_F_IN_ORDER transport feature, specifically those who call
virtqueue_push to push their used elements onto the used ring.
The logic behind this implementation is as follows:
1.) virtqueue_pop always enqueues VirtQueueElements in
Replace qemu_printf() by monitor_printf() / monitor_puts() in monitor.
Signed-off-by: Philippe Mathieu-Daudé
---
target/xtensa/mmu.h | 2 +-
target/xtensa/monitor.c | 117
2 files changed, 61 insertions(+), 58 deletions(-)
diff --git a/target/xtens
Replace qemu_printf() by monitor_printf() in monitor.c.
Rename dump_mmu() as sparc_dump_mmu().
Signed-off-by: Philippe Mathieu-Daudé
---
target/sparc/cpu.h | 2 +-
target/sparc/ldst_helper.c | 18 +++
target/sparc/mmu_helper.c | 102 ++---
target/s
Extract sh4_dump_mmu() from hmp_info_tlb(), replacing
monitor_printf(FIXED_STRING_WITHOUT_FORMAT) by monitor_puts().
Signed-off-by: Philippe Mathieu-Daudé
---
target/sh4/cpu.h | 2 ++
target/sh4/monitor.c | 22 +++---
2 files changed, 17 insertions(+), 7 deletions(-)
diff -
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