> On 05-Mar-2024, at 21:27, Igor Mammedov wrote:
>
> it will help to keep type 4 tables accounting correct in case
> SMBIOS tables are built multiple times.
I suggest you arrange this before patch 15 where you are actually calling
smbios_get_tables_ep() multiple times. That way there is no
Sorry, manual is updated already and we do not notice that still.
https://www.loongson.cn/uploads/images/2023102309132647981.%E9%BE%99%E8%8A%AF%E6%9E%B6%E6%9E%84%E5%8F%82%E8%80%83%E6%89%8B%E5%86%8C%E5%8D%B7%E4%B8%80_r1p10.pdf
It is Chinese web link, English manual is not updated. Here is English
On Wed, Mar 06, 2024 at 08:07:31AM +0100, Eugenio Perez Martin wrote:
> On Wed, Mar 6, 2024 at 6:34 AM Jason Wang wrote:
> >
> > On Tue, Mar 5, 2024 at 3:46 AM Jonah Palmer wrote:
> > >
> > > The goal of these patches are to add support to a variety of virtio and
> > > vhost devices for the VIRTI
> On 05-Mar-2024, at 21:27, Igor Mammedov wrote:
>
> basically moving code around without functional change.
> And exposing some symbols so that they could be shared
> between smbbios.c and new smbios_legacy.c
>
> plus some meson magic to build smbios_legacy.c only
> for 'pc' machine and othe
On Tue, 5 Mar 2024, Igor Mammedov wrote:
> As a preparation to move legacy handling into a separate file,
> add prefix 'smbios_' to type0/type1/have_binfile_bitmap/have_fields_bitmap
> and expose them in smbios.h so that they can be reused in
> legacy and modern code.
>
> Doing it as a separate
On Wed, Mar 6, 2024 at 6:34 AM Jason Wang wrote:
>
> On Tue, Mar 5, 2024 at 3:46 AM Jonah Palmer wrote:
> >
> > The goal of these patches are to add support to a variety of virtio and
> > vhost devices for the VIRTIO_F_NOTIFICATION_DATA transport feature. This
> > feature indicates that a driver
> On 05-Mar-2024, at 21:27, Igor Mammedov wrote:
>
> it will be used by follow up patch when legacy handling
> is moved out into a separate file.
>
> Signed-off-by: Igor Mammedov
Reviewed-by: Ani Sinha
> ---
> hw/smbios/smbios.c | 18 ++
> 1 file changed, 14 insertions(+),
On 6/3/24 00:39, Richard Henderson wrote:
Fixes Coverity CID: 1534962
Fixes: 243c4706625 ("linux-user/elfload: Write corefile elf header in one
block")
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
Reviewed-
On 6/3/24 00:39, Richard Henderson wrote:
Fixes Coverity CID: 1534964
Fixes: 106f8da664 ("linux-user/elfload: Open core file after vma_init")
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daud
On Tue, 5 Mar 2024, Igor Mammedov wrote:
> currently smbios_entry_add() preserves internally '-smbios type='
> options but tables provided with '-smbios file=' are stored directly
> into blob that eventually will be exposed to VM. And then later
> QEMU adds default/'-smbios type' entries on top
This removes the need to enumarate QEMUCPUState twice and saves code.
Signed-off-by: Akihiko Odaki
Reviewed-by: Peter Maydell
---
contrib/elf2dmp/qemu_elf.c | 25 -
1 file changed, 8 insertions(+), 17 deletions(-)
diff --git a/contrib/elf2dmp/qemu_elf.c b/contrib/elf2dm
pa_space_create() used to return an integer to propagate error, but
it never fails so let it return void.
Signed-off-by: Akihiko Odaki
---
contrib/elf2dmp/addrspace.h | 2 +-
contrib/elf2dmp/addrspace.c | 4 +---
contrib/elf2dmp/main.c | 5 +
3 files changed, 3 insertions(+), 8 deletion
Let fill_context() continue even if it fails to fill contexts of some
CPUs. A dump may still contain valuable information even if it lacks
contexts of some CPUs due to dump corruption or a failure before
starting CPUs.
Signed-off-by: Akihiko Odaki
Reviewed-by: Peter Maydell
---
contrib/elf2dmp/
This fixes crashes with truncated dumps.
Signed-off-by: Akihiko Odaki
Reviewed-by: Peter Maydell
---
contrib/elf2dmp/qemu_elf.c | 87 +-
1 file changed, 55 insertions(+), 32 deletions(-)
diff --git a/contrib/elf2dmp/qemu_elf.c b/contrib/elf2dmp/qemu_
include/qapi/error.h says:
> We recommend
> * bool-valued functions return true on success / false on failure,
> ...
Signed-off-by: Akihiko Odaki
---
contrib/elf2dmp/download.h | 2 +-
contrib/elf2dmp/download.c | 10 +-
contrib/elf2dmp/main.c | 2 +-
3 files changed, 7 insertions(
The relevant value may be unaligned and is little-endian.
Signed-off-by: Akihiko Odaki
---
contrib/elf2dmp/pdb.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/contrib/elf2dmp/pdb.c b/contrib/elf2dmp/pdb.c
index 1c5051425185..492aca4434c8 100644
--- a/contrib/elf2dmp/pdb.c
include/qapi/error.h says:
> We recommend
> * bool-valued functions return true on success / false on failure,
> ...
Signed-off-by: Akihiko Odaki
---
contrib/elf2dmp/qemu_elf.h | 2 +-
contrib/elf2dmp/main.c | 2 +-
contrib/elf2dmp/qemu_elf.c | 32
3 files
include/qapi/error.h says:
> We recommend
> * bool-valued functions return true on success / false on failure,
> ...
Signed-off-by: Akihiko Odaki
---
contrib/elf2dmp/pdb.h | 2 +-
contrib/elf2dmp/main.c | 2 +-
contrib/elf2dmp/pdb.c | 50 +-
3
for little
endian host".
- Added patch "contrib/elf2dmp: Ensure phdrs fit in file" to fix
https://gitlab.com/qemu-project/qemu/-/issues/2202 as patch
"contrib/elf2dmp: Clamp QEMU note to file size" was not really fixing
the crash.
- Link to v2:
https://lore.kernel.org
Destroy PA space even if paging base couldn't be found, fixing memory
leak.
Signed-off-by: Akihiko Odaki
Reviewed-by: Peter Maydell
---
contrib/elf2dmp/main.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/contrib/elf2dmp/main.c b/contrib/elf2dmp/main.c
index c290781feb18
Not checking PA resolution failure can result in NULL deference.
Signed-off-by: Akihiko Odaki
Reviewed-by: Peter Maydell
---
contrib/elf2dmp/addrspace.c | 46 -
1 file changed, 29 insertions(+), 17 deletions(-)
diff --git a/contrib/elf2dmp/addrspace.
On Wed, Mar 06, 2024 at 10:19:41AM +0530, Prasad Pandit wrote:
> Date: Wed, 6 Mar 2024 10:19:41 +0530
> From: Prasad Pandit
> Subject: Re: [PATCH] hw/core/machine-smp: Remove deprecated "parameter=0"
> SMP configurations
>
> Hello Zhao,
>
> On Wed, 6 Mar 2024 at 08:49, Zhao Liu wrote:
> >> the
Callers of elf64_getphdr() and elf_getphdrnum() assume phdrs are
accessible.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2202
Signed-off-by: Akihiko Odaki
---
contrib/elf2dmp/qemu_elf.c | 8
1 file changed, 8 insertions(+)
diff --git a/contrib/elf2dmp/qemu_elf.c b/contrib/e
include/qapi/error.h says:
> We recommend
> * bool-valued functions return true on success / false on failure,
> ...
Signed-off-by: Akihiko Odaki
---
contrib/elf2dmp/main.c | 63 +-
1 file changed, 32 insertions(+), 31 deletions(-)
diff --git a/co
elf2dmp assumes little endian host in many places. Build it only for
little endian hosts until they are fixed.
Signed-off-by: Akihiko Odaki
---
contrib/elf2dmp/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/contrib/elf2dmp/meson.build b/contrib/elf2dmp/meson.buil
Signed-off-by: Akihiko Odaki
Reviewed-by: Peter Maydell
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 65dfdc9677e4..d25403f3709b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3583,6 +3583,7 @@ F: util/iova-tree.c
elf2dmp
M: Viktor Prutya
This makes elf2dmp more robust against corrupted inputs.
Signed-off-by: Akihiko Odaki
Reviewed-by: Peter Maydell
---
contrib/elf2dmp/addrspace.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/contrib/elf2dmp/addrspace.c b/contrib/elf2dmp/addrspace.c
index e01860d15b07.
rol64() is roubust against too large shift values and fixes UBSan
warnings.
Signed-off-by: Akihiko Odaki
Reviewed-by: Peter Maydell
---
contrib/elf2dmp/main.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/contrib/elf2dmp/main.c b/contrib/elf2dmp/main.c
index 51e1ab
include/qapi/error.h says:
> We recommend
> * bool-valued functions return true on success / false on failure,
> ...
Signed-off-by: Akihiko Odaki
---
contrib/elf2dmp/addrspace.h | 4 ++--
contrib/elf2dmp/addrspace.c | 8
contrib/elf2dmp/main.c | 47 +--
A common construct in contrib/elf2dmp is to set "err" flag and goto
in error paths. In such a construct, there is only one successful path
while there are several error paths, so it will be more simpler to
initialize "err" flag set, and clear it in the successful path.
Signed-off-by: Akihiko Odaki
They are always evaluated to 1.
Signed-off-by: Akihiko Odaki
Reviewed-by: Peter Maydell
---
contrib/elf2dmp/pdb.c | 14 +++---
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/contrib/elf2dmp/pdb.c b/contrib/elf2dmp/pdb.c
index 40991f5f4c34..abf17c2e7c12 100644
--- a/contr
...after some testing...
[Trying to add 'libdl' to be linked with QEMU]
I did try to use 'g_module_open/close/symbol', but what I noticed is that
'g_module_close' did not really unload my library.
So if I would do:
1. g_module_open(my-lib)
2. Load symbols, use my library...
3. g_module_
On Tue, Mar 5, 2024 at 3:46 AM Jonah Palmer wrote:
>
> The goal of these patches are to add support to a variety of virtio and
> vhost devices for the VIRTIO_F_NOTIFICATION_DATA transport feature. This
> feature indicates that a driver will pass extra data (instead of just a
> virtqueue's index) w
Hi Laurent:
On Tue, Mar 5, 2024 at 6:07 PM Laurent Vivier wrote:
>
> On 2/1/24 06:45, Jason Wang wrote:
> > On Wed, Jan 24, 2024 at 6:40 PM Laurent Vivier wrote:
> >>
> >> On resume e1000e_vm_state_change() always calls e1000e_autoneg_resume()
> >> that sets link_down to false, and thus activate
On 2024/03/05 22:33, Peter Maydell wrote:
On Tue, 5 Mar 2024 at 07:37, Akihiko Odaki wrote:
elf2dmp assumes little endian host in many places.
Signed-off-by: Akihiko Odaki
---
contrib/elf2dmp/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/contrib/elf2dmp/m
On 2024/03/05 22:28, Peter Maydell wrote:
On Tue, 5 Mar 2024 at 07:36, Akihiko Odaki wrote:
include/qapi/error.h says:
We recommend
* bool-valued functions return true on success / false on failure,
...
Signed-off-by: Akihiko Odaki
---
contrib/elf2dmp/addrspace.h | 6 +--
contrib/elf2
On Fri, Feb 2, 2024 at 9:42 PM Vadim Shakirov
wrote:
>
> mcountinhibit, mcounteren, scounteren and hcounteren must always be 32-bit
> by privileged spec
>
> Signed-off-by: Vadim Shakirov
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu.h | 8
> target/ri
On Fri, Feb 2, 2024 at 9:42 PM Vadim Shakirov
wrote:
>
> mcountinhibit, mcounteren, scounteren and hcounteren must always be 32-bit
> by privileged spec
>
> Signed-off-by: Vadim Shakirov
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h | 8
> target/riscv/machi
Hello Zhao,
On Wed, 6 Mar 2024 at 08:49, Zhao Liu wrote:
>> then checking 'config->has_maxcpus ?' above is probably not required I
>> think. It could just be
>>
>>maxcpus = config->maxcpus
>
> Yes.
>
> > If a user does not specify config->maxcpus with -smp option, then it
> > could default to
On Sat, Mar 2, 2024 at 12:41 AM Daniel Henrique Barboza
wrote:
>
> smaia and ssaia were ratified in August 25th 2023 [1].
>
> zvfh and zvfhmin were ratified in August 2nd 2023 [2].
>
> zfbfmin and zvfbf(min|wma) are frozen and moved to public review since
> Dec 16th 2023 [3].
>
> zaamo and zalrsc
On Sat, Mar 2, 2024 at 12:41 AM Daniel Henrique Barboza
wrote:
>
> smaia and ssaia were ratified in August 25th 2023 [1].
>
> zvfh and zvfhmin were ratified in August 2nd 2023 [2].
>
> zfbfmin and zvfbf(min|wma) are frozen and moved to public review since
> Dec 16th 2023 [3].
>
> zaamo and zalrsc
On Thu, Feb 29, 2024 at 11:21 PM Nazerke Turtayeva wrote:
>
> Hi everyone,
>
> Recently, I was planning to measure the performance of my application of
> interest for potential RISC-V hardware. Hence, I started my simulations from
> Spike to analyze dynamic instruction traces and instruction cou
On Sun, Mar 3, 2024 at 8:34 PM Andreas Schwab wrote:
>
> On Jan 28 2024, Michael Tokarev wrote:
>
> > From: Richard Henderson
> >
> > A typo in sizeof_reg put the registers at the wrong offset.
> >
> > Simplify the expressions to use positive addresses from the
> > start of uc_mcontext instead of
On 3/5/24 17:56, Jinjie Ruan via wrote:
This patch set implements FEAT_NMI and FEAT_GICv3_NMI for armv8. These
introduce support for a new category of interrupts in the architecture
which we can use to provide NMI like functionality.
There are two modes for using this FEAT_NMI. When PSTATE.ALLIN
On 3/5/24 17:57, Jinjie Ruan via wrote:
If GICD_CTLR_DS bit is zero and the NMI is non-secure, the NMI prioirty
is higher than 0x80, otherwise it is higher than 0x0. And save NMI
super prioirty information in hppi.superprio to deliver NMI exception.
Since both GICR and GICD can deliver NMI, it is
On 3/5/24 17:52, lixianglai wrote:
The LDDIR_PS variable is not described in detail in the manual, but is only an
intermediate variable to assist in page size calculation during tcg simulation.
This is exactly why I believe adding this intermediate variable is wrong.
What happens if LDPTE is *
Add ALLINT MSR (immediate) to decodetree, in which the CRm is 0b000x. The
EL0 check is necessary to ALLINT, and the EL1 check is necessary when
imm == 1. So implement it inline for EL2/3, or EL1 with imm==0. Avoid the
unconditional write to pc and use raise_exception_ra to unwind.
Signed-off-by: J
Add IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI or
CPU_INTERRUPT_VNMI, both CPSR_I and ISR_IS must be set. With
CPU_INTERRUPT_VFIQ and HCRX_EL2.VFNMI set, both CPSR_F and ISR_FS must be set.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v7:
- env->cp15.hc
Support ALLINT msr access as follow:
mrs , ALLINT// read allint
msr ALLINT, // write allint with imm
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v5:
- Add Reviewed-by.
v4:
- Remove arm_is_el2_enabled() check in allint_check().
- Change to env->ps
According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt
with superpriority is always IRQ, never FIQ, so handle NMI same as IRQ in
arm_phys_excp_target_el().
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v4:
- Add Reviewed-by.
v3:
- Remove nmi_is_irq flag in CPUA
According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt
with superpriority is always IRQ, never FIQ, so the NMI exception trap entry
behave like IRQ. And VNMI(vIRQ with Superpriority) can be raised from the
GIC or come from the hcrx_el2.HCRX_VINMI bit.
Signed-off-by: Jinjie Ruan
Added properties to enable FEAT_GICv3_NMI feature, setup distributor
and redistributor registers to indicate NMI support.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v4:
- Add Reviewed-by.
---
hw/intc/arm_gicv3_common.c | 1 +
hw/intc/arm_gicv3_dist.c | 2 ++
In CPU Interface, if the IRQ has the superpriority property, report
NMI to the corresponding PE.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v6:
- Add Reviewed-by.
v4:
- Swap the ordering of the IFs.
v3:
- Remove handling nmi_is_irq flag.
---
hw/intc/arm_gicv3_cpuif.c | 4
Add the NMIAR CPU interface registers which deal with acknowledging NMI.
When introduce NMI interrupt, there are some updates to the semantics for the
register ICC_IAR1_EL1 and ICC_HPPIR1_EL1. For ICC_IAR1_EL1 register, it
should return 1022 if the intid has super priority. And for ICC_NMIAR1_EL1
This only implements the external delivery method via the GICv3.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v7:
- Add Reviewed-by.
v6:
- env->cp15.hcr_el2 -> arm_hcr_el2_eff().
- env->cp15.hcrx_el2 -> arm_hcrx_el2_eff().
- Not include VF && VFNMI in CPU_INTERRUPT_VNMI.
v4:
- A
Enable FEAT_NMI on the 'max' CPU.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v3:
- Add Reviewed-by.
- Sorted to last.
---
docs/system/arm/emulation.rst | 1 +
target/arm/tcg/cpu64.c| 1 +
2 files changed, 2 insertions(+)
diff --git a/docs/system/arm/emulation.rst b/d
A PE that implements FEAT_NMI and FEAT_GICv3 also implements
FEAT_GICv3_NMI. A PE that does not implement FEAT_NMI, does not implement
FEAT_GICv3_NMI
So included support FEAT_GICv3_NMI feature as part of virt platform
GIC initialization if FEAT_NMI and FEAT_GICv3 supported.
Signed-off-by: Jinjie
Add GICR_INMIR0 register and support access GICR_INMIR0.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v6:
- Add Reviewed-by.
v4:
- Make the GICR_INMIR0 implementation more clearer.
---
hw/intc/arm_gicv3_redist.c | 19 +++
hw/intc/gicv3_internal.h | 1 +
2 fil
Set or clear PSTATE.ALLINT on taking an exception to ELx according to the
SCTLR_ELx.SPINTMASK bit.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v3:
- Add Reviewed-by.
---
target/arm/helper.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/arm/helper.c b/targ
Wire the new NMI and VNMI interrupt line from the GIC to each CPU.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v4:
- Add Reviewed-by.
v3:
- Also add VNMI wire.
---
hw/arm/virt.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt.c b/hw/arm/vi
FEAT_NMI defines another three new bits in HCRX_EL2: TALLINT, HCRX_VINMI and
HCRX_VFNMI. When the feature is enabled, allow these bits to be written in
HCRX_EL2.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v4:
- Update the comment for FEAT_NMI in hcrx_write().
- Update the comm
When PSTATE.ALLINT is set, an IRQ or FIQ interrupt that is targeted to
ELx, with or without superpriority is masked.
As Richard suggested, place ALLINT bit in PSTATE in env->pstate.
With the change to pstate_read/write, exception entry
and return are automatically handled.
Signed-off-by: Jinjie
In vCPU Interface, if the vIRQ has the superpriority property, report
vNMI to the corresponding vPE.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v6:
- Add Reviewed-by.
---
hw/intc/arm_gicv3_cpuif.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --g
A SPI, PPI or SGI interrupt can have a superpriority property. So
maintain superpriority information in PendingIrq and GICR/GICD.
Signed-off-by: Jinjie Ruan
Acked-by: Richard Henderson
---
v3:
- Place this ahead of implement GICR_INMIR.
- Add Acked-by.
---
include/hw/intc/arm_gicv3_common.h | 4
Implement icv_nmiar1_read() for icc_nmiar1_read(), so add definition for
ICH_LR_EL2.NMI and ICH_AP1R_EL2.NMI bit.
If FEAT_GICv3_NMI is supported, ich_ap_write() should consider ICH_AP1R_EL2.NMI
bit. In icv_activate_irq() and icv_eoir_write(), the ICH_AP1R_EL2.NMI bit
should be set or clear accordi
If GICD_CTLR_DS bit is zero and the NMI is non-secure, the NMI prioirty
is higher than 0x80, otherwise it is higher than 0x0. And save NMI
super prioirty information in hppi.superprio to deliver NMI exception.
Since both GICR and GICD can deliver NMI, it is both necessary to check
whether the pendi
Add GICD_INMIR, GICD_INMIRnE register and support access GICD_INMIR0.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v4:
- Make the GICD_INMIR implementation more clearer.
- Udpate the commit message.
v3:
- Add Reviewed-by.
---
hw/intc/arm_gicv3_dist.c | 34 ++
Add support for FEAT_NMI. NMI (FEAT_NMI) is an mandatory feature in
ARMv8.8-A and ARM v9.3-A.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v3:
- Add Reviewed-by.
- Adjust to before the MSR patches.
---
target/arm/internals.h | 3 +++
1 file changed, 3 insertions(+)
diff --git
Augment the GICv3's QOM device interface by adding one
new set of sysbus IRQ line, to signal NMI to each CPU.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v4:
- Add Reviewed-by.
v3:
- Add support for VNMI.
---
hw/intc/arm_gicv3_common.c | 6 ++
include/hw/intc/arm_g
On Tue, Mar 5, 2024 at 6:27 PM Huang, Ying wrote:
>
> "Ho-Ren (Jack) Chuang" writes:
>
> > On Sun, Mar 3, 2024 at 6:42 PM Huang, Ying wrote:
> >>
> >> Hi, Jack,
> >>
> >> "Ho-Ren (Jack) Chuang" writes:
> >>
> >> > * Introduce `mt_init_with_hmat()`
> >> > We defer memory tier initialization for
Hi Richard :
On 3/4/24 20:21, lixianglai wrote:
Hi Richard:
On 3/4/24 17:51, Xianglai Li wrote:
When we use qemu tcg simulation, the page size of bios is 4KB.
When using the level 2 super large page (page size is 1G) to create
the page table,
it is found that the content of the corresponding
On Fri, Mar 1, 2024 at 2:20 AM Anup Patel wrote:
>
> On Thu, Feb 29, 2024 at 8:42 PM Andrew Jones wrote:
> >
> > On Thu, Feb 29, 2024 at 07:07:43PM +0530, Himanshu Chauhan wrote:
> > > All the CPUs may or may not implement the debug triggers (sdtrig)
> > > extension. The presence of it should be
>-Original Message-
>From: Eric Auger
>Subject: [PATCH v6 8/9] hw/arm/virt: Set virtio-iommu aw-bits default value
>to 48
>
>On ARM we set 48b as a default (matching SMMUv3 SMMU_IDR5.VAX == 0).
>
>hw_compat_8_2 is used to handle the compatibility for machine types
>before 9.0 (default w
Hi Prasad,
> On Tue, 5 Mar 2024 at 12:59, Zhao Liu wrote:
> > After simple test, if user sets maxcpus as 0, the has_maxcpus will be
> > true as well...I think it's related with QAPI code generation logic.
>
> * Right.
>
> [Maybe we digressed a bit in the discussion, so I snipped much of the
> d
Hi Eric,
>-Original Message-
>From: Eric Auger
>Subject: [PATCH v6 7/9] hw/i386/q35: Set virtio-iommu aw-bits default
>value to 39
>
>Currently the default input range can extend to 64 bits. On x86,
>when the virtio-iommu protects vfio devices, the physical iommu
>may support only 39 bits
On Mon, Mar 4, 2024 at 11:48 PM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> Let's update QEMU KVM extension support up to 6.8-rc6 before the 9.0
> freeze.
>
> Patches based on alistair/riscv-to-apply.next.
>
> Daniel Henrique Barboza (2):
> linux-headers: Update to Linux v6.8-rc6
> target/riscv
On Mon, Mar 4, 2024 at 11:48 PM Daniel Henrique Barboza
wrote:
>
> The last KVM extensions added were back in 6.6. Sync them to Linux 6.8.
>
> Signed-off-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/kvm/kvm-cpu.c | 29 +
> 1
Hi Conor,
On 3/6/2024 8:27 AM, Conor Dooley wrote:
> On Mon, Mar 04, 2024 at 06:25:39PM +0800, Fei Wu wrote:
>
>> +name = riscv_isa_string(cpu_ptr);
>> +qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name);
>> +g_free(name);
>
> Please use riscv_isa_write_fdt() h
On 2024/3/6 6:36, Richard Henderson wrote:
> On 3/4/24 21:03, Jinjie Ruan via wrote:
>> -static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio)
>> +static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio,
>> + bool has_superprio)
>> {
>> /* Return tru
> -Original Message-
> From: Fabiano Rosas
> Sent: Wednesday, March 6, 2024 4:58 AM
> To: Liu, Yuan1 ; pet...@redhat.com
> Cc: qemu-devel@nongnu.org; hao.xi...@bytedance.com;
> bryan.zh...@bytedance.com; Liu, Yuan1 ; Zou, Nanhai
>
> Subject: Re: [PATCH v4 4/8] migration/multifd: add qpl c
"Ho-Ren (Jack) Chuang" writes:
> On Sun, Mar 3, 2024 at 6:42 PM Huang, Ying wrote:
>>
>> Hi, Jack,
>>
>> "Ho-Ren (Jack) Chuang" writes:
>>
>> > * Introduce `mt_init_with_hmat()`
>> > We defer memory tier initialization for those CPUless NUMA nodes
>> > until acquiring HMAT info. `mt_init_with_h
On 3/5/2024 5:59 AM, Peter Maydell wrote:
> On Tue, 5 Mar 2024 at 13:40, RR NN wrote:
>>
>> Hello
>> ARM hypervisors (pKVM, Gunyah) can run x86 OSs?
>
> No. A hypervisor uses the host CPU's virtualization extensions
> to allow the guest code to run directly on the host CPU. This
> is why they're
> -Original Message-
> From: Fabiano Rosas
> Sent: Wednesday, March 6, 2024 4:32 AM
> To: Liu, Yuan1 ; pet...@redhat.com
> Cc: qemu-devel@nongnu.org; hao.xi...@bytedance.com;
> bryan.zh...@bytedance.com; Liu, Yuan1 ; Zou, Nanhai
>
> Subject: Re: [PATCH v4 3/8] configure: add --enable-qpl
On Mon, Mar 4, 2024 at 11:48 PM Daniel Henrique Barboza
wrote:
>
> The idea with this update is to get the latest KVM caps for RISC-V.
>
> Signed-off-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Alistair
> ---
> include/standard-headers/drm/drm_fourcc.h | 10 +-
> include/stan
On Wed, Feb 28, 2024 at 12:19 AM Li, Yong wrote:
>
> Hello,
>
> QEMU virt platform of RISCV-64 can emulate the mmc device by using below
> parameters:
> -device sdhci-pci,sd-spec-version=3 \
> -drive if=none,file=disk.img,format=raw,id=MMC1 \
> -device sd-card,drive=MMC1
>
> And as to u-boot, it
On Thu, Feb 22, 2024 at 7:33 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> In this version 2 new patches were added:
>
> - patch 5 eliminates the 'cpu_vl' global, and do_vsetvl() now loads 'vl'
> directly from env. This was suggested by Richard in the v5 review;
>
> - patch 9 does a change in ho
On Fri, Mar 1, 2024 at 4:07 AM Christoph Müllner
wrote:
>
> Running test-fcvtmod triggers the following deprecation warning:
> warning: CPU property 'Zfa' is deprecated. Please use 'zfa' instead
> Let's fix that.
>
> Signed-off-by: Christoph Müllner
Thanks!
Applied to riscv-to-apply.next
Ali
On Tue, Mar 05, 2024 at 03:43:41PM +0100, Markus Armbruster wrote:
> Peter Maydell writes:
>
> > On Mon, 4 Mar 2024 at 13:52, Maksim Davydov
> > wrote:
> >>
> >> The following changes since commit
> >> e1007b6bab5cf97705bf4f2aaec1f607787355b8:
> >>
> >> Merge tag 'pull-request-2024-03-01' of
On Fri, Mar 1, 2024 at 4:07 AM Christoph Müllner
wrote:
>
> Running test-fcvtmod triggers the following deprecation warning:
> warning: CPU property 'Zfa' is deprecated. Please use 'zfa' instead
> Let's fix that.
>
> Signed-off-by: Christoph Müllner
Reviewed-by: Alistair Francis
Alistair
>
On Thu, Feb 22, 2024 at 7:33 AM Daniel Henrique Barboza
wrote:
>
> Change the for loops in ldst helpers to do a single increment in the
> counter, and assign it env->vstart, to avoid re-reading from vstart
> every time.
>
> Suggested-by: Richard Henderson
> Signed-off-by: Daniel Henrique Barboza
On Thu, Feb 22, 2024 at 7:34 AM Daniel Henrique Barboza
wrote:
>
> From: Ivan Klokov
>
> The vstart_qe_zero flag is set at the beginning of the translation
> phase from the env->vstart variable. During the execution phase all
> functions will set env->vstart = 0 after a successful execution,
> bu
On Thu, Feb 22, 2024 at 7:33 AM Daniel Henrique Barboza
wrote:
>
> trans_vmv_v_i , trans_vfmv_v_f and the trans_##NAME macro from
> GEN_VMV_WHOLE_TRANS() are calling mark_vs_dirty() in both branches of
> their 'ifs'. conditionals.
>
> Call it just once in the end like other functions are doing.
>
On Thu, Feb 22, 2024 at 7:34 AM Daniel Henrique Barboza
wrote:
>
> The helper isn't setting env->vstart = 0 after its execution, as it is
> expected from every vector instruction that completes successfully.
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Richard Henderson
Reviewed-by
On Thu, Feb 22, 2024 at 7:34 AM Daniel Henrique Barboza
wrote:
>
> At this moment the global is used only in do_vsetvl(). Do a direct env
> load in do_vsetvl() to read 'vl' and remove the global.
>
> Suggested-by: Richard Henderson
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair
On Thu, Feb 22, 2024 at 7:33 AM Daniel Henrique Barboza
wrote:
>
> The global is unused after recent changes.
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/translate.c | 4 +---
> 1 file changed, 1 ins
On Thu, Feb 22, 2024 at 7:32 AM Daniel Henrique Barboza
wrote:
>
> Most of the vector translations has this following pattern at the start:
>
> TCGLabel *over = gen_new_label();
> tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>
> And then right at the end:
>
> gen_set_lab
On Thu, Feb 22, 2024 at 7:34 AM Daniel Henrique Barboza
wrote:
>
> After the 'mark_vs_dirty' changes from the previous patch the 'is_store'
> bool is unused in all load/store functions that were changed. Remove it.
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Richard Henderson
> Rev
On Thu, Feb 22, 2024 at 7:34 AM Daniel Henrique Barboza
wrote:
>
> While discussing a problem with how we're (not) setting vstart_eq_zero
> Richard had the following to say w.r.t the conditional mark_vs_dirty()
> calls on load/store functions [1]:
>
> "I think it's required to have stores set dirt
On 2024/3/5 下午11:45, Richard Henderson wrote:
On 3/4/24 20:26, Bibo Mao wrote:
+#ifdef CONFIG_TCG
static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr
*physical,
int *prot, target_ulong address,
int acc
> -Original Message-
> From: Fabiano Rosas
> Sent: Wednesday, March 6, 2024 4:24 AM
> To: Liu, Yuan1 ; pet...@redhat.com
> Cc: qemu-devel@nongnu.org; hao.xi...@bytedance.com;
> bryan.zh...@bytedance.com; Liu, Yuan1 ; Zou, Nanhai
>
> Subject: Re: [PATCH v4 2/8] migration/multifd: add get_i
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