On 13/2/24 16:50, Paolo Bonzini wrote:
Once the Kconfig for hw/mips is cleaned up, it will be possible to build a
binary that does not include any USB host controller and therefore that
does not include the code guarded by CONFIG_USB. While the simpler
creation functions such as usb_create_simpl
v1:
1. support uart controller both 0 and 1 base
2. fix hardcode boot address 0
v2:
1. introduce a new UART0 device name
2. remove ASPEED_SOC_SPI_BOOT_ADDR marco
v3:
1. add uart helper functions to get the index, start and last.
2. add more description in commit log
Jamin Lin (2):
aspeed: intr
In the previous design of ASPEED SOCs QEMU model, it set the boot
address at "0" which was the hardcode setting for ast10x0, ast2600,
ast2500 and ast2400.
According to the design of ast2700, it has a bootmcu(riscv-32) which
is used for executing SPL and initialize DRAM and copy u-boot image
from S
The Aspeed datasheet refers to the UART controllers
as UART1 - UART13 for the ast10x0, ast2600, ast2500
and ast2400 SoCs and the Aspeed ast2700 introduces an UART0
and the UART controllers as UART0 - UART12.
To keep the naming in the QEMU models
in sync with the datasheet, let's introduce a new U
In the previous design of ASPEED SOCs QEMU model, it set the boot
address at "0" which was the hardcode setting for ast10x0, ast2600,
ast2500 and ast2400.
According to the design of ast2700, it has a bootmcu(riscv-32) which
is used for executing SPL and initialize DRAM and copy u-boot image
from S
v1:
1. support uart controller both 0 and 1 base
2. fix hardcode boot address 0
v2:
1. introduce a new UART0 device name
2. remove ASPEED_SOC_SPI_BOOT_ADDR marco
v3:
1. add uart helper functions to get the index, start and last.
2. add more description in commit log
Jamin Lin (2):
aspeed: intr
In the previous design of ASPEED SOCs QEMU model, it set the boot
address at "0" which was the hardcode setting for ast10x0, ast2600,
ast2500 and ast2400.
According to the design of ast2700, it has a bootmcu(riscv-32) which
is used for executing SPL and initialize DRAM and copy u-boot image
from S
On 2/14/24 21:07, Philippe Mathieu-Daudé wrote:
On 15/2/24 07:20, Richard Henderson wrote:
The assertion was never correct, because the alignment is a composite
of the image alignment and SHMLBA. Even if the alignment didn't match
the image an assertion would not be correct -- more appropriate
Hi Luc,
On 2/13/24 09:22, Luc Michel wrote:
> An access fault is raised when the Access Flag is not set in the
> looked-up PTE and the AFFD field is not set in the corresponding context
> descriptor. This was already implemented for stage 2. Implement it for
> stage 1 as well.
>
> Signed-off-by: Lu
The Aspeed datasheet refers to the UART controllers
as UART1 - UART13 for the ast10x0, ast2600, ast2500
and ast2400 SoCs and the Aspeed ast2700 introduces an UART0
and the UART controllers as UART0 - UART12.
To keep the naming in the QEMU models
in sync with the datasheet, let's introduce a new U
v1:
1. support uart controller both 0 and 1 base
2. fix hardcode boot address 0
v2:
1. introduce a new UART0 device name
2. remove ASPEED_SOC_SPI_BOOT_ADDR marco
v3:
1. add uart helper functions to get the index, start and last.
2. add more description in commit log
Jamin Lin (2):
aspeed: intr
On 15/2/24 07:20, Richard Henderson wrote:
The assertion was never correct, because the alignment is a composite
of the image alignment and SHMLBA. Even if the alignment didn't match
the image an assertion would not be correct -- more appropriate would
be an error message about an ill formed ima
On 15/2/24 07:20, Richard Henderson wrote:
For the cases for which the host mmap succeeds, but does
not yield the desired address, use do_munmap to restore
the reserved_va memory reservation.
Signed-off-by: Richard Henderson
---
linux-user/mmap.c | 6 +++---
1 file changed, 3 insertions(+),
On 15/2/24 07:20, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
linux-user/mmap.c | 23 ---
1 file changed, 16 insertions(+), 7 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 14/2/24 05:54, Richard Henderson wrote:
The assertion was never correct, because the alignment is a composite
of the image alignment and SHMLBA. Even if the alignment didn't match
the image an assertion would not be correct -- more appropriate would
be an error message about an ill formed ima
On Wed, Feb 14, 2024 at 9:59 PM Si-Wei Liu wrote:
>
>
>
> On 2/14/2024 10:54 AM, Eugenio Perez Martin wrote:
> > On Wed, Feb 14, 2024 at 1:39 PM Si-Wei Liu wrote:
> >> Introduce new API. No functional change on existing API.
> >>
> >> Acked-by: Jason Wang
> >> Signed-off-by: Si-Wei Liu
> > I'm
Basic validation of operands does not require the lock.
Hoist them from target_mmap__locked back into target_mmap.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Reviewed-by: Ilya Leoshkevich
Acked-by: Helge Deller
Message-Id: <20240102015808.132373-18-richard.hender...@l
For the cases for which the host mmap succeeds, but does
not yield the desired address, use do_munmap to restore
the reserved_va memory reservation.
Signed-off-by: Richard Henderson
---
linux-user/mmap.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/linux-user/mmap.c
Use qemu_real_host_page_size() instead.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Ilya Leoshkevich
Acked-by: Helge Deller
Message-Id: <20240102015808.132373-16-richard.hender...@linaro.org>
---
linux-user/main.c | 10 ++
1 file changed, 6 insert
Replace with the maximum of the real host page size
and the target page size. This is an exact replacement.
Signed-off-by: Richard Henderson
Reviewed-by: Ilya Leoshkevich
Reviewed-by: Pierrick Bouvier
Acked-by: Helge Deller
Message-Id: <20240102015808.132373-12-richard.hender...@linaro.org>
-
For reserved_va, place all non-fixed maps then proceed
as for MAP_FIXED.
Signed-off-by: Richard Henderson
Reviewed-by: Pierrick Bouvier
Reviewed-by: Ilya Leoshkevich
Acked-by: Helge Deller
Message-Id: <20240102015808.132373-21-richard.hender...@linaro.org>
---
linux-user/mmap.c | 12 +++--
The size of the allocation need not match the alignment.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Ilya Leoshkevich
Acked-by: Helge Deller
Message-Id: <20240102015808.132373-13-richard.hender...@linaro.org>
---
hw/tpm/tpm_ppi.c | 3 +--
1 file changed,
We cannot skip over the_end1 to the_end, because we fail to
record the validity of the guest page with the interval tree.
Remove "the_end" and rename "the_end1" to "the_end".
Signed-off-by: Richard Henderson
Reviewed-by: Pierrick Bouvier
Reviewed-by: Ilya Leoshkevich
Acked-by: Helge Deller
Mes
Align allocation sizes to the maximum of host and target page sizes.
Signed-off-by: Richard Henderson
Reviewed-by: Ilya Leoshkevich
Reviewed-by: Pierrick Bouvier
Acked-by: Helge Deller
Message-Id: <20240102015808.132373-15-richard.hender...@linaro.org>
---
system/physmem.c | 15 +++---
Dynamically size the node for the runtime target page size.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Reviewed-by: Ilya Leoshkevich
Acked-by: Helge Deller
Message-Id: <20240102015808.132373-29-richard.hender...@linaro.org>
---
accel/tcg/user-exec.c | 13
Use qemu_real_host_page_size() instead.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Ilya Leoshkevich
Acked-by: Helge Deller
Message-Id: <20240102015808.132373-14-richard.hender...@linaro.org>
---
system/physmem.c | 2 +-
1 file changed, 1 insertion(+), 1
Move qemu_host_page_{size,mask} and HOST_PAGE_ALIGN into bsd-user.
It should be removed from bsd-user as well, but defer that cleanup.
Reviewed-by: Warner Losh
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Tested-by: Ilya Leoshkevich
Acked-by: Helge Deller
Message-Id: <
Since aarch64 binaries are generally built for multiple
page sizes, it is trivial to allow the page size to vary.
Signed-off-by: Richard Henderson
Reviewed-by: Pierrick Bouvier
Acked-by: Helge Deller
Message-Id: <20240102015808.132373-31-richard.hender...@linaro.org>
---
target/arm/cpu-param.h
When guest page size > host page size, this test can fail
due to the SIGBUS protection hack. Avoid this by making
sure that the file size is at least one guest page.
Visible with alpha guest on x86_64 host.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Reviewed-by: Ilya
Use TARGET_PAGE_SIZE and MAP_FIXED_NOREPLACE.
We really should be attending to this earlier during
probe_guest_base, as well as better detection and
emulation of various Linux personalities.
Signed-off-by: Richard Henderson
Reviewed-by: Ilya Leoshkevich
Reviewed-by: Pierrick Bouvier
Acked-by:
Use a subroutine instead of a goto within target_mmap__locked.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Reviewed-by: Ilya Leoshkevich
Acked-by: Helge Deller
Message-Id: <20240102015808.132373-20-richard.hender...@linaro.org>
---
linux-user/mmap.c | 71 +
Since alpha binaries are generally built for multiple
page sizes, it is trivial to allow the page size to vary.
Signed-off-by: Richard Henderson
Reviewed-by: Pierrick Bouvier
Reviewed-by: Ilya Leoshkevich
Acked-by: Helge Deller
Message-Id: <20240102015808.132373-34-richard.hender...@linaro.org
Use qemu_real_host_page_size instead.
Signed-off-by: Richard Henderson
Reviewed-by: Ilya Leoshkevich
Reviewed-by: Pierrick Bouvier
Acked-by: Helge Deller
Message-Id: <20240102015808.132373-9-richard.hender...@linaro.org>
---
linux-user/mmap.c | 66 +++--
This removes a hidden use of qemu_host_page_size, using instead
the existing host_page_size local within each function.
Signed-off-by: Richard Henderson
Reviewed-by: Pierrick Bouvier
Reviewed-by: Ilya Leoshkevich
Acked-by: Helge Deller
Message-Id: <20240102015808.132373-11-richard.hender...@li
These tests are confused, because -p does not change
the guest page size, but the host page size.
Signed-off-by: Richard Henderson
Reviewed-by: Pierrick Bouvier
Reviewed-by: Ilya Leoshkevich
Acked-by: Helge Deller
Message-Id: <20240102015808.132373-25-richard.hender...@linaro.org>
---
tests/t
Since ppc binaries are generally built for multiple
page sizes, it is trivial to allow the page size to vary.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Reviewed-by: Ilya Leoshkevich
Acked-by: Helge Deller
Message-Id: <20240102015808.132373-33-richard.hender...@linaro
AT_PAGESZ is supposed to advertise the guest page size.
The random adjustment made here using qemu_host_page_size
does not match anything else within linux-user.
The idea here is good, but should be done more systemically
via adjustment to TARGET_PAGE_SIZE.
Signed-off-by: Richard Henderson
Revie
All "goto fail" may be transformed to "return -1".
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Reviewed-by: Pierrick Bouvier
Reviewed-by: Ilya Leoshkevich
Acked-by: Helge Deller
Message-Id: <20240102015808.132373-17-richard.hender...@linaro.org>
---
linux-user/mmap.c
Move the MAX_FIXED_NOREPLACE check for reserved_va earlier.
Move the computation of host_prot earlier.
Signed-off-by: Richard Henderson
Reviewed-by: Pierrick Bouvier
Acked-by: Helge Deller
Message-Id: <20240102015808.132373-22-richard.hender...@linaro.org>
---
linux-user/mmap.c | 68 ++
This option controls the host page size. From the mis-usage in
our own testsuite, this is easily confused with guest page size.
The only thing that occurs when changing the host page size is
that stuff breaks, because one cannot actually change the host
page size. Therefore reject all but the no
The assertion was never correct, because the alignment is a composite
of the image alignment and SHMLBA. Even if the alignment didn't match
the image an assertion would not be correct -- more appropriate would
be an error message about an ill formed image. But the image cannot
be held to SHMLBA u
Use qemu_real_host_page_size.
If !reserved_va, use MAP_FIXED_NOREPLACE.
Signed-off-by: Richard Henderson
Reviewed-by: Pierrick Bouvier
Acked-by: Helge Deller
Message-Id: <20240102015808.132373-7-richard.hender...@linaro.org>
---
linux-user/elfload.c | 14 +-
1 file changed, 9 inser
If set, match the host and guest page sizes.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Acked-by: Helge Deller
Message-Id: <20240102015808.132373-30-richard.hender...@linaro.org>
---
linux-user/main.c | 16 +---
1 file changed, 13 insertions(+), 3 deletion
Use qemu_real_host_page_size.
If the commpage is not within reserved_va, use MAP_FIXED_NOREPLACE.
Signed-off-by: Richard Henderson
Reviewed-by: Pierrick Bouvier
Acked-by: Helge Deller
Message-Id: <20240102015808.132373-8-richard.hender...@linaro.org>
---
linux-user/elfload.c | 13 -
Use qemu_real_host_page_size instead. Except for the final mprotect
within page_protect, we already handled host < target page size.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Ilya Leoshkevich
Acked-by: Helge Deller
Message-Id: <20240102015808.132373-2-r
If reserved_va, then we have already reserved the entire
guest virtual address space; no need to remap page.
If !reserved_va, then use MAP_FIXED_NOREPLACE.
Signed-off-by: Richard Henderson
Reviewed-by: Pierrick Bouvier
Reviewed-by: Ilya Leoshkevich
Acked-by: Helge Deller
Message-Id: <202401020
Work much harder to get alignment and mapping beyond the end
of the file correct. Both of which are excercised by our
test-mmap for alpha (8k pages) on any 4k page host.
Signed-off-by: Richard Henderson
Reviewed-by: Pierrick Bouvier
Acked-by: Helge Deller
Message-Id: <20240102015808.132373-23-
We already have qemu_real_host_page_size() in a local variable.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Reviewed-by: Ilya Leoshkevich
Acked-by: Helge Deller
Message-Id: <20240102015808.132373-10-richard.hender...@linaro.org>
---
linux-user/mmap.c | 2 +-
1 file ch
Bizzarely, it is possible to set /proc/sys/vm/mmap_min_addr
to a value below the host page size. Fix that.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Ilya Leoshkevich
Acked-by: Helge Deller
Message-Id: <20240102015808.132373-32-richard.hender...@linaro.o
Signed-off-by: Richard Henderson
---
linux-user/mmap.c | 23 ---
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/linux-user/mmap.c b/linux-user/mmap.c
index 1bbfeb25b1..8ebcca 100644
--- a/linux-user/mmap.c
+++ b/linux-user/mmap.c
@@ -267,6 +267,21 @@ int ta
Changes for v4:
* Split out do_munmap.
* Incorporate review feedback.
Blurb from v1:
While working on mmap issues for 8.1, I noticed a lot of corner
cases of host != guest page size that we implement poorly.
This seems to be particularly visible on Apple M1 with 16k pages,
more so than Power
Signed-off-by: Richard Henderson
Reviewed-by: Pierrick Bouvier
Acked-by: Helge Deller
Message-Id: <20240102015808.132373-24-richard.hender...@linaro.org>
---
linux-user/mmap.c | 288 ++
1 file changed, 139 insertions(+), 149 deletions(-)
diff --git a
The host SHMLBA is by definition a multiple of the host page size.
Thus the remaining component of qemu_host_page_size is the
target page size.
Signed-off-by: Richard Henderson
Reviewed-by: Ilya Leoshkevich
Reviewed-by: Pierrick Bouvier
Acked-by: Helge Deller
Message-Id: <20240102015808.132373
On Sat, Feb 3, 2024 at 1:22 AM Daniel Henrique Barboza
wrote:
>
> From: Andrew Jones
>
> Gate hardware A/D PTE bit updating on {m,h}envcfg.ADUE and only
> enable menvcfg.ADUE on reset if svade has not been selected. Now
> that we also consider svade, we have four possible configurations:
>
> 1)
On Sat, Feb 3, 2024 at 1:24 AM Daniel Henrique Barboza
wrote:
>
> From: Andrew Jones
>
> Named features are extensions which don't make sense for users to
> control and are therefore not exposed on the command line. However,
> svade is an extension which makes sense for users to control, so treat
On Sat, Feb 3, 2024 at 1:23 AM Daniel Henrique Barboza
wrote:
>
> From: Andrew Jones
>
> The hypervisor should decide what it wants to enable. Zero all
> configuration enable bits on reset.
>
> Also, commit ed67d63798f2 ("target/riscv: Update CSR bits name for
> svadu extension") missed one refer
On Wed, Feb 14, 2024 at 5:18 AM Daniel Henrique Barboza
wrote:
>
> Add a RISC-V 'virt' machine to the graph. This implementation is a
> modified copy of the existing arm machine in arm-virt-machine.c
>
> It contains a virtio-mmio and a generic-pcihost controller. The
> generic-pcihost controller h
On Wed, Feb 14, 2024 at 5:18 AM Daniel Henrique Barboza
wrote:
>
> The 'virt' machine makes assumptions on the Advanced Core-Local
> Interruptor, or aclint, based on 'tcg_enabled()' conditionals. This
> will impact MSI related tests support when adding a RISC-V 'virt' libqos
> machine. The accele
On Wed, Feb 14, 2024 at 5:18 AM Daniel Henrique Barboza
wrote:
>
> We want to add a RISC-V 'virt' libqos machine to increase our test
> coverage. Some of the tests will try to plug a virtio-iommu-pci
> device into the board and do some tests with it.
>
> Enable virtio-iommu-pci in the 'virt' machi
On Wed, Feb 14, 2024 at 5:19 AM Daniel Henrique Barboza
wrote:
>
> Hotplugged FDT nodes will attempt to write this node that, at this
> moment, is being created only in create_fdt_pcie() during
> finalize_fdt().
>
> Create it earlier.
>
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alist
On Wed, Feb 14, 2024 at 5:18 AM Daniel Henrique Barboza
wrote:
>
> In qvring_init() we're writing vq->used->avail_event at "vq->used + 2 +
> array_size". The struct pointed by vq->used is, from virtio_ring.h
> Linux header):
>
> * // A ring of used descriptor heads with free-running index.
On Wed, Feb 14, 2024 at 5:18 AM Daniel Henrique Barboza
wrote:
>
> The loop isn't setting the values for the last element. Every other
> element is being initialized with addr = 0, flags = VRING_DESC_F_NEXT
> and next = i + 1. The last elem is never touched.
>
> This became a problem when enabling
On Wed, Feb 7, 2024 at 1:42 AM Alexandre Ghiti wrote:
>
> Currently, the initrd is placed at 128MB, which overlaps with the kernel
> when it is large (for example syzbot kernels are). From the kernel side,
> there is no reason we could not push the initrd further away in memory
> to accommodate la
On Wed, Jan 24, 2024 at 10:15 AM Atish Kumar Patra wrote:
>
> On Sun, Jan 21, 2024 at 9:04 PM Alistair Francis wrote:
> >
> > On Tue, Jan 9, 2024 at 10:29 AM Atish Patra wrote:
> > >
> > > Privilege mode filtering can also be emulated for cycle/instret by
> > > tracking host_ticks/icount during
On Tue, Jan 9, 2024 at 10:29 AM Atish Patra wrote:
>
> Privilege mode filtering can also be emulated for cycle/instret by
> tracking host_ticks/icount during each privilege mode switch. This
> patch implements that for both cycle/instret and mhpmcounters. The
> first one requires Smcntrpmf while t
On Mon, Feb 5, 2024 at 6:37 PM Christoph Müllner
wrote:
>
> On Mon, Feb 5, 2024 at 3:42 AM Alistair Francis wrote:
> >
> > On Sun, Feb 4, 2024 at 3:44 PM LIU Zhiwei
> > wrote:
> > >
> > > This patch set fix the regression on kernel pointed by Björn Töpel in
> > > https://www.mail-archive.com/qe
On Sat, Feb 3, 2024 at 1:24 AM Daniel Henrique Barboza
wrote:
>
> The RVA22U64 and RVA22S64 profiles mandates certain extensions that,
> until now, we were implying that they were available.
>
> We can't do this anymore since named features also has a riscv,isa
> entry. Let's add them to riscv_cpu
On Fri, Jan 26, 2024 at 11:33 PM Andrew Jones wrote:
>
> From: Daniel Henrique Barboza
>
> The RVA22U64 and RVA22S64 profiles mandates certain extensions that,
> until now, we were implying that they were available.
>
> We can't do this anymore since named features also has a riscv,isa
> entry.
Alistair
On Fri, Jan 26, 2024 at 11:32 PM Andrew Jones wrote:
>
> From: Daniel Henrique Barboza
>
> Further discussions after the introduction of rva22 support in QEMU
> revealed that what we've been calling 'named features' are actually
> regular extensions, with their respective riscv,isa DTs.
This patch extends the PCIe link speed option so that slots can be
configured as supporting 32GT/s (Gen5) or 64GT/s (Gen5) speeds.
This is as simple as setting the appropriate bit in LnkCap2 and
the appropriate value in LnkCap and LnkCtl2.
Signed-off-by: Lukas Stockner
---
hw/core/qdev-propertie
On Fri, Feb 09, 2024 at 07:54:15PM +0800, Shiyang Ruan wrote:
> If poison is detected(reported from cxl memdev), OS should be notified to
> handle it. Introduce this function:
> 1. translate DPA to HPA;
> 2. construct a MCE instance; (TODO: more details need to be filled)
> 3. log it into MC
On Sat, Jan 27, 2024 at 12:18 AM Andrew Jones wrote:
>
> From: Daniel Henrique Barboza
>
> Recent changes in options handling removed the 'mmu' default the bare
> CPUs had, meaning that we must enable 'mmu' by hand when using the
> rva22s64 profile CPU.
>
> Given that this profile is setting a sa
On Wed, Jan 10, 2024 at 2:07 AM Irina Ryapolova
wrote:
>
> Added xATP_MODE validation for vsatp/hgatp CSRs.
> The xATP register is an SXLEN-bit read/write WARL register, so
> the legal value must be returned (See riscv-privileged-20211203,
> SATP/VSATP/HGATP CSRs).
>
> Signed-off-by: Irina Ryapol
On Wed, Jan 10, 2024 at 1:00 AM Irina Ryapolova
wrote:
>
> The SATP register is an SXLEN-bit read/write WARL register. It means that CSR
> fields are only defined
> for a subset of bit encodings, but allow any value to be written while
> guaranteeing to return a legal
> value whenever read (See
On Fri, Nov 17, 2023 at 5:35 PM 方 <1584389...@qq.com> wrote:
>
> Hello everyone! I am working on implementing a tool to assess the complexity
> of CPU architecture porting. It primarily focuses on RISC-V architecture
> porting. In fact, the tool may have an average estimate of various
> archite
On Tue, Jan 16, 2024 at 11:11 AM Sia Jee Heng
wrote:
>
> Generate Serial Port Console Redirection Table (SPCR) for RISC-V
> virtual machine.
>
> Signed-off-by: Sia Jee Heng
> Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/riscv/virt-acpi-build.c | 39
On Tue, Jan 16, 2024 at 11:11 AM Sia Jee Heng
wrote:
>
> RISC-V should also generate the SPCR in a manner similar to ARM.
> Therefore, instead of replicating the code, relocate this function
> to the common AML build.
>
> Signed-off-by: Sia Jee Heng
Reviewed-by: Alistair Francis
Alistair
> --
> -Original Message-
> From: Cédric Le Goater
> Sent: Friday, February 9, 2024 4:32 PM
> To: Jamin Lin ; Peter Maydell
> ; Andrew Jeffery ;
> Joel Stanley ; open list:ASPEED BMCs
> ; open list:All patches CC here
>
> Cc: Troy Lee
> Subject: Re: [PATCH v2 2/2] aspeed: fix hardcode boot ad
> -Original Message-
> From: Cédric Le Goater
> Sent: Friday, February 9, 2024 4:27 PM
> To: Jamin Lin ; Cédric Le Goater ;
> Peter Maydell ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc: Troy Lee
> Subject: Re: [PATCH v2 1/2] aspeed: i
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Thursday, February 8, 2024 4:29 AM
> To: Jamin Lin ; Cédric Le Goater ;
> Peter Maydell ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc: Troy Lee
> Subject: Re: [PATCH v2 2/2] a
On Wed, Feb 14, 2024, at 13:26, Dmitry Baryshkov wrote:
> On Tue, 13 Feb 2024 at 23:22, Linus Walleij wrote:
>> On Tue, Feb 13, 2024 at 9:12 PM Arnd Bergmann wrote:
>> > On Tue, Feb 13, 2024, at 16:36, Guenter Roeck wrote:
>> > > On Tue, Feb 13, 2024 at 03:14:21PM +, Peter Maydell wrote:
>>
>
On Wed, Feb 14, 2024 at 2:39 PM Marcin Juszkiewicz
wrote:
>
> Most of OpenZaurus/Ångström developers abandoned Zaurus devices in 2008.
> Usually in favour of Nokia 770/n800/n810 tablets.
>
> Both OpenZaurus and Ångström used own hosting in handhelds.org era.
I joined OpenEmbedded in that years an
Hello,
This patchset includes patches for adding Identify data for the
recently added Endurance Group (endgrpid=1) used in FDP, and patches
for increasing the maximum number of SR-IOV VF Resources to support
more resources to enable testing as recent SSDs.
Thanks,
Minwoo Im (3):
hw/nvme: add I
From: Minwoo Im
Commit 73064edfb864 ("hw/nvme: flexible data placement emulation")
intorudced NVMe FDP feature to nvme-subsys and nvme-ctrl with a
single endurance group #1 supported. This means that controller should
return proper identify data to host with Identify Endurance Group List
(CNS 19
From: Minwoo Im
The number of virtual functions(VFs) supported in SR-IOV is 64k as per
spec. To test a large number of MSI-X vectors mapping to CPU matrix in
the QEMU system, we need much more than 127 VFs. This patch made
support for 256 VFs per a physical function(PF).
Signed-off-by: Minwoo
From: Minwoo Im
VI and VQ resources cover queue resources in each VFs in SR-IOV.
Current maximum I/O queue pair size is 0x, we can expand them to
cover the full number of I/O queue pairs.
This patch also fixed Identify Secondary Controller List overflow due to
expand of number of secondary c
Begin forwarded message:
From: Xu Liu
Subject: How do I make my emulated device's DMA go through viommu ?
Date: February 14, 2024 at 11:46:04 AM EST
To: "qemu-disc...@nongnu.org"
Cc: 刘旭 , Xu Liu
Hello, All
I am working a project, which has a custom emulated PCI device for the QEMU.
In sid
On 2/14/2024 10:54 AM, Eugenio Perez Martin wrote:
On Wed, Feb 14, 2024 at 1:39 PM Si-Wei Liu wrote:
Introduce new API. No functional change on existing API.
Acked-by: Jason Wang
Signed-off-by: Si-Wei Liu
I'm ok with the new function, but doesn't the compiler complain
because adding a st
Cédric Le Goater writes:
> Hello Fabiano
>
> On 2/8/24 14:29, Fabiano Rosas wrote:
>> Cédric Le Goater writes:
>>
>>> In case of error, close_return_path_on_source() can perform a shutdown
>>> to exit the return-path thread. However, in migrate_fd_cleanup(),
>>> 'to_dst_file' is closed before
On Wed, Feb 14, 2024 at 7:29 PM Si-Wei Liu wrote:
>
> Hi Michael,
>
> On 2/13/2024 2:22 AM, Michael S. Tsirkin wrote:
> > On Mon, Feb 05, 2024 at 05:10:36PM -0800, Si-Wei Liu wrote:
> >> Hi Eugenio,
> >>
> >> I thought this new code looks good to me and the original issue I saw with
> >> x-svq=on
On 2/13/24 23:40, Chinmay Rath wrote:
This patch moves the below instructions to decodetree specification:
{add, subf}[c,e,me,ze][o][.] : XO-form
addic[.], subfic : D-form
addex : Z23-form
This patch introduces XO f
On Wed, Feb 14, 2024 at 1:39 PM Si-Wei Liu wrote:
>
> Introduce new API. No functional change on existing API.
>
> Acked-by: Jason Wang
> Signed-off-by: Si-Wei Liu
I'm ok with the new function, but doesn't the compiler complain
because adding a static function is not used?
> ---
> net/vhost-v
Paolo Bonzini writes:
> The build-previous-qemu job is now trying to fetch from the upstream
> repository, but the tag is only fetched into FETCH_HEAD:
>
> $ git remote add upstream https://gitlab.com/qemu-project/qemu 00:00
> $ git fetch upstream $QEMU_PREV_VERSION 00:02
> warning: redirecting t
Hi Michael,
I'm taking off for 2+ weeks, but please feel free to provide comment and
feedback while I'm off. I'll be checking emails still, and am about to
address any opens as soon as I am back.
Thanks,
-Siwei
On 2/14/2024 3:50 AM, Si-Wei Liu wrote:
There could be a mix of both vhost-user
Hi Eugenio,
Just to answer the question you had in the sync meeting as I've just
tried, it seems that the issue is also reproducible even with VGA device
and VNC display removed, and also reproducible with 8G mem size. You
already knew that I can only repro with x-svq=on.
Regards,
-Siwei
On
Hi Michael,
On 2/13/2024 2:22 AM, Michael S. Tsirkin wrote:
On Mon, Feb 05, 2024 at 05:10:36PM -0800, Si-Wei Liu wrote:
Hi Eugenio,
I thought this new code looks good to me and the original issue I saw with
x-svq=on should be gone. However, after rebase my tree on top of this,
there's a new fa
On Wed, 14 Feb 2024 at 11:19, Michael S. Tsirkin wrote:
>
> On Wed, Feb 14, 2024 at 06:13:16AM -0500, Michael S. Tsirkin wrote:
> > The following changes since commit df50424b4dcfde823047d3717abd6a61224ea205:
> >
> > Merge tag 'pull-riscv-to-apply-20240209' of
> > https://github.com/alistair23/
Hao Xiang writes:
> On Fri, Feb 9, 2024 at 4:20 AM Fabiano Rosas wrote:
>>
>> Hao Xiang writes:
>>
>> > On Fri, Feb 2, 2024 at 2:30 AM wrote:
>> >>
>> >> From: Peter Xu
>> >>
>> >> This array is redundant when p->pages exists. Now we extended the life of
>> >> p->pages to the whole period wh
On 2024/02/15 1:34, Michael S. Tsirkin wrote:
On Thu, Feb 15, 2024 at 01:07:29AM +0900, Akihiko Odaki wrote:
On 2024/02/15 0:46, Michael S. Tsirkin wrote:
On Wed, Feb 14, 2024 at 11:09:50PM +0900, Akihiko Odaki wrote:
On 2024/02/14 16:07, Michael S. Tsirkin wrote:
On Wed, Feb 14, 2024 at 02:1
On Thu, Feb 15, 2024 at 01:07:29AM +0900, Akihiko Odaki wrote:
> On 2024/02/15 0:46, Michael S. Tsirkin wrote:
> > On Wed, Feb 14, 2024 at 11:09:50PM +0900, Akihiko Odaki wrote:
> > > On 2024/02/14 16:07, Michael S. Tsirkin wrote:
> > > > On Wed, Feb 14, 2024 at 02:13:47PM +0900, Akihiko Odaki wrot
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