On 1/12/24 13:52, Mark Cave-Ayland wrote:
The FIFO contents should not be affected if the target selection fails.
Signed-off-by: Mark Cave-Ayland
I built and tested this series together with your "esp-pci: fixes for
Linux and MS-DOS" on top of git head and they fixed all outstanding issues.
On Thu, Jan 11, 2024 at 9:59 AM Jonathan Cameron
wrote:
>
> From: Hyeonggon Yoo <42.hye...@gmail.com>
>
> In the current mdev_reg_read() implementation, it consistently returns
> that the Media Status is Ready (01b). This was fine until commit
> 25a52959f99d ("hw/cxl: Add support for device sanita
Allwinner R40 supports an AHCI compliant SATA controller.
Add support for it.
Signed-off-by: Guenter Roeck
---
docs/system/arm/bananapi_m2u.rst | 1 +
hw/arm/Kconfig | 1 +
hw/arm/allwinner-r40.c | 12 +++-
include/hw/arm/allwinner-r40.h | 3 +++
4 files
Add watchdog timer support to Allwinner-H40 and Bananapi.
The watchdog timer is added as an overlay to the Timer
module memory map.
Signed-off-by: Guenter Roeck
---
docs/system/arm/bananapi_m2u.rst | 2 +-
hw/arm/Kconfig | 1 +
hw/arm/allwinner-r40.c | 8
inc
Allwinner R40 supports two USB host ports shared between a USB 2.0 EHCI
host controller and a USB 1.1 OHCI host controller. Add support for both
of them.
If machine USB support is not enabled, create unimplemented devices
for the USB memory ranges to avoid crashes when booting Linux.
Signed-off-b
Add support for
- USB 2.0 EHCI/OHCI
- SATA/AHCI
- Watchdog
to Allwinner R40. The hardware is quite similar to Allwinner A10 and H3,
so the code is derived from the implementations for those SOCs.
Tested with bpim2u emulation by instantiating EHCI and OHCI keyboards,
by booting from USB, by booti
Pierrick Bouvier writes:
> On 1/12/24 21:20, Alex Bennée wrote:
>> Pierrick Bouvier writes:
>>
>>> On 1/11/24 19:57, Philippe Mathieu-Daudé wrote:
Hi Pierrick,
On 11/1/24 15:23, Pierrick Bouvier wrote:
> For now, it simply performs instruction, bb and mem count, and ensure
> t
> -Original Message-
> From: Hao Xiang
> Sent: Thursday, January 11, 2024 1:42 PM
> To: Liu, Yuan1
> Cc: Fabiano Rosas ; Bryan Zhang
> ; qemu-devel@nongnu.org;
> marcandre.lur...@redhat.com; pet...@redhat.com; quint...@redhat.com;
> peter.mayd...@linaro.org; berra...@redhat.com; Zou, Na
> -Original Message-
> From: Hao Xiang
> Sent: Thursday, January 11, 2024 2:40 PM
> To: Fabiano Rosas
> Cc: Liu, Yuan1 ; Bryan Zhang
> ; qemu-devel@nongnu.org;
> marcandre.lur...@redhat.com; pet...@redhat.com; quint...@redhat.com;
> peter.mayd...@linaro.org; berra...@redhat.com
> Subject:
On Wed, 10 Jan 2024 at 19:53, Philippe Mathieu-Daudé wrote:
>
> Since v2 [2]:
> - Dropped "Simplify checking A64_MTE bit in FEATURE_ID register"
> - Correct object_property_get_bool() uses
> - Update ARM_FEATURE_AARCH64 && aa64_mte
>
> Since RFC [1]:
> - Split one patch per feature
> - Addressed P
On Wed, 10 Jan 2024 at 19:54, Philippe Mathieu-Daudé wrote:
>
> All CPUs implementing ARM_FEATURE_M have the 'init-nsvtor' property.
> Since setting the property can not fail, replace
>
>object_property_set_uint(..., "init-nsvtor", ..., &error_abort);
>
> by:
>qdev_prop_set_uint32(..., "in
On Wed, 10 Jan 2024 at 19:53, Philippe Mathieu-Daudé wrote:
>
> ARMV7M container can only accept M-profile CPU types.
> Check requested type is valid once to allow further simplifications.
>
> Suggested-by: Peter Maydell
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/arm/armv7m.c | 4
>
On Wed, 10 Jan 2024 at 19:53, Philippe Mathieu-Daudé wrote:
>
> Reorganize a bit by first setting properties which are not
> dependent of CPU features (and can not fail).
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Wed, 10 Jan 2024 at 19:53, Philippe Mathieu-Daudé wrote:
>
> We are going to cast s->cpu as DeviceState multiple times.
> Add a local 'cpudev' variable to simplify code review, having
> a single DEVICE(s->cpu) conversion.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/arm/armv7m.c | 7 +
On Wed, 10 Jan 2024 at 23:42, Nabih Estefan wrote:
>
> From: Hao Wu
>
> This patches adds a qtest for NPCM7XX PCI Mailbox module.
> It sends read and write requests to the module, and verifies that
> the module contains the correct data after the requests.
>
> Change-Id: I2e1dbaecf8be9ec7eab55cb5
On Wed, 10 Jan 2024 at 23:42, Nabih Estefan wrote:
>
> From: Nabih Estefan Diaz
>
> [Changes since v11]
> Was running into error syncing into master. It seemed to be related to a
> hash problem introduced in patchset 10 (unrelated to the macOS build
> issue). carried the patches from v9 (before t
On Wed, 10 Jan 2024 at 23:42, Nabih Estefan wrote:
>
> From: Hao Wu
>
> The PCI Mailbox Module is a high-bandwidth communcation module
> between a Nuvoton BMC and CPU. It features 16KB RAM that are both
> accessible by the BMC and core CPU. and supports interrupt for
> both sides.
>
> This patch
On Wed, 10 Jan 2024 at 23:42, Nabih Estefan wrote:
>
> From: Hao Wu
>
> This patch implements the basic registers of GMAC device and sets
> registers for networking functionalities.
>
> Tested:
> The following message shows up with the change:
> Broadcom BCM54612E stmmac-0:00: attached PHY driver
On Wed, 10 Jan 2024 at 23:42, Nabih Estefan wrote:
>
> From: Nabih Estefan Diaz
>
> - Implementation of Receive function for packets
> - Implementation for reading and writing from and to descriptors in
> memory for Rx
>
> When RX starts, we need to flush the queued packets so that they
> can b
Arnaud Minier writes:
+ * The procedure is taken from a program by Samuel Tardieu.
You may drop this line as I used the same procedure which is used
in other tests, this does not deserve a mention here.
Sam
--
Samuel Tardieu
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
hw/misc/stm32l4x5_rcc.c | 154 ++
hw/misc/trace-events | 5 +
include/hw/misc/stm32l4x5_rcc.h | 119 +
include/hw/misc/stm32l4x5_rcc_internals.h | 2
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
hw/arm/b-l475e-iot01a.c| 10 +-
hw/arm/stm32l4x5_soc.c | 33 -
include/hw/arm/stm32l4x5_soc.h | 3 ---
3 files changed, 5 insertions(+), 41 deletions(-)
diff --git a/hw/arm/b-l47
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
hw/misc/stm32l4x5_rcc.c | 506 +++-
1 file changed, 494 insertions(+), 12 deletions(-)
diff --git a/hw/misc/stm32l4x5_rcc.c b/hw/misc/stm32l4x5_rcc.c
index 33c2a1915f..29545198a0 100644
--- a/hw/misc
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
MAINTAINERS | 5 +-
docs/system/arm/b-l475e-iot01a.rst| 2 +-
hw/arm/Kconfig| 1 +
hw/arm/stm32l4x5_soc.c| 12 +-
hw/misc/Kconfig
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
hw/misc/stm32l4x5_rcc.c | 168 ++
hw/misc/trace-events | 5 +
include/hw/misc/stm32l4x5_rcc.h | 40 ++
include/hw/misc/stm32l4x5_rcc_internals.h | 22 +++
4 fi
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
tests/qtest/meson.build | 3 +-
tests/qtest/stm32l4x5_rcc-test.c | 211 +++
2 files changed, 213 insertions(+), 1 deletion(-)
create mode 100644 tests/qtest/stm32l4x5_rcc-test.c
diff --git a/test
This patch adds a new device STM32L4x5 RCC (Reset and Clock Control) device and
is part
of a series implementing the STM32L4x5 with a few peripherals.
Due to the high number of lines, I tried to split the patch into several
independent commits.
Each commit compiles on its own but I had to add te
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
hw/misc/stm32l4x5_rcc.c | 69 ++-
include/hw/misc/stm32l4x5_rcc_internals.h | 707 ++
2 files changed, 774 insertions(+), 2 deletions(-)
diff --git a/hw/misc/stm32l4x5_rcc.c b/hw/misc/stm32l4x5_rc
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