Without this, we just dirty a single byte, and so if the caller writes
more than one byte to the host memory then we won't have invalidated any
translation blocks that start after the first byte and overlap those
writes. In particular, AArch64's DC ZVA implementation uses probe_access
(via probe_wr
On 11/3/23 12:07, Peter Maydell wrote:
On Thu, 26 Oct 2023 at 01:25, Richard Henderson
wrote:
Tested-by: Mark Cave-Ayland
Acked-by: Mark Cave-Ayland
Signed-off-by: Richard Henderson
+static TCGv do_rdgsr(DisasContext *dc, TCGv dst)
+{
+gen_trap_ifnofpu(dc);
+return cpu_gsr;
+}
+
On 11/2/2023 3:12 AM, Si-Wei Liu wrote:
On 10/19/2023 7:34 AM, Eugenio Pérez wrote:
Current memory operations like pinning may take a lot of time at the
destination. Currently they are done after the source of the
migration is
stopped, and before the workload is resumed at the destinat
On 11/3/2023 3:51 PM, Steven Sistare wrote:
> On 11/3/2023 1:33 PM, Daniel P. Berrangé wrote:
>> On Fri, Nov 03, 2023 at 09:01:29AM -0700, Steve Sistare wrote:
>>> Buffered monitor output is lost when abort() is called. The pattern
>>> error_report() followed by abort() occurs about 60 times, so v
On 11/2/2023 5:37 AM, Eugenio Perez Martin wrote:
On Thu, Nov 2, 2023 at 11:13 AM Si-Wei Liu wrote:
On 10/19/2023 7:34 AM, Eugenio Pérez wrote:
Current memory operations like pinning may take a lot of time at the
destination. Currently they are done after the source of the migration is
Expose an internal API to QEMU to find groups of registers. It returns
a list containing the details required to called gdb_read_register().
Based-on: <20231025093128.33116-15-akihiko.od...@daynix.com>
Cc: Akihiko Odaki
Signed-off-by: Alex Bennée
---
vAJB:
This principle difference is the find
From: Akihiko Odaki
These members will be used to help plugins to identify registers.
The added members in instances of GDBFeature dynamically generated by
CPUs will be filled in later changes.
Signed-off-by: Akihiko Odaki
Message-Id: <20231025093128.33116-14-akihiko.od...@daynix.com>
Signed-of
From: Greg Manning
Generate a qemu_plugin_api.lib delay import lib on windows, for
windows qemu plugins to link against.
Implement an example dll load fail hook to link up the API functions
correctly when a plugin is loaded on windows.
Update the build scripts for the test and example plugins t
This avoids two duplicates being presented to gdbstub. As the
registers are RAZ anyway it is unlikely their value would be of use to
someone using gdbstub anyway.
Signed-off-by: Alex Bennée
---
target/arm/debug_helper.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/
We can only request a list of registers once the vCPU has been
initialised so the user needs to use either call the find function on
vCPU initialisation or during the translation phase. We don't expose
the reg number to the plugin instead hiding it behind an opaque
handle. This allows for a bit of
From: Greg Manning
allow plugins to be enabled in the configure script on windows. Also,
add the qemu_plugin_api.lib to the installer.
Signed-off-by: Greg Manning
Reviewed-by: Alex Bennée
Message-Id: <20231102172053.17692-5-gmann...@rapitasystems.com>
Signed-off-by: Alex Bennée
---
configure
From: Akihiko Odaki
In preparation for a change to use GDBFeature as a parameter of
gdb_register_coprocessor(), convert the internal representation of
dynamic feature from plain XML to GDBFeature.
Signed-off-by: Akihiko Odaki
Acked-by: Richard Henderson
Message-Id: <20231025093128.33116-5-akih
From: Akihiko Odaki
This function is no longer used.
Signed-off-by: Akihiko Odaki
Reviewed-by: Alex Bennée
Message-Id: <20231025093128.33116-13-akihiko.od...@daynix.com>
Signed-off-by: Alex Bennée
---
include/hw/core/cpu.h | 4
target/arm/cpu.h | 6 --
target/ppc/cpu.h |
From: Akihiko Odaki
This avoids optimizations incompatible when reading registers.
Signed-off-by: Akihiko Odaki
Message-Id: <20231025093128.33116-17-akihiko.od...@daynix.com>
Signed-off-by: Alex Bennée
---
accel/tcg/plugin-helpers.h | 3 ++-
include/qemu/plugin.h | 1 +
accel/tcg/plugi
From: Akihiko Odaki
Now we know all instances of GDBFeature that is used in CPU so we can
traverse them to find XML. This removes the need for a CPU-specific
lookup function for dynamic XMLs.
Signed-off-by: Akihiko Odaki
Reviewed-by: Alex Bennée
Message-Id: <20231025093128.33116-11-akihiko.od.
From: Greg Manning
The lockstep plugin uses unix sockets and would require a different
communication mechanism to work on Windows.
Signed-off-by: Greg Manning
Reviewed-by: Alex Bennée
Message-Id: <20231102172053.17692-4-gmann...@rapitasystems.com>
Signed-off-by: Alex Bennée
---
contrib/plugi
From: Akihiko Odaki
GDBFeature has the num_regs member so use it where applicable to
remove magic numbers.
Signed-off-by: Akihiko Odaki
Message-Id: <20231025093128.33116-12-akihiko.od...@daynix.com>
Signed-off-by: Alex Bennée
---
include/hw/core/cpu.h | 3 ++-
target/s390x/cpu.h | 2 --
From: Akihiko Odaki
Simplify GDBRegisterState by replacing num_regs and xml members with
one member that points to GDBFeature.
Signed-off-by: Akihiko Odaki
Reviewed-by: Alex Bennée
Message-Id: <20231025093128.33116-9-akihiko.od...@daynix.com>
Signed-off-by: Alex Bennée
---
gdbstub/gdbstub.c
From: Akihiko Odaki
This is a tree-wide change to introduce GDBFeature parameter to
gdb_register_coprocessor(). The new parameter just replaces num_regs
and xml parameters for now. GDBFeature will be utilized to simplify XML
lookup in a following change.
Signed-off-by: Akihiko Odaki
Acked-by: A
From: Akihiko Odaki
In preparation for a change to use GDBFeature as a parameter of
gdb_register_coprocessor(), convert the internal representation of
dynamic feature from plain XML to GDBFeature.
Signed-off-by: Akihiko Odaki
Message-Id: <20231025093128.33116-7-akihiko.od...@daynix.com>
Signed-
From: Greg Manning
In qemu-plugin.h, mark all API functions as __declspec(dllexport) when
compiling the executables, and as __declspec(dllimport) when being used
to compile plugins against.
Signed-off-by: Greg Manning
Reviewed-by: Alex Bennée
Message-Id: <20231102172053.17692-2-gmann...@rapita
With the new plugin register API we can now track changes to register
values. Currently the implementation is fairly dumb which will slow
down if a large number of register values are being tracked. This
could be improved by only instrumenting instructions which mention
registers we are interested
There are a number of things that are broken on the test currently so
lets fix that up:
- replace retired Debian kernel for tuxrun_baseline one
- remove "detected repeat instructions test" since ea185a55
- log total counted instructions/memory accesses
Signed-off-by: Alex Bennée
---
tests
From: Akihiko Odaki
The initialization and exit hooks will not affect the state of vCPU
outside TCG context, but they may depend on the state of vCPU.
Therefore, it's better to call plugin hooks after the vCPU state is
fully initialized and before it gets uninitialized.
Signed-off-by: Akihiko Od
From: Akihiko Odaki
In preparation for a change to use GDBFeature as a parameter of
gdb_register_coprocessor(), convert the internal representation of
dynamic feature from plain XML to GDBFeature.
Signed-off-by: Akihiko Odaki
Reviewed-by: Richard Henderson
Message-Id: <20231025093128.33116-6-a
From: Akihiko Odaki
Align the parameters of gdb_get_reg_cb and gdb_set_reg_cb with the
gdb_read_register and gdb_write_register members of CPUClass to allow
to unify the logic to access registers of the core and coprocessors
in the future.
Signed-off-by: Akihiko Odaki
Reviewed-by: Alex Bennée
This is a slightly hacky way to avoid duplicate PAR's in the system
register XML we send to gdb which causes an alias. However the other
alternative would be to post process ARMCPRegInfo once all registers
have been defined looking for textual duplicates. And that seems like
overkill.
Signed-off-b
From: Akihiko Odaki
loongarch64-linux-user has references to XML files so include them.
Fixes: d32688ecdb ("default-configs: Add loongarch linux-user support")
Signed-off-by: Akihiko Odaki
Message-Id: <20231030054834.39145-6-akihiko.od...@daynix.com>
Reviewed-by: Philippe Mathieu-Daudé
---
co
This is just a constant alias register with the same value as the
"other" MIDR so it serves no purpose being presented to gdbstub.
Signed-off-by: Alex Bennée
---
target/arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
inde
Here are my final updates for the 8.2 cycle which I can hopefully
merge if we get enough review. Aside from the usual tweaks and fixes
there are two new features:
TCG Plugin Register Access
This is based on Akihiko's previously posted series with some changes
by myself. I wasn't keen on the plugi
From: Akihiko Odaki
GDBFeatureBuilder unifies the logic to generate dynamic GDBFeature.
Signed-off-by: Akihiko Odaki
Reviewed-by: Richard Henderson
Message-Id: <20231025093128.33116-4-akihiko.od...@daynix.com>
Signed-off-by: Alex Bennée
---
include/exec/gdbstub.h | 50 +++
Signed-off-by: Alex Bennée
---
gdb-xml/arm-neon.xml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gdb-xml/arm-neon.xml b/gdb-xml/arm-neon.xml
index 9dce0a996f..d61f6b8549 100644
--- a/gdb-xml/arm-neon.xml
+++ b/gdb-xml/arm-neon.xml
@@ -76,7 +76,7 @@
-
+
From: Akihiko Odaki
Currently the number of registers exposed to GDB is written as magic
numbers in code. Derive the number of registers GDB actually see from
XML files to replace the magic numbers in code later.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Ale
We already do a couple of "info registers" for specific tests but this
is a more comprehensive multiarch test. It also has some output
helpful for debugging the gdbstub by showing which XML features are
advertised and what the underlying register numbers are.
My initial motivation was to see if th
From: Akihiko Odaki
This function is useful to determine the number of registers exposed to
GDB from the XML name.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-Id: <20231025093128.33116-3-akihiko.od...@daynix
On 11/3/2023 1:33 PM, Daniel P. Berrangé wrote:
> On Fri, Nov 03, 2023 at 09:01:29AM -0700, Steve Sistare wrote:
>> Buffered monitor output is lost when abort() is called. The pattern
>> error_report() followed by abort() occurs about 60 times, so valuable
>> information is being lost when the abo
Greg Manning writes:
> V1-2:
> * Break up commit into separate commits
> * tidy up contrib/plugins/Makefile so the "if windows" and "if macos"
> conditions are symmetric.
Queued to maintainer/gdb-and-plugins-for-8.2, thanks.
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
On Thu, 26 Oct 2023 at 01:25, Richard Henderson
wrote:
>
> Tested-by: Mark Cave-Ayland
> Acked-by: Mark Cave-Ayland
> Signed-off-by: Richard Henderson
> +static TCGv do_rdgsr(DisasContext *dc, TCGv dst)
> +{
> +gen_trap_ifnofpu(dc);
> +return cpu_gsr;
> +}
> +
> +TRANS(RDGSR, 64, do_r
On the vexpress-a9 board we try to map both RAM and flash to address 0,
as seen in "info mtree":
address-space: memory
- (prio 0, i/o): system
-03ff (prio 0, romd): alias vexpress.flashalias
@vexpress.flash0 -00
On Tue, Oct 31, 2023 at 09:42:10AM -0700, Andrea Bolognani wrote:
> On Fri, Oct 27, 2023 at 07:33:30PM +0200, Victor Toso wrote:
> > Hi,
> >
> > Daniel & Andrea, it would be great to have your take on the Go
> > side of this series. If we can agree with an acceptable
> > 'unstable' version of Go mo
Convert the musicpal key input device to use
qemu_add_kbd_event_handler(). This lets us simplify it because we no
longer need to track whether we're in the middle of a PS/2 multibyte
key sequence.
In the conversion we move the keyboard handler registration from init
to realize, because devices sh
These two fields are adjusted by all FPop insns.
Having them separate makes it easier to set without masking.
Signed-off-by: Richard Henderson
---
target/sparc/cpu.h| 7 +-
target/sparc/helper.h | 2 +-
target/sparc/fop_helper.c | 46 ++-
tar
Represent each fcc field separately from the rest of fsr.
This vastly simplifies floating-point comparisons.
Signed-off-by: Richard Henderson
---
target/sparc/cpu.h| 20 +-
target/sparc/helper.h | 34 +--
target/sparc/fop_helper.c | 169 ++---
target/sparc/translate.c | 50
If an exception is to be raised, the destination fp register
should be unmodified. The current implementation is incorrect,
in that double results will be written back before calling
gen_helper_check_ieee_exceptions, despite the placement of
gen_store_fpr_D, since gen_dest_fpr_D returns cpu_fpr[].
Signed-off-by: Richard Henderson
---
target/sparc/helper.h | 4 ++--
target/sparc/fop_helper.c | 8
target/sparc/translate.c | 7 ---
3 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/target/sparc/helper.h b/target/sparc/helper.h
index 0a030fc908..e770107eb0 100644
Align the operation to the 32-byte cacheline.
Use 2 i128 instead of 4 i64.
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 29 ++---
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 5
Signed-off-by: Richard Henderson
---
target/sparc/helper.h | 4 ++--
target/sparc/fop_helper.c | 8
target/sparc/translate.c | 7 ---
3 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/target/sparc/helper.h b/target/sparc/helper.h
index e770107eb0..4cb3451878 100644
Signed-off-by: Richard Henderson
---
target/sparc/helper.h | 16 ++--
target/sparc/fop_helper.c | 23 +
target/sparc/translate.c | 54 +++
3 files changed, 41 insertions(+), 52 deletions(-)
diff --git a/target/sparc/helper.h b/targ
Don't do the clearing explicitly before each FPop,
rather do it as part of the rest of exception handling.
Signed-off-by: Richard Henderson
---
target/sparc/fop_helper.c | 2 ++
target/sparc/translate.c | 16
2 files changed, 2 insertions(+), 16 deletions(-)
diff --git a/targ
These are simple bit manipulation insns.
Begin using i128 for float128.
Implement FMOVq with do_qq.
Signed-off-by: Richard Henderson
---
target/sparc/helper.h | 6
target/sparc/fop_helper.c | 34 -
target/sparc/translate.c | 62 +++--
This field is read-only. It is easier to store it separately
and merge it only upon read.
While we're at it, use FSR_VER_SHIFT to initialize fpu_version.
Signed-off-by: Richard Henderson
---
target/sparc/cpu.h| 3 +++
target/sparc/cpu.c| 27 +--
target/
Signed-off-by: Richard Henderson
---
target/sparc/cpu.h | 4 +++-
target/sparc/helper.h | 1 +
linux-user/sparc/cpu_loop.c | 2 +-
linux-user/sparc/signal.c | 14 +-
target/sparc/cpu.c | 5 +++--
target/sparc/fop_helper.c | 21 ++--
targ
Major changes:
(1) Get rid of the env->qt[01] temporaries and use TCGv_i128 for float128.
(2) Perform ieee exception check within the helpers, before any writeback
to the floating point registers.
(3) Split env->fsr into pieces to simplify update, especially compares.
r~
Based-on: 2023110
Signed-off-by: Richard Henderson
---
target/sparc/helper.h | 4 ++--
target/sparc/fop_helper.c | 8
target/sparc/translate.c | 9 +
3 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/target/sparc/helper.h b/target/sparc/helper.h
index 5e93342583..20f67f89b0 100
Use them for trans_FMOVq.
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 25 +++--
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index cdc85be807..0e494d3ebd 100644
--- a/target/sparc/transl
These macros are no longer used.
Signed-off-by: Richard Henderson
---
target/sparc/cpu.h | 7 ---
1 file changed, 7 deletions(-)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 30bab9a7b3..9ca9fb30ff 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -202,13 +202,6 @@ en
These are no longer used for passing data to/from helpers.
Signed-off-by: Richard Henderson
---
target/sparc/cpu.h | 2 --
target/sparc/fop_helper.c | 3 ---
target/sparc/ldst_helper.c | 3 ---
3 files changed, 8 deletions(-)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 3
Replace with tcg_temp_new_i32.
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 17 ++---
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 713ac5bbae..cdc85be807 100644
--- a/target/sparc/translate
Align the operation to the 32-byte cacheline.
Use 2 pair of i128 instead of 8 pair of i32.
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 43 +++-
1 file changed, 25 insertions(+), 18 deletions(-)
diff --git a/target/sparc/translate.c b/targe
Signed-off-by: Richard Henderson
---
target/sparc/helper.h | 2 +-
target/sparc/fop_helper.c | 26 --
target/sparc/translate.c | 12 +++-
3 files changed, 32 insertions(+), 8 deletions(-)
diff --git a/target/sparc/helper.h b/target/sparc/helper.h
index 74a15
Signed-off-by: Richard Henderson
---
target/sparc/helper.h | 12 +---
target/sparc/fop_helper.c | 29 ++---
target/sparc/translate.c | 13 +++--
3 files changed, 26 insertions(+), 28 deletions(-)
diff --git a/target/sparc/helper.h b/target/sparc/helpe
Drop this field as a tcg global, loading it explicitly in the
few places required. This means that all FPop helpers may
once again be TCG_CALL_NO_WG.
Signed-off-by: Richard Henderson
---
target/sparc/helper.h | 120 +++---
target/sparc/fop_helper.c | 9 ++-
Signed-off-by: Richard Henderson
---
target/sparc/helper.h | 4 ++--
target/sparc/fop_helper.c | 8
target/sparc/translate.c | 9 +
3 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/target/sparc/helper.h b/target/sparc/helper.h
index 7caae9a441..5e93342583 100
Signed-off-by: Richard Henderson
---
target/sparc/helper.h | 2 +-
target/sparc/fop_helper.c | 8
target/sparc/translate.c | 15 ---
3 files changed, 9 insertions(+), 16 deletions(-)
diff --git a/target/sparc/helper.h b/target/sparc/helper.h
index 20f67f89b0..f7aeb311
On Fri, Nov 03, 2023 at 09:01:29AM -0700, Steve Sistare wrote:
> Buffered monitor output is lost when abort() is called. The pattern
> error_report() followed by abort() occurs about 60 times, so valuable
> information is being lost when the abort is called in the context of a
> monitor command.
The intention of the code appears to have been to unconditionally set
the multifunction bit but since the emulation mask is 0x00 it has no
effect. Instead, emulate the bit and set it based on the multifunction
property of the PCIDevice (which can be set using QAPI).
This allows making passthrough
On 03.11.23 17:44, Ilya Leoshkevich wrote:
On Tue, 2023-10-31 at 09:38 +0100, David Hildenbrand wrote:
On 31.10.23 06:32, Ilya Leoshkevich wrote:
Hi,
This series fixes two issues with updating CC. David was suggesting
a
bigger rewrite [1], but I did not dare do this (yet). Instead,
these
I s
On Tue, 2023-10-31 at 09:38 +0100, David Hildenbrand wrote:
> On 31.10.23 06:32, Ilya Leoshkevich wrote:
> > Hi,
> >
> > This series fixes two issues with updating CC. David was suggesting
> > a
> > bigger rewrite [1], but I did not dare do this (yet). Instead,
> > these
>
> I started coding that
Philippe Mathieu-Daudé writes:
> On 3/11/23 08:40, Markus Armbruster wrote:
>> Philippe Mathieu-Daudé writes:
>>
>>> Instead of having CPUs dangling in the /unattached/device
>>> bucket, attach them to the machine container.
>>>
>>> Signed-off-by: Philippe Mathieu-Daudé
>>> ---
>>> hw/ppc/e5
Look for read-after-write instead of overlap of reads and writes
Here is an example with overalp but no read-after-write:
0x000200fc: 0x38103876 { R0 = add(R0,R1); R6 = add(R6,R7) }
BEFORE:
000200fc
mov_i32 loc2,$0x0
mov_i32 loc2,r0
add_i32 loc3,loc2,r1
mov_i32 loc2,loc3
Look for read-after-write instead of overlap of reads and writes
HVX instructions with helpers have pass-by-reference semantics, so
we check for overlaps of reads and writes within the same instruction.
Signed-off-by: Taylor Simpson
---
target/hexagon/translate.h | 88 ++
This patch series improves the set of packets that can short-circuit
the commit packet logic and write the results directly during the
execution of each instruction in the packet.
The key observation is that checking for overlap between register reads
and writes is different from read-after-write.
We divide gen_analyze_funcs.py into 3 phases
Declare the operands
Analyze the register reads
Analyze the register writes
We also create special versions of ctx_log_*_read for new operands
Check that the operand is written before the read
This is a precursor to improving the analys
On Fri, 3 Nov 2023 at 16:02, Markus Armbruster wrote:
>
> Peter Maydell writes:
>
> > On Fri, 3 Nov 2023 at 03:08, John Snow wrote:
> >>
> >> On Wed, Oct 25, 2023 at 6:10 AM Markus Armbruster
> >> wrote:
> >> >
> >> > Pylint advises:
> >> >
> >> > docs/sphinx/qapidoc.py:518:12: W0707: Cons
Peter Maydell writes:
> On Fri, 3 Nov 2023 at 03:08, John Snow wrote:
>>
>> On Wed, Oct 25, 2023 at 6:10 AM Markus Armbruster wrote:
>> >
>> > Pylint advises:
>> >
>> > docs/sphinx/qapidoc.py:518:12: W0707: Consider explicitly re-raising
>> > using 'raise ExtensionError(str(err)) from err'
Buffered monitor output is lost when abort() is called. The pattern
error_report() followed by abort() occurs about 60 times, so valuable
information is being lost when the abort is called in the context of a
monitor command.
To fix, install a SIGABRT handler to flush the monitor buffer to stderr
On 03.11.23 16:51, Hanna Czenczek wrote:
On 20.10.23 23:56, Andrey Drobyshev wrote:
[...]
@@ -528,6 +543,14 @@ for use_backing_file in yes no; do
else
_make_test_img -o extended_l2=on 1M
fi
+ # Write cluster #0 and discard its subclusters #0-#3
+ $QEMU_IO -c 'write
Kevin Wolf writes:
> Am 03.11.2023 um 10:36 hat Markus Armbruster geschrieben:
>> Vladimir Sementsov-Ogievskiy writes:
>>
>> > On 11.10.23 13:18, Fiona Ebner wrote:
>> >> Am 10.10.23 um 19:55 schrieb Vladimir Sementsov-Ogievskiy:
>> >>> On 09.10.23 12:46, Fiona Ebner wrote:
>>
>> Init
On 20.10.23 23:56, Andrey Drobyshev wrote:
This commit makes the discard operation work on the subcluster level
rather than cluster level. It introduces discard_l2_subclusters()
function and makes use of it in qcow2 discard implementation, much like
it's done with zero_in_l2_slice() / zero_l2_su
On 20.10.23 23:56, Andrey Drobyshev wrote:
Add _verify_du_delta() checker which is used to check that real disk
usage delta meets the expectations. For now we use it for checking that
subcluster-based discard/unmap operations lead to actual disk usage
decrease (i.e. PUNCH_HOLE operation is perfo
Looks like a problem with git send-email ☹
I will troubleshoot ...
> -Original Message-
> From: Anton Johansson
> Sent: Thursday, November 2, 2023 6:44 PM
> To: Taylor Simpson
> Cc: qemu-devel@nongnu.org
> Subject: Re: [PATCH 0/3] Hexagon (target/hexagon) Enable more short-
> circuit p
On Fri, 3 Nov 2023 at 14:27, Peter Maydell wrote:
>
> On Fri, 3 Nov 2023 at 14:14, Sebastian Ott wrote:
> >
> > Since commit 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic")
> > PMU IRQ registration fails for arm64 guests:
> >
> > [0.563689] hw perfevents: unable to request IRQ14 for
On Fri, 3 Nov 2023 at 15:21, Peter Maydell wrote:
>
> From: Udo Steinberg
>
> Documentation for using the GAS in ACPI tables to report debug UART addresses
> at
> https://learn.microsoft.com/en-us/windows-hardware/drivers/bringup/acpi-debug-port-table
> states the following:
>
> - The Register B
Update the virt SPCR and DBG2 golden reference files to have the
fix for the description of the UART.
Diffs from iasl:
@@ -1,57 +1,57 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
- * Di
Allow changes to the virt board SPCR and DBG2 -- we are going to fix
an error in the UART descriptions there.
Signed-off-by: Peter Maydell
---
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qt
From: Udo Steinberg
Documentation for using the GAS in ACPI tables to report debug UART addresses at
https://learn.microsoft.com/en-us/windows-hardware/drivers/bringup/acpi-debug-port-table
states the following:
- The Register Bit Width field contains the register stride and must be a
power of
This patchseries is Udo's patch, plus the necessary extra patches
that update the golden-reference files for bios-tables-test so that
'make check' continues to pass.
Changes v2->v3:
* report the UART as requiring 32-bit accesses, not 16-bit;
it turns out that Linux has a bug where it fails to
On 20.10.23 23:56, Andrey Drobyshev wrote:
Move the definition from iotests/250 to common.rc. This is used to
detect real disk usage of sparse files. In particular, we want to use
it for checking subclusters-based discards.
Signed-off-by: Andrey Drobyshev
---
tests/qemu-iotests/250 |
On 20.10.23 23:56, Andrey Drobyshev wrote:
When zeroizing subclusters within single cluster, detect usage of the
BDRV_REQ_MAY_UNMAP flag and fall through to the subcluster-based discard
operation, much like it's done with the cluster-based discards. That
way subcluster-aligned operations "qemu-i
On 11/2/23 04:49, Philippe Mathieu-Daudé wrote:
Hi Daniel,
On 31/10/23 22:49, Daniel Henrique Barboza wrote:
On 10/30/23 11:39, Philippe Mathieu-Daudé wrote:
Following the discussion with Peter on my "cpus: Step toward
removing global 'first_cpu'" series [*], we now pass the array
of CPUs v
On Wed, Oct 25, 2023 at 3:08 AM Hawkins Jiawei wrote:
>
> Enable SVQ with VIRTIO_NET_F_RSS feature.
>
Acked-by: Eugenio Pérez
> Signed-off-by: Hawkins Jiawei
> ---
> v5:
> - no changes
>
> v4:
> https://lore.kernel.org/all/4ee7f3f339469f41626ca2c3ac7b1c574ebce901.1697904740.git.yin31...@gma
On Wed, Oct 25, 2023 at 3:08 AM Hawkins Jiawei wrote:
>
> This patch reuses vhost_vdpa_net_load_rss() with some
> refactorings to restore the receive-side scaling state
> at device's startup.
>
Acked-by: Eugenio Pérez
> Signed-off-by: Hawkins Jiawei
> ---
> v5:
> - resolve conflict with the
On Fri, 3 Nov 2023 at 14:14, Sebastian Ott wrote:
>
> Since commit 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic")
> PMU IRQ registration fails for arm64 guests:
>
> [0.563689] hw perfevents: unable to request IRQ14 for ARM PMU counters
> [0.565160] armv8-pmu: probe of pmu failed
On Wed, Oct 25, 2023 at 3:02 AM Hawkins Jiawei wrote:
>
> Enable SVQ with VIRTIO_NET_F_HASH_REPORT feature.
>
Acked-by: Eugenio Pérez
> Signed-off-by: Hawkins Jiawei
> ---
> v4:
> - no changes
>
> v3:
> https://lore.kernel.org/all/c3b69f0a65600722c1e4d3aa14d53a71e8ffb888.1697902949.git.yin3
On Wed, Oct 25, 2023 at 3:02 AM Hawkins Jiawei wrote:
>
> This patch introduces vhost_vdpa_net_load_rss() to restore
> the hash calculation state at device's startup.
>
> Signed-off-by: Hawkins Jiawei
> ---
> v4:
> - fix some typos pointed out by Michael
> - zero the `cfg` fields at the defin
Since commit 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic")
PMU IRQ registration fails for arm64 guests:
[0.563689] hw perfevents: unable to request IRQ14 for ARM PMU counters
[0.565160] armv8-pmu: probe of pmu failed with error -22
That commit re-defined VIRTUAL_PMU_IRQ to be
On Fri, Nov 03, 2023 at 08:42:45AM +0100, Juan Quintela wrote:
> We were not unlocking bitmap mutex on the error case. To fix it
> forever change to enclose the code with WITH_QEMU_LOCK_GUARD().
> Coverity CID 1523750.
>
> Fixes: a2326705e5 ("migration: Stop migration immediately in RDMA error
>
We have two instances of the setting/clearing a MISA bit from
env->misa_ext and env->misa_ext_mask pattern. And the next patch will
end up adding one more.
Create a helper to avoid code repetition.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: LIU Zhiwei
Rev
This CPU was suggested by Alistair [1] and others during the profile
design discussions. It consists of the bare 'rv64i' CPU with rva22u64
enabled by default, like an alias of '-cpu rv64i,rva22u64=true'.
Users now have an even easier way of consuming this user-mode profile by
doing '-cpu rva22u64'
We already track user choice for multi-letter extensions because we
needed to honor user choice when enabling/disabling extensions during
realize(). We refrained from adding the same mechanism for MISA
extensions since we didn't need it.
Profile support requires tne need to check for user choice f
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