On 10/11/23 22:09, Eric Auger wrote:
In vfio_realize, on the error path, we currently call
vfio_detach_device() after a successful vfio_attach_device.
While this looks natural, vfio_instance_finalize also induces
a vfio_detach_device(), and it seems to be the right place
instead as other resource
Hi Zhenzhong,
On 10/12/23 04:34, Duan, Zhenzhong wrote:
>
>> -Original Message-
>> From: Eric Auger
>> Sent: Thursday, October 12, 2023 4:10 AM
>> To: eric.auger@gmail.com; eric.au...@redhat.com; qemu-
>> de...@nongnu.org; alex.william...@redhat.com; c...@redhat.com; Duan,
>> Zhenzhon
From: Jeuk Kim
Fixed four ufs-related coverity issues.
The coverity issues and fixes are as follows
1. CID 1519042: Security issue with the rand() function
Changed to use a fixed value (0xab) instead of rand() as
the value for testing
2. CID 1519043: Dereference after null check
Removed useles
From: Jeuk Kim
The following changes since commit a51e5124a655b3dad80b36b18547cb1eca2c5eb2:
Merge tag 'pull-omnibus-111023-1' of https://gitlab.com/stsquad/qemu into
staging (2023-10-11 09:43:10 -0400)
are available in the Git repository at:
https://gitlab.com/jeuk20.kim/qemu.git tags/pul
From: Jeuk Kim
This patch fixes invalid ufs register fields.
This fixes an issue reported by Bin Meng that
caused ufs to fail over riscv.
Fixes: bc4e68d362ec ("hw/ufs: Initial commit for emulated
Universal-Flash-Storage")
Signed-off-by: Jeuk Kim
Reported-by: Bin Meng
Reviewed-by: Bin Meng
Te
Thomas Huth writes:
> Avoid using trivial variable names in macros, otherwise we get
> the following compiler warning when compiling with -Wshadow=local:
>
> In file included from ../../qemu/hw/display/virtio-gpu-virgl.c:19:
> ../../home/thuth/devel/qemu/hw/display/virtio-gpu-virgl.c:
> In funct
Thomas Huth writes:
> No need to declare a new variable with the same name here,
> we can simple re-use the one from the top of the function.
> With this change, the file now compiles fine with -Wshadow=local.
>
> Signed-off-by: Thomas Huth
Queued. Thanks!
Thomas Huth writes:
> Rename shadowing variables to make this code compilable
> with -Wshadow=local.
>
> Signed-off-by: Thomas Huth
Queued. Thanks!
On 2023/10/12 0:23, Alex Bennée wrote:
Akihiko Odaki writes:
MISA limits are common for all instances of a RISC-V CPU class so they
are better put into class.
Signed-off-by: Akihiko Odaki
---
target/riscv/cpu-qom.h | 2 +
target/riscv/cpu.h | 2 -
hw/riscv/boot.c |
Nina Schoetterl-Glausch writes:
> Clarify roles of different architectures.
> Also change things a bit in anticipation of additional members being
> added.
>
> Suggested-by: Markus Armbruster
> Signed-off-by: Nina Schoetterl-Glausch
> ---
>
>
> Reference to s390x docs added in patch 14
>
>
> q
On 2023/10/11 13:31, Philippe Mathieu-Daudé wrote:
On 11/10/23 05:25, LIU Zhiwei wrote:
On 2023/10/11 1:04, Richard Henderson wrote:
On 10/9/23 05:42, LIU Zhiwei wrote:
On 2023/10/9 19:02, Philippe Mathieu-Daudé wrote:
When CPUArchState* is available (here CPURISCVState*), we
can use the
GDBFeature has the num_regs member so use it where applicable to
remove magic numbers.
Signed-off-by: Akihiko Odaki
---
include/hw/core/cpu.h | 3 ++-
target/s390x/cpu.h | 2 --
gdbstub/gdbstub.c | 5 -
target/arm/cpu.c| 1 -
target/arm/cpu64.c | 1 -
target/avr/cpu
This demonstrates how a register can be read from a plugin.
Signed-off-by: Akihiko Odaki
---
docs/devel/tcg-plugins.rst | 10 +++-
contrib/plugins/execlog.c | 120 +++--
2 files changed, 97 insertions(+), 33 deletions(-)
diff --git a/docs/devel/tcg-plugins.rst
These members will be used to help plugins to identify registers.
The added members in instances of GDBFeature dynamically generated by
CPUs will be filled in later changes.
Signed-off-by: Akihiko Odaki
---
include/exec/gdbstub.h | 3 +++
gdbstub/gdbstub.c | 10 --
target/riscv/g
This is a tree-wide change to introduce GDBFeature parameter to
gdb_register_coprocessor(). The new parameter just replaces num_regs
and xml parameters for now. GDBFeature will be utilized to simplify XML
lookup in a following change.
Signed-off-by: Akihiko Odaki
Acked-by: Alex Bennée
---
inclu
This function is useful to determine the number of registers exposed to
GDB from the XML name.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
---
include/exec/gdbstub.h | 2 ++
gdbstub/gdbstub.c | 13 +
It is based on GDB protocol to ensure interface stability.
The timing of the vcpu init hook is also changed so that the hook will
get called after GDB features are initialized.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1706
Signed-off-by: Akihiko Odaki
---
include/qemu/qemu-plugin
In preparation for a change to use GDBFeature as a parameter of
gdb_register_coprocessor(), convert the internal representation of
dynamic feature from plain XML to GDBFeature.
Signed-off-by: Akihiko Odaki
Acked-by: Richard Henderson
---
target/arm/cpu.h | 21 +++
target/arm/internal
Simplify GDBRegisterState by replacing num_regs and xml members with
one member that points to GDBFeature.
Signed-off-by: Akihiko Odaki
Reviewed-by: Alex Bennée
---
gdbstub/gdbstub.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/gdbstub/gdbstub.c b/gdbstub/g
Now we know all instances of GDBFeature that is used in CPU so we can
traverse them to find XML. This removes the need for a CPU-specific
lookup function for dynamic XMLs.
Signed-off-by: Akihiko Odaki
---
include/exec/gdbstub.h | 2 +
gdbstub/gdbstub.c | 85 +++-
Align the parameters of gdb_get_reg_cb and gdb_set_reg_cb with the
gdb_read_register and gdb_write_register members of CPUClass to allow
to unify the logic to access registers of the core and coprocessors
in the future.
Signed-off-by: Akihiko Odaki
---
include/exec/gdbstub.h | 4 +-
target
Currently the number of registers exposed to GDB is written as magic
numbers in code. Derive the number of registers GDB actually see from
XML files to replace the magic numbers in code later.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
---
include
This avoids optimizations incompatible when reading registers.
Signed-off-by: Akihiko Odaki
---
accel/tcg/plugin-helpers.h | 3 ++-
include/exec/plugin-gen.h | 4 ++--
include/hw/core/cpu.h | 4 ++--
include/qemu/plugin.h | 3 +++
plugins/plugin.h | 5 +++--
accel/tcg/p
This function is no longer used.
Signed-off-by: Akihiko Odaki
---
include/hw/core/cpu.h | 4
target/arm/cpu.h | 6 --
target/ppc/cpu.h | 1 -
target/arm/cpu.c | 1 -
target/arm/gdbstub.c | 18 --
target/ppc/cpu_init.c | 3 ---
target/ppc/gdbstub.c |
In preparation for a change to use GDBFeature as a parameter of
gdb_register_coprocessor(), convert the internal representation of
dynamic feature from plain XML to GDBFeature.
Signed-off-by: Akihiko Odaki
---
target/riscv/cpu.h | 5 +--
target/riscv/cpu.c | 4 +--
target/riscv/gdbstub
The initialization and exit hooks will not affect the state of vCPU
outside TCG context, but they may depend on the state of vCPU.
Therefore, it's better to call plugin hooks after the vCPU state is
fully initialized and before it gets uninitialized.
Signed-off-by: Akihiko Odaki
---
cpu-target.c
gdb_find_feature() and gdb_find_feature_register() find registers.
gdb_read_register() actually reads registers.
Signed-off-by: Akihiko Odaki
---
include/exec/gdbstub.h | 5 +
gdbstub/gdbstub.c | 31 ++-
2 files changed, 35 insertions(+), 1 deletion(-)
diff
Based-on: <20231012054223.37870-1-akihiko.od...@daynix.com>
("[PATCH 0/4] gdbstub and TCG plugin improvements")
I and other people in the University of Tokyo, where I research processor
design, found TCG plugins are very useful for processor design exploration.
The feature we find missing is the
GDBFeatureBuilder unifies the logic to generate dynamic GDBFeature.
Signed-off-by: Akihiko Odaki
Reviewed-by: Richard Henderson
---
include/exec/gdbstub.h | 20 ++
gdbstub/gdbstub.c | 59 ++
2 files changed, 79 insertions(+)
diff --git a
In preparation for a change to use GDBFeature as a parameter of
gdb_register_coprocessor(), convert the internal representation of
dynamic feature from plain XML to GDBFeature.
Signed-off-by: Akihiko Odaki
Reviewed-by: Richard Henderson
---
target/ppc/cpu-qom.h | 4 ++--
target/ppc/cpu.h
misa_mxl_max is now a class member and initialized only once for each
class. This also moves the initialization of gdb_core_xml_file which
will be referenced before realization in the future.
Signed-off-by: Akihiko Odaki
---
target/riscv/cpu.c | 6 ++
1 file changed, 2 insertions(+), 4 delet
misa_mxl_max is common for all instances of a RISC-V CPU class so they
are better put into class.
Signed-off-by: Akihiko Odaki
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.h | 1 -
hw/riscv/boot.c | 2 +-
target/riscv/cpu.c | 127 +++
copy_call() has an unused parameter so remove it.
Signed-off-by: Akihiko Odaki
---
accel/tcg/plugin-gen.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
index 39b3c9351f..78b331b251 100644
--- a/accel/tcg/plugin-gen.c
It is initialized with a simple assignment and there is little room for
error. In fact, the validation is even more complex.
Signed-off-by: Akihiko Odaki
---
target/riscv/cpu.c | 13 ++---
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cp
This series extracts fixes and refactorings that can be applied
independently from "[PATCH v9 00/23] plugins: Allow to read registers".
The patch "target/riscv: Move MISA limits to class" was replaced with
patch "target/riscv: Move misa_mxl_max to class" since I found instances
may have different
Philippe Mathieu-Daudé writes:
> Hi Srivatsa,
>
> (+Markus/Peter for QOM fu)
QOM fu needs Paolo; cc'ed.
I'm not sure how much this is about QOM, though. Perhaps it's more
about good taste.
> On 11/10/23 18:52, Srivatsa Vaddagiri wrote:
>> Avoid dereferencing a NULL pointer that its_class_name
Hi Srivatsa,
On 11/10/23 18:52, Srivatsa Vaddagiri wrote:
Add gunyah.rst that provide some informaiton on how to build and test
'gunyah' accelerator with open-source Gunyah hypervisor.
Signed-off-by: Srivatsa Vaddagiri
---
MAINTAINERS| 1 +
docs/system/arm/gunyah.rst | 214
On 11/10/23 18:52, Srivatsa Vaddagiri wrote:
Complete the cpu execution loop. At this time, we recognize exits
associated with only MMIO access. Future patches will add support for
recognizing other exit reasons, such as PSCI calls made by guest.
Signed-off-by: Srivatsa Vaddagiri
---
accel/gu
> On 11-Oct-2023, at 10:01 PM, Jonathan Cameron
> wrote:
>
> On Wed, 11 Oct 2023 16:23:35 +0530
> Ani Sinha wrote:
>
>> pc_get_device_memory_range() finds the device memory size by calculating the
>> difference between maxram and ram sizes. This calculation makes sense only
>> when
>> maxr
On 11/10/23 18:52, Srivatsa Vaddagiri wrote:
Customize device-tree with Gunyah specific properties. Some of these
properties include specification of doorbells that need to be created
and associated with various interrupts.
Signed-off-by: Srivatsa Vaddagiri
---
hw/arm/virt.c | 11 ++
On 11/10/23 18:52, Srivatsa Vaddagiri wrote:
Specify the location of device-tree and its size, as Gunyah requires the
device-tree to be parsed before VM can begin its execution.
Signed-off-by: Srivatsa Vaddagiri
---
MAINTAINERS | 1 +
hw/arm/virt.c | 6 ++
includ
Hi Srivatsa,
On 11/10/23 18:52, Srivatsa Vaddagiri wrote:
Add a new accelerator, gunyah, with basic functionality of creating a
VM. Subsequent patches will add support for other functions required to
run a VM.
Signed-off-by: Srivatsa Vaddagiri
---
MAINTAINERS | 7 +++
Hi Srivatsa,
(+Markus/Peter for QOM fu)
On 11/10/23 18:52, Srivatsa Vaddagiri wrote:
Avoid dereferencing a NULL pointer that its_class_name() could return.
While your patch is correct, there is some code smell
around its_class_name(). IMHO a foo_class_name() handler
should never return NULL.
- Use QOM DEFINE_TYPES
- Rename few functions
- Replace magic value by definition
Philippe Mathieu-Daudé (3):
hw/pci-host/sh_pcic: Declare CPU QOM types using DEFINE_TYPES() macro
hw/pci-host/sh_pcic: Correct PCI host / devfn#0 function names
hw/pci-host/sh_pcic: Replace magic value by prope
From: Clément Chigot
This replaces the exit calls by shutdown requests, ensuring a proper
cleanup of Qemu. Features like net/vhost-vdpa.c are expecting
qemu_cleanup to be called to remove their last residuals.
Signed-off-by: Clément Chigot
Reviewed-by: Alistair Francis
Message-ID: <20231003071
From: Clément Chigot
This replaces the exit calls by shutdown requests, ensuring a proper
cleanup of Qemu. Otherwise, some connections like gdb could be broken
before its final packet ("Wxx") is being sent. This part, being done
inside qemu_cleanup function, can be reached only when the main loop
From: Daniel Henrique Barboza
KVM for RISC-V started supporting KVM_GET_REG_LIST in Linux 6.6. It
consists of a KVM ioctl() that retrieves a list of all available regs
for get_one_reg/set_one_reg. Regs that aren't present in the list aren't
supported in the host.
This simplifies our lives when i
From: Daniel Henrique Barboza
Enabling RVG will enable a set of extensions that we're not checking if
the user was okay enabling or not. And in this case we want to error
out, instead of ignoring, otherwise we will be inconsistent enabling RVG
without all its extensions.
After this patch, disabl
From: Clément Chigot
As of now, the exit code was either EXIT_FAILURE when a panic shutdown
was requested or EXIT_SUCCESS otherwise.
However, some hardware could want to pass more complex exit codes. Thus,
introduce a new shutdown request function allowing that.
Signed-off-by: Clément Chigot
Re
From: Daniel Henrique Barboza
Move the remaining of riscv_tcg_ops now that we have a working realize()
implementation.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Andrew Jones
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Message-ID: <2023
From: Daniel Henrique Barboza
target/riscv/cpu.c needs to handle all possible accelerators (TCG and
KVM at this moment) during both init() and realize() time. This forces
us to resort to a lot of "if tcg" and "if kvm" throughout the code,
which isn't wrong, but can get cluttered over time. Splitt
From: Daniel Henrique Barboza
This function is used for both accelerators. Make it public, and call it
from kvm_riscv_cpu_add_kvm_properties(). This will make it easier to
split KVM specific code for the KVM accelerator class in the next patch.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by
When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. In
particular because type array declared with such macro
are easier to review.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/sh_pci.c | 40 +---
From: Daniel Henrique Barboza
This CPU only exists if we're compiling with KVM so move it to the kvm
specific file.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Andrew Jones
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Message-ID: <2023092
From: Daniel Henrique Barboza
Add a new cpu_cfg_ext_is_user_set() helper to check if an extension was
set by the user in the command line. Use it inside
cpu_cfg_ext_auto_update() to verify if the user set a certain extension
and, if that's the case, do not change its value.
This will make us hon
From: Clément Chigot
This replaces the exit calls by shutdown requests, ensuring a proper
cleanup of Qemu. Otherwise, some connections like gdb could be broken
before its final packet ("Wxx") is being sent. This part, being done
inside qemu_cleanup function, can be reached only when the main loop
From: Daniel Henrique Barboza
riscv_cpu_add_misa_properties() is being used to fill the missing KVM
MISA properties but it is a TCG helper that was adapted to do so. We'll
move it to tcg-cpu.c in the next patches, meaning that KVM needs to fill
the remaining MISA properties on its own.
Do not us
From: Daniel Henrique Barboza
We'll introduce generic errors that will output a CPU type name via its
RISCVCPU pointer. Create a helper for that.
Use the helper in tcg_cpu_realizefn() instead of hardcoding the 'host'
CPU name.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Franci
From: Daniel Henrique Barboza
Add a KVM accelerator class like we did with TCG. The difference is
that, at least for now, we won't be using a realize() implementation for
this accelerator.
We'll start by assiging kvm_riscv_cpu_add_kvm_properties(), renamed to
kvm_cpu_instance_init(), as a 'cpu_i
From: Max Chou
The operator (fwmacc16) of vfwmaccbf16.vf helper function should be
replaced by fwmaccbf16.
Fixes: adf772b0f7 ("target/riscv: Add support for Zvfbfwma extension")
Signed-off-by: Max Chou
Reviewed-by: LIU Zhiwei
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20231005095734.567
From: Daniel Henrique Barboza
At this moment we do not expose extension properties for vendor CPUs
because that would allow users to change them via command line. The
drawback is that if we were to add an API that shows all CPU properties,
e.g. qmp-query-cpu-model-expansion, we won't be able to s
From: Daniel Henrique Barboza
Create a new riscv_cpu_experimental_exts[] to store the non-ratified
extensions properties. Once they are ratified we'll move them back to
riscv_cpu_extensions[].
riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties() are
changed to keep adding non-ratif
From: Daniel Henrique Barboza
This array will be read by the TCG accel class, allowing it to handle
priv spec verifications on its own. The array will remain here in cpu.c
because it's also used by the riscv,isa string function.
To export it we'll finish it with an empty element since ARRAY_SIZE
From: "Richard W.M. Jones"
RISCV_CPU(cs) uses a checked cast. When QOM cast debugging is enabled
this adds about 5% total overhead when emulating RV64 on x86-64 host.
Using a RISC-V guest with 16 vCPUs, 16 GB of guest RAM, virtio-blk
disk. The guest has a copy of the qemu source tree. The tes
From: Daniel Henrique Barboza
Our error message is returning the value of 'ret', which will be always
-1 in case of error, and will not be that useful:
qemu-system-riscv64: Unable to read ISA_EXT KVM register ssaia, error -1
Improve the error message by outputting 'errno' instead of 'ret'. Use
From: Daniel Henrique Barboza
Priv spec validation is TCG specific. Move it to the TCG accel class.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20230925175709.35696-20-dbarb...@ventanamicro.co
From: Daniel Henrique Barboza
Our goal is to make riscv_cpu_extensions[] hold only ratified,
non-vendor extensions.
Create a new riscv_cpu_vendor_exts[] array for them, changing
riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties()
accordingly.
Signed-off-by: Daniel Henrique Barboz
From: Daniel Henrique Barboza
We'll add a new CPU type that will enable a considerable amount of
extensions. To make it easier for us we'll do a few cleanups in our
existing riscv_cpu_extensions[] array.
Start by splitting all CPU non-boolean options from it. Create a new
riscv_cpu_options[] arr
From: Daniel Henrique Barboza
We'll need to export these arrays to the accelerator classes in the next
patches. Mark them as 'const' now because they should not be modified at
runtime.
Note that 'riscv_cpu_options' will also be exported, but can't be marked
as 'const', because the properties are
From: Daniel Henrique Barboza
All generic CPUs call riscv_cpu_add_user_properties(). The 'max' CPU
calls riscv_init_max_cpu_extensions(). Both can be moved to a common
instance_post_init() callback, implemented in riscv_cpu_post_init(),
called by all CPUs. The call order then becomes:
riscv_cpu_
From: Daniel Henrique Barboza
Inside riscv_cpu_validate_v() we're always throwing a log message if the
user didn't set a vector version via 'vext_spec'.
We're going to include one case with the 'max' CPU where env->vext_ver
will be set in the cpu_init(). But that alone will not stop the "vector
From: Daniel Henrique Barboza
We'll move riscv_init_max_cpu_extensions() to tcg-cpu.c in the next
patch and set_misa() needs to be usable from there.
Rename it to riscv_cpu_set_misa() and make it public.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: A
From: Daniel Henrique Barboza
Let's change the other instances in realize() where we're enabling an
extension based on a certain criteria (e.g. it's a dependency of another
extension).
We're leaving icsr and ifencei being enabled during RVG for later -
we'll want to error out in that case. Every
From: Daniel Henrique Barboza
We'll introduce the KVM accelerator class with a 'cpu_instance_init'
implementation that is going to be invoked during the common
riscv_cpu_post_init() (via accel_cpu_instance_init()). This
instance_init will execute KVM exclusive code that TCG doesn't care
about, su
From: Daniel Henrique Barboza
If we want to make better decisions when auto-enabling extensions during
realize() we need a way to tell if an user set an extension manually.
The RISC-V KVM driver has its own solution via a KVMCPUConfig struct
that has an 'user_set' flag that is set during the Prop
From: Daniel Henrique Barboza
Before adding support to detect if an extension was user set we need to
handle how we're enabling extensions in riscv_init_max_cpu_extensions().
object_property_set_bool() calls the set() callback for the property,
and we're going to use this callback to set the 'mul
From: Daniel Henrique Barboza
tcg_cpu_instance_init() will be the 'cpu_instance_init' impl for the TCG
accelerator. It'll be called from within riscv_cpu_post_init(), via
accel_cpu_instance_init(), similar to what happens with KVM. In fact, to
preserve behavior, the implementation will be similar
From: Daniel Henrique Barboza
Move the files to a 'kvm' dir to promote more code separation between
accelerators and making our lives easier supporting build options such
as --disable-tcg.
Rename kvm.c to kvm-cpu.c to keep it in line with its TCG counterpart.
Signed-off-by: Daniel Henrique Barb
From: Daniel Henrique Barboza
riscv_cpu_realize_tcg() was added to allow TCG cpus to have a different
realize() path during the common riscv_cpu_realize(), making it a good
choice to start moving TCG exclusive code to tcg-cpu.c.
Rename it to tcg_cpu_realizefn() and assign it as a implementation
From: Daniel Henrique Barboza
Add DEFINE_PROP_END_OF_LIST() and eliminate the ARRAY_SIZE() usage when
iterating in the riscv_cpu_options[] array, making it similar to what
we already do when working with riscv_cpu_extensions[].
We also have a more sophisticated motivation behind this change. In
From: Daniel Henrique Barboza
The 'max' CPU type is used by tooling to determine what's the most
capable CPU a current QEMU version implements. Other archs such as ARM
implements this type. Let's add it to RISC-V.
What we consider "most capable CPU" in this context are related to
ratified, non-v
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/sh_pci.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/pci-host/sh_pci.c b/hw/pci-host/sh_pci.c
index 580e273d96..4edebced5e 100644
--- a/hw/pci-host/sh_pci.c
+++ b/hw/pci-host/sh_pci.c
@@ -40,7 +40,7 @@ struct SH
From: Daniel Henrique Barboza
All code related to MISA TCG properties is also moved.
At this point, all TCG properties handling is done in tcg-cpu.c, all KVM
properties handling is done in kvm-cpu.c.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Franci
From: Daniel Henrique Barboza
This file is not needed for some time now. Both kvm_riscv_reset_vcpu()
and kvm_riscv_set_irq() have public declarations in kvm_riscv.h and are
wrapped in 'if kvm_enabled()' blocks that the compiler will rip it out
in non-KVM builds.
Signed-off-by: Daniel Henrique Ba
From: Daniel Henrique Barboza
At this moment there are eleven CPU extension properties that starts
with capital 'Z': Zifencei, Zicsr, Zihintntl, Zihintpause, Zawrs, Zfa,
Zfh, Zfhmin, Zve32f, Zve64f and Zve64d. All other extensions are named
with lower-case letters.
We want all properties to be n
From: Daniel Henrique Barboza
The array isn't marked as 'const' because we're initializing their
elements in riscv_cpu_add_misa_properties(), 'name' and 'description'
fields.
In a closer look we can see that we're not using these 2 fields after
creating the MISA properties. And we can create the
From: Clément Chigot
gdb_exit function aims to close gdb sessions and sends the exit code of
the current execution. It's being called by qemu_cleanup once the main
loop is over.
Until now, the exit code sent was always 0. Now that hardware can
shutdown this main loop with custom exit codes, these
From: Daniel Henrique Barboza
Vendor CPUs that set RVG are displaying user warnings about other
extensions that RVG must enable, one warning per CPU. E.g.:
$ ./build/qemu-system-riscv64 -smp 8 -M virt -cpu veyron-v1 -nographic
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zif
Host bridge device and PCI function #0 are inverted.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/sh_pci.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/pci-host/sh_pci.c b/hw/pci-host/sh_pci.c
index 41aed48c85..580e273d96 100644
--- a/hw/pci-ho
From: Daniel Henrique Barboza
After the introduction of riscv_cpu_options[] all properties in
riscv_cpu_extensions[] are booleans. This check is now obsolete.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Message-ID: <20230912132423.268494-3-db
From: Daniel Henrique Barboza
The RISC-V KVM driver uses a CPUCFG() macro that calculates the offset
of a certain field in the struct RISCVCPUConfig. We're going to use this
macro in target/riscv/cpu.c as well in the next patches. Make it public.
Rename it to CPU_CFG_OFFSET() for more clarity wh
From: Daniel Henrique Barboza
Use a helper in riscv_cpu_add_kvm_properties() to eliminate some of its
code repetition.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Message-ID: <20230912132423.268494-9-dbarb...@ventanamicro.com>
Signed-off-by:
From: Daniel Henrique Barboza
We'll have future usage for a function where, given an offset of the
struct RISCVCPUConfig, the flag is updated to a certain val.
Change all existing callers to use edata->ext_enable_offset instead of
'edata'.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Al
From: Daniel Henrique Barboza
During realize() time we're activating a lot of extensions based on some
criteria, e.g.:
if (cpu->cfg.ext_zk) {
cpu->cfg.ext_zkn = true;
cpu->cfg.ext_zkr = true;
cpu->cfg.ext_zkt = true;
}
This practice resulted in at least one case
From: Daniel Henrique Barboza
This function is the core of the RISC-V validations for TCG CPUs, and it
has a lot going on.
Functions in cpu.c were made public to allow them to be used by the KVM
accelerator class later on. 'cpu_cfg_ext_get_min_version()' is notably
hard to move it to another fil
From: Daniel Henrique Barboza
The 'any' CPU type was introduced in commit dc5bd18fa5725 ("RISC-V CPU
Core Definition"), being around since the beginning. It's not an easy
CPU to use: it's undocumented and its name doesn't tell users much about
what the CPU is supposed to bring. 'git log' doesn't
The following changes since commit a51e5124a655b3dad80b36b18547cb1eca2c5eb2:
Merge tag 'pull-omnibus-111023-1' of https://gitlab.com/stsquad/qemu into
staging (2023-10-11 09:43:10 -0400)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-
From: Daniel Henrique Barboza
Future patches will split the existing Property arrays even further, and
the existing code in riscv_cpu_add_user_properties() will start to scale
bad with it because it's dealing with KVM constraints mixed in with TCG
constraints. We're going to pay a high price to s
From: "liguang.zhang"
This patch fixes guest reboot errors when using KVM.
There are two issues when rebooting a guest using KVM
1. When the guest initiates a reboot the host is unable to stop the vcpu
2. When running a SMP guest the qemu monitor system_reset causes a vcpu crash
This can be fix
From: Alvin Chang
Fix the inverted order of pmpaddr13 and pmpaddr14 in csr_name().
Signed-off-by: Alvin Chang
Reviewed-by: Alistair Francis
Message-ID: <20230907084500.328-1-alvi...@andestech.com>
Signed-off-by: Alistair Francis
---
disas/riscv.c | 4 ++--
1 file changed, 2 insertions(+), 2
1 - 100 of 525 matches
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