The dolog macro is unused. Remove the macro and use the now unused
ES1370_VERBOSE macro to replace its inverse ES1370_SILENT macro.
Tested-by: Rene Engel
Signed-off-by: Volker Rümelin
---
hw/audio/es1370.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/hw/audio/es1370.c b/hw/audio/es
It seems that nobody has enabled the debug code of the ES1370
device for a long time. Since then, the code has bit-rotted.
Replace the bit-rotten code with tracepoints.
Tested-by: Rene Engel
Signed-off-by: Volker Rümelin
---
hw/audio/es1370.c | 55 ++-
Change the block structure according to the QEMU Coding Style
documentation.
Signed-off-by: Volker Rümelin
---
hw/audio/es1370.c | 36
1 file changed, 16 insertions(+), 20 deletions(-)
diff --git a/hw/audio/es1370.c b/hw/audio/es1370.c
index e1ca6a4cd5..86a8
It turns out that there are drivers which assume that interrupts
can't be lost. E.g. the AROS sb128 driver is such a driver. Add
a lost interrupt tracepoint to debug this kind of issues.
Signed-off-by: Volker Rümelin
---
hw/audio/es1370.c | 14 ++
hw/audio/trace-events | 3 ++-
Replace the #ifdef ES1370_DEBUG code with code that the compiler
can optimize away to avoid bit rot. While at it, replace strcat()
with pstrcat().
Tested-by: Rene Engel
Signed-off-by: Volker Rümelin
---
hw/audio/es1370.c | 135 +++---
1 file changed, 66 i
Change the type of the variable temp to size_t to avoid a type
cast. While at it, rename the variable name to to_transfer. This
improves the readability of the code.
Signed-off-by: Volker Rümelin
---
hw/audio/es1370.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --
Replace the #ifdef ES1370_VERBOSE code with code that the compiler
can optimize away to avoid bit rot and fix the already rotten code.
Tested-by: Rene Engel
Signed-off-by: Volker Rümelin
---
hw/audio/es1370.c | 25 +
1 file changed, 13 insertions(+), 12 deletions(-)
dif
Reset the current sample counter when writing the Channel Sample
Count Register. The Linux ens1370 driver and the AROS sb128
driver expect the current sample counter counts down from sample
count to 0 after a write to the Channel Sample Count Register.
Currently the current sample counter starts fr
Cc: qemu-stable. Patch 1/8 is a bug fix.
Cc: more people. The maintainer of hw/audio is busy with other projects.
Earlier this year I was asked if I could help to debug an audio playback
speed issue with the es1370 device. While debugging the playback speed
error, I noticed that the debug code of
On Sat, Sep 16, 2023 at 06:42:04PM +0800, Akihiko Odaki wrote:
> On 2023/09/16 19:32, Huang Rui wrote:
> > On Fri, Sep 15, 2023 at 11:20:46PM +0800, Akihiko Odaki wrote:
> >> On 2023/09/15 20:11, Huang Rui wrote:
> >>> Patch "virtio-gpu: CONTEXT_INIT feature" has added the context_init
> >>> featur
On 2023/09/17 14:45, Huang Rui wrote:
On Sat, Sep 16, 2023 at 06:42:04PM +0800, Akihiko Odaki wrote:
On 2023/09/16 19:32, Huang Rui wrote:
On Fri, Sep 15, 2023 at 11:20:46PM +0800, Akihiko Odaki wrote:
On 2023/09/15 20:11, Huang Rui wrote:
Patch "virtio-gpu: CONTEXT_INIT feature" has added th
Am Donnerstag, 14. September 2023, 03:22:49 CEST schrieb Andreas K. Huettel:
> > > https://lists.gnu.org/archive/html/bug-bash/2023-09/msg00119.html
> > > ^ Here I'm trying to find out more.
> > >
> > > Bash tests apparently indicate that argv[0] is overwritten, and that
> > > reading through a pip
Use new registers for the output, so that we never overlap
the input address, which could happen for user-only.
This avoids a "tmp = addr + 0" in that case.
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 2 +-
tcg/loongarch64/tcg-target.c.inc | 17 +++---
Constraint with two outputs, both in new registers.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 604fa9bf3e..fdbf79689a 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -644,6 +644,7 @@ static void tcg_out_movext3(TC
Signed-off-by: Richard Henderson
---
host/include/loongarch64/host/cpuinfo.h | 21 +++
util/cpuinfo-loongarch.c| 35 +
util/meson.build| 2 ++
3 files changed, 58 insertions(+)
create mode 100644 host/include/loongarch6
While loongarch64 does not have a 128-bit cmpxchg, it does
have 128-bit atomic load and store via the vector unit.
Signed-off-by: Richard Henderson
---
.../include/loongarch64/host/atomic128-ldst.h | 52 +++
.../loongarch64/host/load-extract-al16-al8.h | 39 ++
.../l
Store bytes under a mask is fundamentally a cmpxchg, not a straight store.
Use HAVE_CMPXCHG128 instead of HAVE_ATOMIC128_RW.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 2 +-
accel/tcg/ldst_atomicity.c.inc | 10 +-
2 files changed, 6 insertions(+), 6 deletions(
We handled the HAVE_ATOMIC128_RW case with atomic16_set at the top of
the function; the only thing left for a host without that support is
to fall through to cpu_loop_exit_atomic.
Signed-off-by: Richard Henderson
---
accel/tcg/ldst_atomicity.c.inc | 4
1 file changed, 4 deletions(-)
diff -
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.h | 8
tcg/loongarch64/tcg-target.c.inc | 8 +---
2 files changed, 5 insertions(+), 11 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
index 03017672f6..1bea15b02e 100644
--- a/
For tcg generated code, use new registers with load so that we never
overlap the input address, so that we can simplify address build for
64-bit user-only.
For tcg out-of-line code, implement the host/ headers to for atomic 128-bit
load and store, reducing the cases for which we must raise EXCP_AT
This function is now empty, so remove it. In the case of
m68k and tricore, this empties the class instance initfn,
so remove those as well.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 10 --
target/alpha/cpu.c | 2 --
target/
From: Philippe Mathieu-Daudé
While these functions are not TCG specific, they are not target
specific. Move them to "exec/cpu-common.h" so their callers don't
have to be tainted as target specific.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johansson
Message-Id: <20230914185718.7
From: Philippe Mathieu-Daudé
Remove the unused "exec/exec-all.h" header. There is
no more target specific code in it: make it target
agnostic (rename using the '-common' suffix). Since
it is TCG specific, move it to accel/tcg, updating
MAINTAINERS.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed
From: Anton Johansson
The prototype of do_[st|ld]*_mmu() is unified between system- and
user-mode allowing a large chunk of helper_[st|ld]*() and cpu_[st|ld]*()
functions to be expressed in same manner between both modes. These
functions will be moved to ldst_common.c.inc in a following commit.
Verify that the distance between CPUNegativeOffsetState and
CPUArchState is no greater than any alignment requirements.
Reviewed-by: Anton Johansson
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/exec/cpu-all.h b/inc
From: Philippe Mathieu-Daudé
accel-blocker.c is not target specific, move it to system_ss[].
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johansson
Message-Id: <20230914185718.76241-5-phi...@linaro.org>
Signed-off-by: Richard Henderson
---
accel/meson.build | 4 ++--
1 file chang
From: Philippe Mathieu-Daudé
We have exec/cpu code split in 2 files for target agnostic
("common") and specific. Rename 'cpu.c' which is target
specific using the '-target' suffix. Update MAINTAINERS.
Remove the 's from 'cpus-common.c' to match the API cpu_foo()
functions.
Signed-off-by: Philipp
From: Anton Johansson
A large chunk of ld/st functions are moved from cputlb.c and user-exec.c
to ldst_common.c.inc as their implementation is the same between both
modes.
Eventually, ldst_common.c.inc could be compiled into a separate
target-specific compilation unit, and be linked in with the
From: Anton Johansson
Makes ldst_atomicity.c.inc almost target-independent, with the exception
of TARGET_PAGE_MASK, which will be addressed in a future patch.
Signed-off-by: Anton Johansson
Message-Id: <20230912153428.17816-8-a...@rev.ng>
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Ma
From: Philippe Mathieu-Daudé
accel/tcg/internal.h contains target specific declarations.
Unit files including it become "target tainted": they can not
be compiled as target agnostic. Rename using the '-target'
suffix to make this explicit.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anto
From: Philippe Mathieu-Daudé
Move target-agnostic declarations from "internal-target.h"
to a new "internal-common.h" header.
monitor.c now don't include target specific headers and can
be compiled once in system_ss[].
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johansson
Message-I
From: Philippe Mathieu-Daudé
In commit 00c9a5c2c3 ("accel/tcg: Restrict 'qapi-commands-machine.h'
to system emulation") we moved the definition to accel/tcg/ which is
where this function is called. No need to expose it outside.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johansson
Inherit the size and alignment from TYPE_ARM_CPU.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 3 ---
target/arm/cpu64.c | 4
2 files changed, 7 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index b9e09a702d..d48a70c039 1006
From: Anton Johansson
do_[ld|st]*() and mmu_lookup*() are changed to use CPUState over
CPUArchState, moving the target-dependence to the target-facing facing
cpu_[ld|st] functions.
Signed-off-by: Anton Johansson
Message-Id: <20230912153428.17816-6-a...@rev.ng>
Reviewed-by: Richard Henderson
Re
Now that there is no padding between CPUNegativeOffsetState
and CPUArchState, this value is constant across all targets.
Reviewed-by: Anton Johansson
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 1 -
accel/tcg/translate-all.c | 2 --
tcg/tcg.c | 15
Reviewed-by: Anton Johansson
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 1 -
include/hw/core/cpu.h| 9 ++---
target/arm/common-semi-target.h | 2 +-
accel/tcg/cpu-exec.c | 8
accel/tcg/cputlb.c
From: Philippe Mathieu-Daudé
Currently accel_cpu_realize() only performs target-specific
realization. Introduce the [un]realize_cpu fields in the
base AccelClass to be able to perform target-agnostic
[un]realization of vCPUs.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20230915190009.684
From: Philippe Mathieu-Daudé
We use the '-common.c' suffix for target agnostic units.
This file is target specific, rename it using the '-target'
suffix.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johansson
Message-Id: <20230914185718.76241-6-phi...@linaro.org>
Signed-off-by: Ric
From: Philippe Mathieu-Daudé
The EXCP_* definitions don't need to be target specific,
move them to "exec/cpu-common.h".
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johansson
Message-Id: <20230914185718.76241-2-phi...@linaro.org>
Signed-off-by: Richard Henderson
---
include/exec/
Now that CPUNegativeOffsetState is part of CPUState,
we can reference it directly.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 11 ---
include/exec/exec-all.h | 2 +-
accel/tcg/cpu-exec.c | 14 +++-
From: Philippe Mathieu-Daudé
Prepare the stub for parity with accel_cpu_realize().
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20230915190009.68404-3-phi...@linaro.org>
Signed-off-by: Richard Henderson
---
include/qemu/accel.h | 6 ++
accel/accel-target.c | 4
cpu-target.c
From: Anton Johansson
The goal is to (in the future) allow for per-target compilation of
functions in atomic_template.h whilst atomic_mmu_lookup() and cputlb.c
are compiled once-per user- or system mode.
Signed-off-by: Anton Johansson
Message-Id: <20230912153428.17816-7-a...@rev.ng>
Reviewed-by
From: Philippe Mathieu-Daudé
cpu_in_serial_context() is not target specific,
move it declaration to "internal-common.h" (which
we include in the 4 source files modified).
Remove the unused "exec/exec-all.h" header from
cpu-exec-common.c. There is no more target specific
code in this file: make
We can now access icount_decr directly.
Reviewed-by: Anton Johansson
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 1 -
include/hw/core/cpu.h | 2 --
hw/core/cpu-common.c | 4 ++--
3 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/include/exec/cpu-all.h b/include
From: Philippe Mathieu-Daudé
We don't need to expose these TCG-specific methods to the
whole code base. Register them as AccelClass handlers, they
will be called by the generic accel_cpu_[un]realize() methods.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20230915190009.68404-6-phi...@lina
From: Philippe Mathieu-Daudé
We use the '*fn' suffix for handlers, this is a public method.
Drop the suffix.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20230915190009.68404-2-phi...@linaro.org>
Signed-off-by: Richard Henderson
---
include/qemu/accel.h | 4 ++--
accel/accel-target
Accept that we will consume space in CPUState for CONFIG_USER_ONLY,
since we cannot test CONFIG_SOFTMMU within hw/core/cpu.h.
Reviewed-by: Anton Johansson
Signed-off-by: Richard Henderson
---
include/exec/cpu-defs.h | 150
include/hw/core/cpu.h | 141 +
Retain the separate structure to emphasize its importance.
Enforce CPUArchState always follows CPUState without padding.
Reviewed-by: Anton Johansson
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h| 22 +-
include/hw/core/cpu.h | 17 +++--
tar
Propagate alignment just like size. This is required in order to
get the correct alignment on most cpu subclasses where the size and
alignment is only specified for the base cpu type.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
qom/object.c | 14 ++
1 f
From: Anton Johansson
TARGET_PAGE_ENTRY_EXTRA is a macro that allows guests to specify additional
fields for caching with the full TLB entry. This macro is replaced with
a union in CPUTLBEntryFull, thus making CPUTLB target-agnostic at the
cost of slightly inflated CPUTLBEntryFull for non-arm gu
Omnibus cleanups for making more code target agnostic.
r~
Based-on: 20230916171223.521545-1-richard.hender...@linaro.org
("[PULL v2 00/39] tcg patch queue")
Supercedes: 20230914024435.1381329-1-richard.hender...@linaro.org
("[PATCH v2 00/24] Reduce usage of CPUArchState in cputlb.c")
Supercede
Replace the single use within env_tlb() and remove.
Reviewed-by: Anton Johansson
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 13 +
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 477e59b4b3..af9516
From: Philippe Mathieu-Daudé
This matches the target agnostic 'page-vary-common.c' counterpart.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johansson
Message-Id: <20230914185718.76241-8-phi...@linaro.org>
Signed-off-by: Richard Henderson
---
MAINTAINERS | 2
From: Philippe Mathieu-Daudé
Following the example documented since commit e3fe3988d7 ("error:
Document Error API usage rules"), have tcg_exec_realizefn() return
a boolean indicating whether an error is set or not.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20230915190009.68404-5-phi...
Minimize the displacement to can_do_io, since it may
be touched at the start of each TranslationBlock.
It fits into other padding within the substructure.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h| 2 +-
accel/dummy-cpus.c
The omission of alignment has technically been wrong since
269bd5d8f61, where QEMU_ALIGNED was added to CPUTLBDescFast.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/alpha/cpu.c | 1 +
target/avr/cpu.c| 1 +
target/cris/cpu.c | 1 +
target/he
From: Anton Johansson
The function is no longer used to access the TLB,
and has been replaced by cpu->neg.tlb.
Signed-off-by: Anton Johansson
Message-Id: <20230912153428.17816-9-a...@rev.ng>
Reviewed-by: Richard Henderson
[rth: Merge comment update patch]
Signed-off-by: Richard Henderson
---
From: Anton Johansson
probe_access_internal() is changed to instead take the generic CPUState
over CPUArchState, in order to lessen the target-specific coupling of
cputlb.c. Note: probe_access*() also don't need the full CPUArchState,
but aren't touched in this patch as they are target-facing.
S
From: Anton Johansson
Changes tlb_*() functions to take CPUState instead of CPUArchState, as
they don't require the full CPUArchState. This makes it easier to
decouple target-(in)dependent code.
Signed-off-by: Anton Johansson
Message-Id: <20230912153428.17816-4-a...@rev.ng>
Reviewed-by: Richard
From: Mikulas Patocka
qemu-hppa may crash when delivering a signal. It can be demonstrated with
this program. Compile the program with "hppa-linux-gnu-gcc -O2 signal.c"
and run it with "qemu-hppa -one-insn-per-tb a.out". It reports that the
address of the flag is 0xb4 and it crashes when attempti
From: Helge Deller
Change the TLB code to store the Block-TLBs at the beginning
of the TLB table. New 4k TLB entries which are added later
shall not overwrite any of the BTLB entries.
Make sure that when the TLB is cleared by the OS via the ptlbe
instruction, the Block-TLBs will not be dropped.
From: Helge Deller
Reserve 16 out of the 256 TLB entries for Block-TLBs.
Signed-off-by: Helge Deller
---
target/hppa/cpu.h | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index fa13694dab..23852d89b2 100644
--- a/target/hppa/cpu.
From: Mikulas Patocka
The code in setup_rt_frame reads two words at haddr, but locks only one.
This patch fixes it to lock both.
Signed-off-by: Mikulas Patocka
Acked-by: Helge Deller
Cc: qemu-sta...@nongnu.org
Signed-off-by: Helge Deller
---
linux-user/hppa/signal.c | 5 +++--
1 file changed
From: Helge Deller
Wire up the hppa diag instruction to support Block-TLBs
when called with the 0x100 value.
The diag_btlb() helper function does all necessary steps
to emulate the PDC BTLB firmware function, which includes
providing BTLB info, adding a new BTLB, deleting a BTLB
and removing all
From: Helge Deller
Extract the immediate value given by the diagnose CPU instruction.
This is needed to distinguish the various diagnose calls.
Signed-off-by: Helge Deller
---
target/hppa/insns.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/hppa/insns.decode
From: Helge Deller
Report the new number of TLB entries (without BTLBs) to the
guest and drop reporting of BTLB entries which weren't used at all.
Clear all BTLB and TLB entries at machine reset.
Signed-off-by: Helge Deller
---
hw/hppa/machine.c | 10 +-
1 file changed, 5 insertions(+
From: Helge Deller
The following changes since commit 9ef497755afc252fb8e060c9ea6b0987abfd20b6:
Merge tag 'pull-vfio-20230911' of https://github.com/legoater/qemu into
staging (2023-09-11 09:13:08 -0400)
are available in the Git repository at:
https://github.com/hdeller/qemu-hppa.git tags
On 9/16/23 19:17, Richard Henderson wrote:
On 9/16/23 09:18, Helge Deller wrote:
On 9/16/23 15:52, Mikulas Patocka wrote:
The code in setup_rt_frame reads two words at haddr, but locks only one.
This patch fixes it to lock both.
Signed-off-by: Mikulas Patocka
---
linux-user/hppa/signal.c |
On 8.09.2023 16:21, David Hildenbrand wrote:
We want to support memory devices that have a dynamically managed memory
region container as device memory region. This device memory region maps
multiple RAM memory subregions (e.g., aliases to the same RAM memory
region), whereby these subregions can
On 9/16/23 00:52, Eric Blake wrote:
> On Fri, Sep 15, 2023 at 07:20:13PM +0300, Andrey Drobyshev wrote:
>> When rebasing an image from one backing file to another, we need to
>> compare data from old and new backings. If the diff between that data
>> happens to be unaligned to the target cluster s
On 8.09.2023 16:21, David Hildenbrand wrote:
We really only care about the RAM memory region not being mapped into
an address space yet as long as we're still setting up the
RamDiscardManager. Once mapped into an address space, memory notifiers
would get notified about such a region and any attem
On 9/16/23 09:18, Helge Deller wrote:
On 9/16/23 15:52, Mikulas Patocka wrote:
The code in setup_rt_frame reads two words at haddr, but locks only one.
This patch fixes it to lock both.
Signed-off-by: Mikulas Patocka
---
linux-user/hppa/signal.c | 5 ++---
1 file changed, 2 insertions(+
On 8.09.2023 16:21, David Hildenbrand wrote:
Let's add vhost_get_max_memslots().
Signed-off-by: David Hildenbrand
Reviewed-by: Maciej S. Szmigiero
Thanks,
Maciej
On 8.09.2023 16:21, David Hildenbrand wrote:
We'll need the stub soon from memory device context.
While at it, use "unsigned int" as return value and place the
declaration next to kvm_get_free_memslots().
Signed-off-by: David Hildenbrand
Reviewed-by: Maciej S. Szmigiero
Thanks,
Maciej
From: Jiajie Chen
If LSX is available, use LSX instructions to implement 128-bit load &
store when MO_128 is required, otherwise use two 64-bit loads & stores.
Signed-off-by: Jiajie Chen
Message-Id: <20230908022302.180442-1...@jia.je>
Reviewed-by: Richard Henderson
Signed-off-by: Richard Hende
v2: tcg/loongarch64 patch set without last minute tweaks.
r~
The following changes since commit 005ad32358f12fe9313a4a01918a55e60d4f39e5:
Merge tag 'pull-tpm-2023-09-12-3' of https://github.com/stefanberger/qemu-tpm
into staging (2023-09-13 13:41:57 -0400)
are available in the Git repository
On 9/16/23 18:49, Helge Deller wrote:
The reason for the crash is that the signal handling routine doesn't clear
the 'N' flag in the PSW. If the signal interrupts a thread when the 'N'
flag is set, the flag remains set at the beginning of the signal handler
and the first instruction of the signal
On 9/16/23 15:49, Mikulas Patocka wrote:
qemu-hppa may crash when delivering a signal. It can be demonstrated with
this program. Compile the program with "hppa-linux-gnu-gcc -O2 signal.c"
and run it with "qemu-hppa -one-insn-per-tb a.out". It reports that the
address of the flag is 0xb4 and it cr
On 8.09.2023 16:21, David Hildenbrand wrote:
Let's track how many memslots are required by plugged memory devices and
how many are currently actually getting used by plugged memory
devices.
"required - used" is the number of reserved memslots. For now, the number
of used and required memslots is
On Sat, 16 Sep 2023, Helge Deller wrote:
> On 9/16/23 15:52, Mikulas Patocka wrote:
> > The code in setup_rt_frame reads two words at haddr, but locks only one.
> > This patch fixes it to lock both.
> >
> > Signed-off-by: Mikulas Patocka
> >
> > ---
> > linux-user/hppa/signal.c |5 ++---
On 8.09.2023 16:21, David Hildenbrand wrote:
We want to place non-qmp stubs in there, so let's rename it. While at
it, put it into the MAINTAINERS file under "Memory devices".
Signed-off-by: David Hildenbrand
Reviewed-by: Maciej S. Szmigiero
Thanks,
Maciej
On 8.09.2023 16:21, David Hildenbrand wrote:
We want to support memory devices that have a memory region container as
device memory region that maps multiple RAM memory regions. Let's start
by supporting memory devices that statically map multiple RAM memory
regions and, thereby, consume multiple
On 9/16/23 15:52, Mikulas Patocka wrote:
The code in setup_rt_frame reads two words at haddr, but locks only one.
This patch fixes it to lock both.
Signed-off-by: Mikulas Patocka
---
linux-user/hppa/signal.c |5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
Index: qemu/linux-us
On 8.09.2023 16:21, David Hildenbrand wrote:
Let's return the number of free slots instead of only checking if there
is a free slot. Required to support memory devices that consume multiple
memslots.
This is a preparation for memory devices that consume multiple memslots.
Signed-off-by: David H
On 8.09.2023 16:21, David Hildenbrand wrote:
Let's return the number of free slots instead of only checking if there
is a free slot. While at it, check all address spaces, which will also
consider SMM under x86 correctly.
This is a preparation for memory devices that consume multiple memslots.
qemu-hppa may crash when delivering a signal. It can be demonstrated with
this program. Compile the program with "hppa-linux-gnu-gcc -O2 signal.c"
and run it with "qemu-hppa -one-insn-per-tb a.out". It reports that the
address of the flag is 0xb4 and it crashes when attempting to touch it.
#inc
The code in setup_rt_frame reads two words at haddr, but locks only one.
This patch fixes it to lock both.
Signed-off-by: Mikulas Patocka
---
linux-user/hppa/signal.c |5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
Index: qemu/linux-user/hppa/signal.c
On 9/16/23 00:55, gaosong wrote:
Hi, Richard
Could you review this patch? it's the lastet patch no review.
Thanks.
Song Gao
在 2023/9/14 上午10:26, Song Gao 写道:
This patch includes:
- XVSHUF.{B/H/W/D};
- XVPERM.W;
- XVSHUF4i.{B/H/W/D};
- XVPERMI.{W/D/Q};
- XVEXTRINS.{B/H/W/D}.
Signed-off-by:
On 2023/09/16 19:32, Huang Rui wrote:
On Fri, Sep 15, 2023 at 11:20:46PM +0800, Akihiko Odaki wrote:
On 2023/09/15 20:11, Huang Rui wrote:
Patch "virtio-gpu: CONTEXT_INIT feature" has added the context_init
feature flags.
We would like to enable the feature with virglrenderer, so add to create
On Sat, Sep 16, 2023 at 12:58:31AM +0800, Akihiko Odaki wrote:
> On 2023/09/15 20:11, Huang Rui wrote:
> > Patch "virtio-gpu: CONTEXT_INIT feature" has added the context_init
> > feature flags.
> > We would like to enable the feature with virglrenderer, so add to create
> > virgl renderer context w
On Fri, Sep 15, 2023 at 11:20:46PM +0800, Akihiko Odaki wrote:
> On 2023/09/15 20:11, Huang Rui wrote:
> > Patch "virtio-gpu: CONTEXT_INIT feature" has added the context_init
> > feature flags.
> > We would like to enable the feature with virglrenderer, so add to create
> > virgl renderer context w
Hi Peter,
Thank you for your comments.
I used the PL050 component as a starting point, but I did not clean things
up well after I saw it working. I will clean it up before sending the new
patch version.
On Fri, Sep 15, 2023 at 4:23 PM Peter Maydell
wrote:
> On Tue, 5 Sept 2023 at 21:14, Strahi
Am 14.09.23 um 09:56 schrieb Philippe Mathieu-Daudé:
>
> On 9/9/23 11:48, Mark Cave-Ayland wrote:
>> MacOS (un)helpfully leaves the FIFO engine running even when all the
>> samples have
>> been written to the hardware, and expects the FIFO status flags and
>> IRQ to be
>> updated continuously.
>>
>
Simplify GDBRegisterState by replacing num_regs and xml members with
one member that points to GDBFeature.
Signed-off-by: Akihiko Odaki
---
gdbstub/gdbstub.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
index 61783ffa48.
This demonstrates how to write a plugin in C++.
Signed-off-by: Akihiko Odaki
---
docs/devel/tcg-plugins.rst | 8
configure | 15 ---
contrib/plugins/Makefile | 5 +
contrib/plugins/cc.cc | 17 +
tests/tcg/Makefile.target | 3 ++
Now we know all instances of GDBFeature that is used in CPU so we can
traverse them to find XML. This removes the need for a CPU-specific
lookup function for dynamic XMLs.
Signed-off-by: Akihiko Odaki
---
include/exec/gdbstub.h | 2 +
gdbstub/gdbstub.c | 85 +++-
This demonstrates how a register can be read from a plugin.
Signed-off-by: Akihiko Odaki
---
docs/devel/tcg-plugins.rst | 10 +++-
contrib/plugins/execlog.c | 120 +++--
2 files changed, 97 insertions(+), 33 deletions(-)
diff --git a/docs/devel/tcg-plugins.rst
It is based on GDB protocol to ensure interface stability.
The timing of the vcpu init hook is also changed so that the hook will
get called after GDB features are initialized.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1706
Signed-off-by: Akihiko Odaki
---
include/qemu/qemu-plugin
gdb_find_feature() and gdb_find_feature_register() find registers.
gdb_read_register() actually reads registers.
Signed-off-by: Akihiko Odaki
---
include/exec/gdbstub.h | 5 +
gdbstub/gdbstub.c | 31 ++-
2 files changed, 35 insertions(+), 1 deletion(-)
diff
This function is useful to determine the number of registers exposed to
GDB from the XML name.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
---
include/exec/gdbstub.h | 2 ++
gdbstub/gdbstub.c | 13 +
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