From: Daniel Henrique Barboza
The RISC-V KVM driver uses a CPUCFG() macro that calculates the offset
of a certain field in the struct RISCVCPUConfig. We're going to use this
macro in target/riscv/cpu.c as well in the next patches. Make it public.
Rename it to CPU_CFG_OFFSET() for more clarity wh
From: Ard Biesheuvel
Use the accelerated SubBytes/ShiftRows/AddRoundKey AES helper to
implement the first half of the key schedule derivation. This does not
actually involve shifting rows, so clone the same value into all four
columns of the AES vector to counter that operation.
Cc: Richard Hend
On 07/07/2023 09:29, Philippe Mathieu-Daudé wrote:
On 2/7/23 17:48, Mark Cave-Ayland wrote:
This determines whether the Apple Sound Chip (ASC) is set to enhanced mode
(default) or to original mode. The real Q800 hardware used an EASC chip however
a lot of older software only works with the olde
On 07/07/2023 09:25, Philippe Mathieu-Daudé wrote:
On 2/7/23 17:48, Mark Cave-Ayland wrote:
It is needed because it defines the BIOSConfig area.
Co-developed-by: Laurent Vivier
Signed-off-by: Mark Cave-Ayland
---
MAINTAINERS | 2 +
hw/m68k/Kconfig | 1 +
hw/m68k/q80
From: Daniel Henrique Barboza
During realize() time we're activating a lot of extensions based on some
criteria, e.g.:
if (cpu->cfg.ext_zk) {
cpu->cfg.ext_zkn = true;
cpu->cfg.ext_zkr = true;
cpu->cfg.ext_zkt = true;
}
This practice resulted in at least one case
Am 28.08.23 um 21:55 schrieb Emmanouil Pitsidianakis:
To perform audio capture we duplicate the TX logic of the previous
commit with the following difference: we receive data from the QEMU
audio backend and write it in the virt queue IO buffers the guest sends
to QEMU. When they are full (i.e. th
From: Andrew Melnychenko
It allows using file descriptors of eBPF provided
outside of QEMU.
QEMU may be run without capabilities for eBPF and run
RSS program provided by management tool(g.e. libvirt).
Signed-off-by: Andrew Melnychenko
Signed-off-by: Jason Wang
---
ebpf/ebpf_rss-stub.c | 6 ++
From: Tomasz Dzieciol
Rename e1000e_ba_state according and e1000e_write_hdr_to_rx_buffers for
consistency with IGB.
Signed-off-by: Tomasz Dzieciol
Reviewed-by: Akihiko Odaki
Tested-by: Akihiko Odaki
Signed-off-by: Jason Wang
---
hw/net/e1000e_core.c | 28 +++-
1 file
From: Andrew Melnychenko
eBPF RSS program and maps may now be passed during initialization.
Initially was implemented for libvirt to launch qemu without permissions,
and initialized eBPF program through the helper.
Signed-off-by: Andrew Melnychenko
Signed-off-by: Jason Wang
---
hw/net/virtio-
From: Andrew Melnychenko
Updated section name, so libbpf should init/gues proper
program type without specifications during open/load.
Also, added map_flags with explicitly declared BPF_F_MMAPABLE.
Added check for BPF_F_MMAPABLE flag to meson script and
requirements to libbpf version.
Signed-off
From: Andrew Melnychenko
Changed eBPF map updates through mmaped array.
Mmaped arrays provide direct access to map data.
It should omit using bpf_map_update_elem() call,
which may require capabilities that are not present.
Signed-off-by: Andrew Melnychenko
Signed-off-by: Jason Wang
---
ebpf/e
From: Andrew Melnychenko
Passing additional parameters (USOv4 and USOv6 offloads) when
setting TAP offloads
Signed-off-by: Yuri Benditovich
Signed-off-by: Andrew Melnychenko
Signed-off-by: Jason Wang
---
hw/net/e1000e_core.c | 2 +-
hw/net/igb_core.c| 2 +-
hw/net/virtio-net.c | 4 ++
From: Yong-Xuan Wang
In this patch, we create the APLIC and IMSIC FDT helper functions and
remove M mode AIA devices when using KVM acceleration.
Signed-off-by: Yong-Xuan Wang
Reviewed-by: Jim Shu
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Message-ID: <20230727102439.2255
From: Tomasz Dzieciol
Refactoring is done in preparation for support of multiple advanced
descriptors RX modes, especially packet-split modes.
Signed-off-by: Tomasz Dzieciol
Reviewed-by: Akihiko Odaki
Tested-by: Akihiko Odaki
Signed-off-by: Jason Wang
---
hw/net/e1000e_core.c | 18 ++--
From: Tomasz Dzieciol
Signed-off-by: Tomasz Dzieciol
Reviewed-by: Akihiko Odaki
Tested-by: Akihiko Odaki
Signed-off-by: Jason Wang
---
hw/net/igb_core.c | 4 +++-
hw/net/igb_regs.h | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
inde
From: Andrew Melnychenko
Now, the binary objects may be retrieved by id.
It would require for future qmp commands that may require specific
eBPF blob.
Added command "request-ebpf". This command returns
eBPF program encoded base64. The program taken from the
skeleton and essentially is an ELF obj
From: Tomasz Dzieciol
Packet-split descriptors are used by Linux VF driver for MTU values from 2048
Signed-off-by: Tomasz Dzieciol
Reviewed-by: Akihiko Odaki
Tested-by: Akihiko Odaki
Signed-off-by: Jason Wang
---
hw/net/igb_core.c | 348 +---
From: Ilya Maximets
AF_XDP is a network socket family that allows communication directly
with the network device driver in the kernel, bypassing most or all
of the kernel networking stack. In the essence, the technology is
pretty similar to netmap. But, unlike netmap, AF_XDP is Linux-native
and
From: Andrew Melnychenko
New features are subject to check with vhost-user and vdpa.
Signed-off-by: Yuri Benditovich
Signed-off-by: Andrew Melnychenko
Signed-off-by: Jason Wang
---
hw/net/vhost_net.c | 3 +++
net/vhost-vdpa.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/hw/net/v
From: Tomasz Dzieciol
Refactoring is done in preparation for support of multiple advanced
descriptors RX modes, especially packet-split modes.
Signed-off-by: Tomasz Dzieciol
Reviewed-by: Akihiko Odaki
Tested-by: Akihiko Odaki
Signed-off-by: Jason Wang
---
hw/net/igb_core.c | 170 +
From: Yuri Benditovich
USO features of virtio-net device depend on kernel ability
to support them, for backward compatibility by default the
features are disabled on 8.0 and earlier.
Signed-off-by: Yuri Benditovich
Signed-off-by: Andrew Melnychecnko
Signed-off-by: Jason Wang
---
hw/core/mach
From: Tomasz Dzieciol
TCP ACK detection is no longer present in igb.
Signed-off-by: Tomasz Dzieciol
Reviewed-by: Akihiko Odaki
Tested-by: Akihiko Odaki
Signed-off-by: Jason Wang
---
hw/net/igb_core.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/hw/net/igb_core.c b/hw/net/igb_core
From: Tomasz Dzieciol
Rename E1000E_RingInfo_st and E1000E_RingInfo according to qemu typdefs guide.
Signed-off-by: Tomasz Dzieciol
Reviewed-by: Akihiko Odaki
Tested-by: Akihiko Odaki
Signed-off-by: Jason Wang
---
hw/net/e1000e_core.c | 34 +-
hw/net/igb_core
From: Yuri Benditovich
Tap indicates support for USO features according to
capabilities of current kernel module.
Signed-off-by: Yuri Benditovich
Signed-off-by: Andrew Melnychecnko
Signed-off-by: Jason Wang
---
include/net/net.h | 3 +++
net/net.c | 9 +
net/tap-bsd.c |
The following changes since commit 03a3a62fbd0aa5227e978eef3c67d3978aec9e5f:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
(2023-09-07 10:29:06 -0400)
are available in the git repository at:
https://github.com/jasowang/qemu.git tags/net-pull-request
for you to fe
On Mon, Sep 4, 2023 at 7:23 PM Andrew Melnichenko wrote:
>
> Hi Jason,
> According to our previous conversation, I've added checks to the meson script.
> Please confirm that everything is correct
I've queued this series.
Thanks
Stefan Hajnoczi writes:
> On Tue, Sep 05, 2023 at 10:34:11AM +0100, Alex Bennée wrote:
>>
>> Albert Esteve writes:
>>
>> > This looks great! Thanks for this proposal.
>> >
>> > On Fri, Sep 1, 2023 at 1:00 PM Alex Bennée wrote:
>> >
>> > Currently QEMU has to know some details about the Vir
From: Yong-Xuan Wang
Select KVM AIA when the host kernel has in-kernel AIA chip support.
Since KVM AIA only has one APLIC instance, we map the QEMU APLIC
devices to KVM APLIC.
Signed-off-by: Yong-Xuan Wang
Reviewed-by: Jim Shu
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Me
08.09.2023 07:24, Nicholas Piggin wrote:
On Fri Sep 8, 2023 at 8:15 AM AEST, Cédric Le Goater wrote:
..
The decrementer fixes are good candidates but there are quite a few
patches and you might encounter conflicts.
Decrementer I was nervous about since there were quite a lot of
interacting is
08.09.2023 09:03, Alistair Francis wrote:
Akihiko Odaki (1):
target/riscv: Allocate itrigger timers only once
Ard Biesheuvel (2):
target/riscv: Use existing lookup tables for MixColumns
target/riscv: Use accelerated helper for AES64KS1I
Conor Dooley (1):
hw/riscv: v
On 6/23/2023 5:48 AM, Joao Martins wrote:
Only block the case when the underlying vIOMMU model does not report any
address space limits, in addition to DMA translation being off or no
vIOMMU present. The limits are needed such that can define the IOVA limits
that arm the device dirty tracker.
On 6/23/2023 5:48 AM, Joao Martins wrote:
Implement IOMMU MR get_attr() method and use the dma_translation
property to report the IOMMU_ATTR_DMA_TRANSLATION attribute.
Additionally add the necessary get_iommu_attr into the PCIIOMMUOps to
support pci_device_iommu_get_attr().
The callback in the
From: LIU Zhiwei
Commit bef6f008b98(accel/tcg: Return bool from page_check_range) converts
integer return value to bool type. However, it wrongly converted the use
of the API in riscv fault-only-first, where page_check_range < = 0, should
be converted to !page_check_range.
Signed-off-by: LIU Zhi
Hi Joao,
On 6/23/2023 5:48 AM, Joao Martins wrote:
Currently, device dirty page tracking with vIOMMU is not supported,
and a blocker is added and the migration is prevented.
When vIOMMU is used, IOVA ranges are DMA mapped/unmapped on the fly as
requesting by the vIOMMU. These IOVA ranges can po
From: Daniel Henrique Barboza
Add smoke tests to ensure that we'll not break the 'max' CPU type when
adding new frozen/ratified RISC-V extensions.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Messag
From: Yong-Xuan Wang
We check the in-kernel irqchip support when using KVM acceleration.
Signed-off-by: Yong-Xuan Wang
Reviewed-by: Jim Shu
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Message-ID: <20230727102439.22554-3-yongxuan.w...@sifive.com>
Signed-off-by: Alistair Fra
From: Daniel Henrique Barboza
We'll add a new CPU type that will enable a considerable amount of
extensions. To make it easier for us we'll do a few cleanups in our
existing riscv_cpu_extensions[] array.
Start by splitting all CPU non-boolean options from it. Create a new
riscv_cpu_options[] arr
From: Daniel Henrique Barboza
Add DEFINE_PROP_END_OF_LIST() and eliminate the ARRAY_SIZE() usage when
iterating in the riscv_cpu_options[] array, making it similar to what
we already do when working with riscv_cpu_extensions[].
We also have a more sophisticated motivation behind this change. In
From: Max Chou
Adds sm4_ck constant for use in sm4 cryptography across different targets.
Signed-off-by: Max Chou
Reviewed-by: Frank Chang
Signed-off-by: Max Chou
Message-ID: <20230711165917.2629866-15-max.c...@sifive.com>
Signed-off-by: Alistair Francis
---
include/crypto/sm4.h | 1 +
cry
From: Lawrence Hunter
This commit adds support for the Zvksh vector-crypto extension, which
consists of the following instructions:
* vsm3me.vv
* vsm3c.vi
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.
From: Daniel Henrique Barboza
Enabling RVG will enable a set of extensions that we're not checking if
the user was okay enabling or not. And in this case we want to error
out, instead of ignoring, otherwise we will be inconsistent enabling RVG
without all its extensions.
After this patch, disabl
From: Daniel Henrique Barboza
After the introduction of riscv_cpu_options[] all properties in
riscv_cpu_extensions[] are booleans. This check is now obsolete.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Message-ID: <20230901194627.1214811-3-d
From: Daniel Henrique Barboza
If we want to make better decisions when auto-enabling extensions during
realize() we need a way to tell if an user set an extension manually.
The RISC-V KVM driver has its own solution via a KVMCPUConfig struct
that has an 'user_set' flag that is set during the Prop
From: Conor Dooley
On a dtb dumped from the virt machine, dt-validate complains:
soc: pmu: {'riscv,event-to-mhpmcounters': [[1, 1, 524281], [2, 2, 524284],
[65561, 65561, 524280], [65563, 65563, 524280], [65569, 65569, 524280]],
'compatible': ['riscv,pmu']} should not be valid under {'type': 'o
From: Leon Schuermann
When the rule-lock bypass (RLB) bit is set in the mseccfg CSR, the PMP
configuration lock bits must not apply. While this behavior is
implemented for the pmpcfgX CSRs, this bit is not respected for
changes to the pmpaddrX CSRs. This patch ensures that pmpaddrX CSR
writes wor
From: Daniel Henrique Barboza
Add a new cpu_cfg_ext_is_user_set() helper to check if an extension was
set by the user in the command line. Use it inside
cpu_cfg_ext_auto_update() to verify if the user set a certain extension
and, if that's the case, do not change its value.
This will make us hon
From: Daniel Henrique Barboza
zmmul was promoted from experimental to ratified in commit 6d00ffad4e95.
Add a riscv,isa string for it.
Fixes: 6d00ffad4e95 ("target/riscv: move zmmul out of the experimental
properties")
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Reviewed-by:
From: Jason Chien
When writing the upper mtime, we should keep the original lower mtime
whose value is given by cpu_riscv_read_rtc() instead of
cpu_riscv_read_rtc_raw(). The same logic applies to writes to lower mtime.
Signed-off-by: Jason Chien
Reviewed-by: Alistair Francis
Message-ID: <20230
08.09.2023 09:03, Alistair Francis wrote:
From: Thomas Huth
@@ -209,11 +210,11 @@ static void htif_handle_tohost_write(HTIFState *s,
uint64_t val_written)
} else {
uint64_t syscall[8];
cpu_physical_memory_read(payload, syscall, sizeof(syscall
From: Vineet Gupta
zicond is now codegen supported in both llvm and gcc.
This change allows seamless enabling/testing of zicond in downstream
projects. e.g. currently riscv-gnu-toolchain parses elf attributes
to create a cmdline for qemu but fails short of enabling it because of
the "x-" prefix.
From: Daniel Henrique Barboza
We'll have future usage for a function where, given an offset of the
struct RISCVCPUConfig, the flag is updated to a certain val.
Change all existing callers to use edata->ext_enable_offset instead of
'edata'.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Al
From: Daniel Henrique Barboza
Let's change the other instances in realize() where we're enabling an
extension based on a certain criteria (e.g. it's a dependency of another
extension).
We're leaving icsr and ifencei being enabled during RVG for later -
we'll want to error out in that case. Every
From: Daniel Henrique Barboza
Before adding support to detect if an extension was user set we need to
handle how we're enabling extensions in riscv_init_max_cpu_extensions().
object_property_set_bool() calls the set() callback for the property,
and we're going to use this callback to set the 'mul
From: Daniel Henrique Barboza
A build with --enable-debug and without KVM will fail as follows:
/usr/bin/ld: libqemu-riscv64-softmmu.fa.p/hw_riscv_virt.c.o: in function
`virt_machine_init':
./qemu/build/../hw/riscv/virt.c:1465: undefined reference to
`kvm_riscv_aia_create'
This happens becaus
From: Kiran Ostrolenk
Refactor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into
function `opivv_trans` (similar to `opivi_trans`). `opivv_trans` will be
used in proceeding vector-crypto commits.
Signed-off-by: Kiran Ostrolenk
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
From: Yong-Xuan Wang
KVM AIA can't emulate APLIC only. When "aia=aplic" parameter is passed,
APLIC devices is emulated by QEMU. For "aia=aplic-imsic", remove the
mmio operations of APLIC when using KVM AIA and send wired interrupt
signal via KVM_IRQ_LINE API.
After KVM AIA enabled, MSI messages a
From: Daniel Henrique Barboza
Our goal is to make riscv_cpu_extensions[] hold only ratified,
non-vendor extensions.
Create a new riscv_cpu_vendor_exts[] array for them, changing
riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties()
accordingly.
Signed-off-by: Daniel Henrique Barboz
From: Max Chou
Allows sharing of sm4_subword between different targets.
Signed-off-by: Max Chou
Reviewed-by: Frank Chang
Reviewed-by: Richard Henderson
Signed-off-by: Max Chou
Message-ID: <20230711165917.2629866-14-max.c...@sifive.com>
Signed-off-by: Alistair Francis
---
include/crypto/sm4
From: Daniel Henrique Barboza
Inside riscv_cpu_validate_v() we're always throwing a log message if the
user didn't set a vector version via 'vext_spec'.
We're going to include one case with the 'max' CPU where env->vext_ver
will be set in the cpu_init(). But that alone will not stop the "vector
From: Yong-Xuan Wang
We create a vAIA chip by using the KVM_DEV_TYPE_RISCV_AIA and then set up
the chip with the KVM_DEV_RISCV_AIA_GRP_* APIs.
We also extend KVM accelerator to specify the KVM AIA mode. The "riscv-aia"
parameter is passed along with --accel in QEMU command-line.
1) "riscv-aia=emu
From: Tommy Wu
According to the new spec, when vsiselect has a reserved value, attempts
from M-mode or HS-mode to access vsireg, or from VS-mode to access
sireg, should preferably raise an illegal instruction exception.
Signed-off-by: Tommy Wu
Reviewed-by: Frank Chang
Message-ID: <202308160616
From: Robbin Ehn
This patch adds the new extensions in
linux 6.5 to the hwprobe syscall.
And fixes RVC check to OR with correct value.
The previous variable contains 0 therefore it
did work.
Signed-off-by: Robbin Ehn
Acked-by: Richard Henderson
Acked-by: Alistair Francis
Message-ID:
Signed-
From: Daniel Henrique Barboza
The cpu->cfg.epmp extension is still experimental, but it already has a
'smepmp' riscv,isa string. Add it.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
Message-Id: <20230720132424.371132-3-dbarb...@ventanamicro.com>
From: Daniel Henrique Barboza
Use a helper in riscv_cpu_add_kvm_properties() to eliminate some of its
code repetition.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Message-ID: <20230901194627.1214811-9-dbarb...@ventanamicro.com>
Signed-off-by:
From: Dickon Hood
Zvbb (implemented in later commit) has a widening instruction, which
requires an extra check on the enabled extensions. Refactor
GEN_OPIVX_WIDEN_TRANS() to take a check function to avoid reimplementing
it.
Signed-off-by: Dickon Hood
Reviewed-by: Richard Henderson
Reviewed-by
From: Kiran Ostrolenk
Take some functions/macros out of `vector_helper` and put them in a new
module called `vector_internals`. This ensures they can be used by both
vector and vector-crypto helpers (latter implemented in proceeding
commits).
Signed-off-by: Kiran Ostrolenk
Reviewed-by: Weiwei L
From: Daniel Henrique Barboza
Future patches will split the existing Property arrays even further, and
the existing code in riscv_cpu_add_user_properties() will start to scale
bad with it because it's dealing with KVM constraints mixed in with TCG
constraints. We're going to pay a high price to s
From: Nikita Shubin
As per ISA:
"For CSRRWI, if rd=x0, then the instruction shall not read the CSR and
shall not cause any of the side effects that might occur on a CSR read."
trans_csrrwi() and trans_csrrw() call do_csrw() if rd=x0, do_csrw() calls
riscv_csrrw_do64(), via helper_csrw() passing
From: Daniel Henrique Barboza
The 'any' CPU type was introduced in commit dc5bd18fa5725 ("RISC-V CPU
Core Definition"), being around since the beginning. It's not an easy
CPU to use: it's undocumented and its name doesn't tell users much about
what the CPU is supposed to bring. 'git log' doesn't
From: Daniel Henrique Barboza
Create a new riscv_cpu_experimental_exts[] to store the non-ratified
extensions properties. Once they are ratified we'll move them back to
riscv_cpu_extensions[].
riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties() are
changed to keep adding non-ratif
From: Nazar Kazakov
This commit adds support for the Zvkg vector-crypto extension, which
consists of the following instructions:
* vgmul.vv
* vghsh.vv
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.
Co-
From: Kiran Ostrolenk
This commit adds support for the Zvknh vector-crypto extension, which
consists of the following instructions:
* vsha2ms.vv
* vsha2c[hl].vv
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helpe
From: Daniel Henrique Barboza
Commit 6df0b37e2ab breaks a --enable-debug build in a non-KVM
environment with the following error:
/usr/bin/ld: libqemu-riscv64-softmmu.fa.p/hw_intc_riscv_aplic.c.o: in function
`riscv_kvm_aplic_request':
./qemu/build/../hw/intc/riscv_aplic.c:486: undefined refere
From: Rob Bradford
These are WARL fields - zero out the bits for unavailable counters and
special case the TM bit in mcountinhibit which is hardwired to zero.
This patch achieves this by modifying the value written so that any use
of the field will see the correctly masked bits.
Tested by modify
From: Dickon Hood
This commit adds support for the Zvbb vector-crypto extension, which
consists of the following instructions:
* vrol.[vv,vx]
* vror.[vv,vx,vi]
* vbrev8.v
* vrev8.v
* vandn.[vv,vx]
* vbrev.v
* vclz.v
* vctz.v
* vcpop.v
* vwsll.[vv,vx,vi]
Translation functions are defined in
`tar
From: Daniel Henrique Barboza
In the same emulated RISC-V host, the 'host' KVM CPU takes 4 times
longer to boot than the 'rv64' KVM CPU.
The reason is an unintended behavior of riscv_cpu_satp_mode_finalize()
when satp_mode.supported = 0, i.e. when cpu_init() does not set
satp_mode_max_supported(
From: Lawrence Hunter
This commit adds support for the Zvbc vector-crypto extension, which
consists of the following instructions:
* vclmulh.[vx,vv]
* vclmul.[vx,vv]
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_
From: Ard Biesheuvel
The AES MixColumns and InvMixColumns operations are relatively
expensive 4x4 matrix multiplications in GF(2^8), which is why C
implementations usually rely on precomputed lookup tables rather than
performing the calculations on demand.
Given that we already carry those table
From: Jason Chien
The variables whose values are given by cpu_riscv_read_rtc() should be named
"rtc". The variables whose value are given by cpu_riscv_read_rtc_raw()
should be named "rtc_r".
Signed-off-by: Jason Chien
Reviewed-by: Alistair Francis
Message-ID: <20230728082502.26439-2-jason.ch..
From: Jason Chien
RVA23 Profiles states:
The RVA23 profiles are intended to be used for 64-bit application
processors that will run rich OS stacks from standard binary OS
distributions and with a substantial number of third-party binary user
applications that will be supported over a considerable
From: Weiwei Li
The Svadu specification updated the name of the *envcfg bit from
HADE to ADUE.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230816141916.66898-1-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
target/risc
From: LIU Zhiwei
Commit a47842d ("riscv: Add support for the Zfa extension") implemented the zfa
extension.
However, it has some typos for fleq.d and fltq.d. Both of them misused the
fltq.s
helper function.
Fixes: a47842d ("riscv: Add support for the Zfa extension")
Signed-off-by: LIU Zhiwei
The following changes since commit 03a3a62fbd0aa5227e978eef3c67d3978aec9e5f:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
(2023-09-07 10:29:06 -0400)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230908
From: Nazar Kazakov
Remove the redundant "vl == 0" check which is already included within the
vstart >= vl check, when vl == 0.
Signed-off-by: Nazar Kazakov
Reviewed-by: Weiwei Li
Signed-off-by: Max Chou
Acked-by: Alistair Francis
Message-ID: <20230711165917.2629866-4-max.c...@sifive.com>
From: Kiran Ostrolenk
Move some macros out of `vector_helper` and into `vector_internals`.
This ensures they can be used by both vector and vector-crypto helpers
(latter implemented in proceeding commits).
Signed-off-by: Kiran Ostrolenk
Reviewed-by: Weiwei Li
Signed-off-by: Max Chou
Message-I
From: Nazar Kazakov
Move the checks out of `do_opiv{v,x,i}_gvec{,_shift}` functions
and into the corresponding macros. This enables the functions to be
reused in proceeding commits without check duplication.
Signed-off-by: Nazar Kazakov
Reviewed-by: Richard Henderson
Reviewed-by: Weiwei Li
Si
From: Daniel Henrique Barboza
The 'host' CPU is available in a CONFIG_KVM build and it's currently
available for all accels, but is a KVM only CPU. This means that in a
RISC-V KVM capable host we can do things like this:
$ ./build/qemu-system-riscv64 -M virt,accel=tcg -cpu host --nographic
qemu-
From: Thomas Huth
The character that should be printed is stored in the 64 bit "payload"
variable. The code currently tries to print it by taking the address
of the variable and passing this pointer to qemu_chr_fe_write(). However,
this only works on little endian hosts where the least significan
From: Thomas Huth
Values that have been read via cpu_physical_memory_read() from the
guest's memory have to be swapped in case the host endianess differs
from the guest.
Fixes: a6e13e31d5 ("riscv_htif: Support console output via proxy syscall")
Signed-off-by: Thomas Huth
Reviewed-by: Alistair F
On Fri Sep 8, 2023 at 8:15 AM AEST, Cédric Le Goater wrote:
> On 9/7/23 21:10, Michael Tokarev wrote:
> > 06.09.2023 17:36, Cédric Le Goater wrote:
> > ...
> >> ppc queue :
> >>
> >> * debug facility improvements
> >> * timebase and decrementer fixes
> >> * record-replay fixes
> >> * TCG fixes
> >>
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
---
include/qemu/timer.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/include/qemu/timer.h b/include/qemu/timer.h
index 9a91cb1248..105767c195 100644
--- a/include/qemu/timer.h
+++ b/include/qemu/timer.h
@@ -979,6 +979,25 @@
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
---
include/qemu/timer.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/include/qemu/timer.h b/include/qemu/timer.h
index 9a91cb1248..ce0b66d122 100644
--- a/include/qemu/timer.h
+++ b/include/qemu/timer.h
@@ -979,6 +979,25 @@
在 2023/9/8 上午1:34, Richard Henderson 写道:
On 9/7/23 01:31, Song Gao wrote:
+static bool gen__ptr_vl(DisasContext *ctx, arg_ *a, uint32_t
oprsz,
+ gen_helper_gvec_4_ptr *fn)
+{
+ tcg_gen_gvec_4_ptr(vec_full_offset(a->vd),
+ vec_full_offs
在 2023/9/8 上午1:19, Richard Henderson 写道:
On 9/7/23 01:31, Song Gao wrote:
Using gvec_*_vl functions hides oprsz. We can use gvec_v* for oprsz 16.
and gvec_v* for oprsz 32.
Signed-off-by: Song Gao
---
target/loongarch/insn_trans/trans_vec.c.inc | 68 +
1 file changed, 44 i
LSX support on host cpu is detected via hwcap.
Lower the following ops to LSX:
- dup_vec
- dupi_vec
- dupm_vec
- ld_vec
- st_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 2 +
tcg/loongarch64/tcg-target-con-str.h | 1 +
tcg/loonga
Lower the following ops:
- ssadd_vec
- usadd_vec
- sssub_vec
- ussub_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 32
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 33 insertions(+), 1 deletion
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 11 ++-
tcg/loongarch64/tcg-target.h | 2 +-
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/tcg/loongarch64/tcg-targ
Pass vece to tcg_target_const_match() to allow correct interpretation of
const args of vector ops.
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/aarch64/tcg-target.c.inc | 2 +-
tcg/arm/tcg-target.c.inc | 2 +-
tcg/i386/tcg-target.c.inc| 2 +-
tcg/loongar
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 21 +
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
Lower the following ops:
- shli_vec
- shrv_vec
- sarv_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 21 +
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/tcg/loon
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