On 8/26/23 09:02, Bastian Koppelmann wrote:
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson
r~
On 8/26/23 09:02, Bastian Koppelmann wrote:
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 8/26/23 09:02, Bastian Koppelmann wrote:
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 8
tests/tcg/tricore/asm/macros.h | 9 +
tests/tcg/tricore/asm/test_insert.S | 5 +
3 files changed, 18 insertions(+), 4 deletions(-)
diff --git
On 8/26/23 09:02, Bastian Koppelmann wrote:
we would crash if width was 0 for these insns, as tcg_gen_deposit() is
undefined for that case. For TriCore, width = 0 is a mov from the src reg
to the dst reg, so we special case this here.
Signed-off-by: Bastian Koppelmann
---
target/tricore/transl
On 8/26/23 09:02, Bastian Koppelmann wrote:
+uint32_t helper_hptof(CPUTriCoreState *env, uint32_t arg)
+{
+float16 f_arg = make_float16(arg);
+uint32_t result = 0;
+int32_t flags = 0;
+
+if (float16_is_any_nan(f_arg)) {
+if (float16_is_signaling_nan(f_arg, &env->fp_status)
On 8/26/23 09:02, Bastian Koppelmann wrote:
+uint32_t helper_ftohp(CPUTriCoreState *env, uint32_t arg)
+{
+float32 f_arg = make_float32(arg);
+uint32_t result = 0;
+int32_t flags = 0;
+
+if (float32_is_infinity(f_arg)) {
+if (float32_is_neg(f_arg)) {
+return H
On 8/26/23 09:02, Bastian Koppelmann wrote:
+uint32_t helper_ftou(CPUTriCoreState *env, uint32_t arg)
+{
+float32 f_arg = make_float32(arg);
+uint32_t result;
+int32_t flags = 0;
+
+if (float32_is_any_nan(f_arg)) {
+result = 0;
+flags |= float_flag_invalid;
+}
On 8/26/23 09:02, Bastian Koppelmann wrote:
when we reconstructed PSW using psw_read(), we were trying to clear the
cached USB bits out of env->PSW. The mask was wrong and we would clear
PSW.RM as well.
when we write the PSW using psw_write() we update the rounding modes in
env->fp_status for so
On 8/26/23 09:02, Bastian Koppelmann wrote:
+static uint32_t crc_div(uint32_t crc_in, uint32_t data, uint32_t gen,
+uint32_t n, uint32_t m)
+{
+uint32_t i;
+
+data = data << n;
+data = deposit32(data, m, 32 - m, 0);
This is data = extract32(data, 0, m), howev
On 8/26/23 09:02, Bastian Koppelmann wrote:
we don't want to exclude ISA v1.6.2 insns from our tests.
Signed-off-by: Bastian Koppelmann
---
tests/tcg/tricore/Makefile.softmmu-target | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Richard Henderson
r~
Suggested-by: Alex Bennée
Signed-off-by: Richard Henderson
---
softmmu/physmem.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
index 3df73542e1..7597dc1c39 100644
--- a/softmmu/physmem.c
+++ b/softmmu/physmem.c
@@ -2413,9 +24
Signed-off-by: Richard Henderson
---
include/exec/cpu-common.h | 1 -
accel/tcg/cpu-exec-common.c | 30 --
2 files changed, 31 deletions(-)
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 87dc9a752c..41788c0bdd 100644
--- a/include/exec/cpu
This seems like something that simply hasn't been updated for MTTCG,
since the last functional change appears to be:
commit 79e2b9aeccedbfde762b05da662132c7fda292be
Author: Paolo Bonzini
Date: Wed Jan 21 12:09:14 2015 +0100
exec: RCUify AddressSpaceDispatch
and the MTTCG work starts to ap
After system startup, run the update to memory_dispatch
and the tlb_flush on the cpu. This eliminates a race,
wherein a running cpu sees the memory_dispatch change
but has not yet seen the tlb_flush.
Since the update now happens on the cpu, we need not use
qatomic_rcu_read to protect the read of
On Wed, Aug 23, 2023 at 12:17 PM Fiona Ebner wrote:
>
> Am 23.08.23 um 10:47 schrieb Fiona Ebner:
> > Am 17.02.23 um 22:22 schrieb Mike Maslenkin:
> >> I can not tell anything about dma-reentracy issues, but yes, i would
> >> start to look at check_cmd() function call sequence.
> >> The most inter
reported in https://gitlab.com/qemu-project/qemu/-/issues/1667
Signed-off-by: Bastian Koppelmann
---
target/tricore/helper.h | 1 +
target/tricore/op_helper.c| 66 +++
target/tricore/translate.c| 6 +++
target/tricore/tricor
Signed-off-by: Bastian Koppelmann
---
target/tricore/fpu_helper.c | 25 +++
target/tricore/helper.h | 1 +
target/tricore/translate.c| 3 +++
tests/tcg/tricore/Makefile.softmmu-target | 1 +
tests/tcg/tricore/asm/test_ftou.S
when we reconstructed PSW using psw_read(), we were trying to clear the
cached USB bits out of env->PSW. The mask was wrong and we would clear
PSW.RM as well.
when we write the PSW using psw_write() we update the rounding modes in
env->fp_status for softfloat. The order of bits used by TriCore is
we don't want to exclude ISA v1.6.2 insns from our tests.
Signed-off-by: Bastian Koppelmann
---
tests/tcg/tricore/Makefile.softmmu-target | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/tcg/tricore/Makefile.softmmu-target
b/tests/tcg/tricore/Makefile.softmmu-target
ind
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1667
Signed-off-by: Bastian Koppelmann
---
target/tricore/fpu_helper.c | 39 +++
target/tricore/helper.h | 1 +
target/tricore/translate.c| 7
target/tricore/tricore-
Hi,
this series implements the insns reported in [1], as well as ftou. Also I fixed
two bugs in the insert insn which I came across during testing.
Cheers,
Bastian
[1] https://gitlab.com/qemu-project/qemu/-/issues/1667
Bastian Koppelmann (10):
tests/tcg/tricore: Bump cpu to tc37x
target/tr
reported in https://gitlab.com/qemu-project/qemu/-/issues/1667
Signed-off-by: Bastian Koppelmann
---
target/tricore/fpu_helper.c | 41 +++
target/tricore/helper.c | 1 +
target/tricore/helper.h | 1 +
target/tricore/translat
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index a68660b326..89ed48c951 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
we would crash if width was 0 for these insns, as tcg_gen_deposit() is
undefined for that case. For TriCore, width = 0 is a mov from the src reg
to the dst reg, so we special case this here.
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 10 --
tests/tcg/tric
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 89ed48c951..a7865db75c 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 8
tests/tcg/tricore/asm/macros.h | 9 +
tests/tcg/tricore/asm/test_insert.S | 5 +
3 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/tra
On Fri, Jun 24, 2022 at 4:40 PM Mauro Matteo Cascella
wrote:
>
> rocker_tlv_parse_nested could return early because of no group ids in
> the group_tlvs. In such case tlvs is NULL; tlvs[i + 1] in the next
> for-loop will deref the NULL pointer.
Someone somehow reserved a new CVE for this bug, publ
Hi!
Hopefully this address still works. If not, let's just commit Peter's comment.
Back in 2016, this commit introduced xlinx-dp.c:
commit 58ac482a66de09a7590f705e53fc6a3fb8a055e8
Author: Frederic Konrad
Date: Tue Jun 14 15:59:15 2016 +0100
introduce xlnx-dp
This is the implementat
Hi, Andrei. I'm preparing a patchset for a pull request.
For this patch, would you mind if I?
1. Generate a single patch from the optimization partition.
2. In the patch above, include my comment and my "Reviewed-by".
3. Add it to the queue with other patchsets.
Then you can improve on top at you
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