From: Helge Deller
Make the conversion between privilege level and QEMU MMU index
consitent, and afterwards switch to MMU indices 11-15.
v2:
- no functional changes
- just typo fixes in commit messages
- branch rebased on v8.1.0 release
Signed-off-by: Helge Deller
Helge Deller (5):
target/h
From: Helge Deller
The MMU indices 9-15 will use shorter assembler instructions
when run on a x86-64 host. So, switch over to those to get
smaller code and maybe minimally faster emulation.
Signed-off-by: Helge Deller
---
target/hppa/cpu.h | 16
1 file changed, 8 insertions(+)
From: Helge Deller
Convert hppa_get_physical_address() to use the privilege helper macro.
Signed-off-by: Helge Deller
---
target/hppa/mem_helper.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index 6f04c101dd..
From: Helge Deller
Avoid using hardcoded values when calling the tlb_flush*() functions.
Instead define the correct mask (HPPA_MMU_FLUSH_MASK) and use it.
Skip flushing the MMU for physical addresses.
Signed-off-by: Helge Deller
---
target/hppa/cpu.h| 5 +
target/hppa/helper.c
From: Helge Deller
The hppa CPU has 4 privilege levels (0-3).
Mention the missing PL1 and PL2 levels, although the Linux kernel
uses only 0 (KERNEL) and 3 (USER). Not sure about HP-UX.
Signed-off-by: Helge Deller
---
target/hppa/cpu.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/targ
Hello,
At 2023-08-23 23:34:11, "David Hildenbrand" wrote:
>For migration purposes, users might want to reuse the default RAM
>backend id, but specify a different memory backend.
>
>For example, to reuse "pc.ram" on q35, one has to set
>-machine q35,memory-backend=pc.ram
>Only then, can a memo
From: Helge Deller
Add two macros which convert privilege level to/from MMU index:
- PRIV_TO_MMU_IDX(priv)
returns the MMU index for the given privilege level
- MMU_IDX_TO_PRIV(mmu_idx)
returns the corresponding privilege level for this MMU index
The introduction of those macros make t
On 8/10/23 10:14, Alistair Francis wrote:
On Tue, Aug 8, 2023 at 2:18 PM Vineet Gupta wrote:
zicond is now codegen supported in both llvm and gcc.
This change allows seamless enabling/testing of zicond in downstream
projects. e.g. currently riscv-gnu-toolchain parses elf attributes
to creat
On 24/8/23 19:51, Michael Tokarev wrote:
do_ppoll() in linux-user/syscall.c uses alloca() to
allocate an array of struct pullfds on the stack.
The only upper boundary for number of entries for this
array is so that whole thing fits in INT_MAX. But this
is definitely too much for a stack allocatio
On 24/8/23 18:48, Peter Maydell wrote:
In xhci_get_port_bandwidth(), we use a variable-length array to
construct the buffer to send back to the guest. Avoid the VLA
by using dma_memory_set() to directly request the memory system
to fill the guest memory with a string of '80's.
The codebase has v
On 2023/08/25 8:40, Gurchetan Singh wrote:
From: Gurchetan Singh
Prior versions:
Changes since v11:
- Incorporated review feedback
How to build both rutabaga and gfxstream guest/host libs:
https://crosvm.dev/book/appendix/rutabaga_gfx.html
Branch containing this patch series (now on QEMU Gi
On 24/8/23 18:10, Thomas Huth wrote:
On 24/08/2023 16.51, Stefan Hajnoczi wrote:
On Thu, 24 Aug 2023 at 02:53, Thomas Huth wrote:
On 23/08/2023 18.34, Stefan Hajnoczi wrote:
On Wed, Aug 23, 2023 at 01:45:32PM +0200, Thomas Huth wrote:
The following changes since commit
b0dd9a7d6dd15a6898e9c
On 24/8/23 18:45, Peter Maydell wrote:
We use a variable-length array in inet_get_free_port_multiple().
This is only test code called at the start of a test, so switch to a
heap allocation instead.
The codebase has very few VLAs, and if we can get rid of them all we
can make the compiler error o
When the zoned request fail, it needs to update only the wp of
the target zones for not disrupting the in-flight writes on
these other zones. The wp is updated successfully after the
request completes.
Fixed the callers with right offset and nr_zones.
Signed-off-by: Sam Li
---
block/file-posix.
Damien Le Moal 于2023年8月25日周五 11:32写道：
>
> On 8/25/23 12:05, Sam Li wrote:
> > Damien Le Moal 于2023年8月25日周五 07:49写道：
> >>
> >> On 8/25/23 02:39, Sam Li wrote:
> >>> When the zoned requests that may change wp fail, it needs to
> >>> update only wps of the zones within the range of the requests
> >>
On 8/25/23 12:05, Sam Li wrote:
> Damien Le Moal 于2023年8月25日周五 07:49写道：
>>
>> On 8/25/23 02:39, Sam Li wrote:
>>> When the zoned requests that may change wp fail, it needs to
>>> update only wps of the zones within the range of the requests
>>> for not disrupting the other in-flight requests. The
From: Zhao Liu
This tests the commit 7298fd7de5551 ("hw/smbios: Fix thread count in
type4").
Add this test to cover 2 cases:
1. Test thread count2 field with multiple sockets and multiple dies to
confirm this field could correctly calculate threads per sockets.
2. Confirm that field calculat
From: Zhao Liu
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly
From: Zhao Liu
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be added to test the thread count2 field
of smbios type4 table.
Signed-off-by: Zhao Liu
---
tests/data/acpi/q35/APIC.thread-count2 | 0
tests/data/acpi/q35/DSDT.t
From: Zhao Liu
This tests the commit d79a284a44bb7 ("hw/smbios: Fix smbios_smp_sockets
calculation").
Test the count of type4 tables for multiple sockets case.
Suggested-by: Igor Mammedov
Signed-off-by: Zhao Liu
---
tests/qtest/bios-tables-test.c | 33 -
1 fil
From: Zhao Liu
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly
From: Zhao Liu
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly
From: Zhao Liu
Change the core count2 from 275 to 260.
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
APIC:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2
From: Zhao Liu
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be added to test the thread count field
of smbios type4 table.
Signed-off-by: Zhao Liu
---
tests/data/acpi/q35/APIC.thread-count | 0
tests/data/acpi/q35/DSDT.th
From: Zhao Liu
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be added to test the type 4 core count
field.
Signed-off-by: Zhao Liu
---
tests/data/acpi/q35/APIC.core-count | 0
tests/data/acpi/q35/DSDT.core-count
From: Zhao Liu
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly
From: Zhao Liu
This tests the commit 196ea60a734c3 ("hw/smbios: Fix core count in
type4").
Test the core count field of type4 table for multiple sockets/dies case.
Suggested-by: Igor Mammedov
Signed-off-by: Zhao Liu
---
tests/qtest/bios-tables-test.c | 19 +++
1 file changed,
From: Zhao Liu
Currently, this case just covers the topology with only core and smt
levels, and doesn't consider more topology layers between socket and
core.
To cover the fixed case in the commit 196ea60a734c3 ("hw/smbios: Fix
core count in type4"), add the "die" level in "-smp" as the more
gen
From: Zhao Liu
Hi all,
This patchset is the follow up tests of previous topology fixes in
smbios [1].
In this patchset, add these test cases:
1. Add the case to test 2 newly added topology helpers (patch 1):
* machine_topo_get_cores_per_socket()
* machine_topo_get_threads_per_socket()
2
From: Zhao Liu
Use the different ways to calculate cores/threads per socket, so that
the new CPU topology levels won't be missed in these 2 helpes:
* machine_topo_get_cores_per_socket()
* machine_topo_get_threads_per_socket()
Test the commit a1d027be95bc3 ("machine: Add helpers to get cores/
th
From: Zhao Liu
This tests the commit 7298fd7de5551 ("hw/smbios: Fix thread count in
type4").
Add this test to cover 2 cases:
1. Test thread count field with multiple sockets and multiple dies to
confirm this field could correctly calculate threads per sockets.
2. Confirm that field calculati
From: Zhao Liu
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be changed about the type 4 core count2
test case.
Signed-off-by: Zhao Liu
---
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
1 file changed, 2 insertions(+)
dif
From: Zhao Liu
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be added to test the type 4 count.
Signed-off-by: Zhao Liu
---
tests/data/acpi/q35/APIC.type4-count| 0
tests/data/acpi/q35/DSDT.type4-count| 0
tests/
Damien Le Moal 于2023年8月25日周五 07:49写道：
>
> On 8/25/23 02:39, Sam Li wrote:
> > When the zoned requests that may change wp fail, it needs to
> > update only wps of the zones within the range of the requests
> > for not disrupting the other in-flight requests. The wp is updated
> > successfully after
On Fri, Aug 25, 2023 at 10:33 AM wrote:
> From: alloc
>
> Convert free to g_free to match g_new and g_malloc functions.
>
> Signed-off-by: alloc
> ---
> softmmu/dirtylimit.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/softmmu/dirtylimit.c b/softmmu/dirty
From: alloc
Changes in v2:
- Split into two patches, one fixing memory leak issue and another
converting free to g_free.
- Fix typos
alloc (1):
softmmu/dirtylimit: Convert free to g_free
alloc.young (1):
softmmu: Fix dirtylimit memory leak
softmmu/dirtylimit.c | 26 -
From: alloc
Convert free to g_free to match g_new and g_malloc functions.
Signed-off-by: alloc
---
softmmu/dirtylimit.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/softmmu/dirtylimit.c b/softmmu/dirtylimit.c
index e3ff53b8fc..fa959d7743 100644
--- a/softmmu/d
From: "alloc.young"
Fix memory leak in hmp_info_vcpu_dirty_limit,use g_autoptr
to handle memory deallocation.
Signed-off-by: alloc.young
---
softmmu/dirtylimit.c | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/softmmu/dirtylimit.c b/softmmu/dirtylimit.c
ind
Thanks for your reply.
On Thu, Aug 24, 2023 at 5:33 PM Peter Maydell
wrote:
> On Thu, 24 Aug 2023 at 06:55, Markus Armbruster wrote:
> >
> > Liu Jaloo writes:
> >
> > > What's the difference between "__attribute__((constructor))" and
> > > "__attribute__((__constructor__))" in qemu source?
>
From: Helge Deller
Avoid using hardcoded values when calling the tlb_flush*() functions.
Instead define the correct mask (HPPA_MMU_FLUSH_MASK) and use it.
Skip flushing the MMU for physical addresses.
Signed-off-by: Helge Deller
---
target/hppa/cpu.h| 5 +
target/hppa/helper.c
From: Helge Deller
Make the conversion between priviledge level and QEMU MMU index
consitent, and afterwards switch to MMU indices 11-15.
Signed-off-by: Helge Deller
Helge Deller (5):
target/hppa: Add missing PL1 and PL2 priviledge levels
target/hppa: Add priviledge to MMU index conversion
From: Helge Deller
The MMU indices 9-15 will use shorter assembler instructions
when run on a x86-64 host. So, switch over to those to get
smaller code and maybe minimally faster emulation.
Signed-off-by: Helge Deller
---
target/hppa/cpu.h | 16
1 file changed, 8 insertions(+)
From: Helge Deller
The hppa CPU has 4 priviledge levels (0-3).
Mention the missing PL1 and PL2 levels, although the Linux kernel
uses only 0 (KERNEL) and 3 (USER). Not sure about HP-UX.
Signed-off-by: Helge Deller
---
target/hppa/cpu.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tar
From: Helge Deller
Convert hppa_get_physical_address() to use the privilege helper macro.
Signed-off-by: Helge Deller
---
target/hppa/mem_helper.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index 6f04c101dd..
From: Helge Deller
Add two macros which convert priviledge level to/from MMU index:
- PRIV_TO_MMU_IDX(priv)
returns the MMU index for the given priviledge level
- MMU_IDX_TO_PRIV(mmu_idx)
returns the corresponding priviledge level for this MMU index
The introduction of those macros mak
On Wed, Aug 23, 2023 at 4:07 AM Alyssa Ross wrote:
> Gurchetan Singh writes:
>
> > - Official "release commits" issued for rutabaga_gfx_ffi,
> > gfxstream, aemu-base. For example, see crrev.com/c/4778941
> >
> > - The release commits can make packaging easier, though once
> > again all know
On Wed, Aug 23, 2023 at 8:03 AM Mark Cave-Ayland <
mark.cave-ayl...@ilande.co.uk> wrote:
> On 17/08/2023 03:23, Gurchetan Singh wrote:
>
> > From: Gurchetan Singh
> >
> > This adds initial support for gfxstream and cross-domain. Both
> > features rely on virtio-gpu blob resources and context typ
On 8/25/23 02:39, Sam Li wrote:
> When the zoned requests that may change wp fail, it needs to
> update only wps of the zones within the range of the requests
> for not disrupting the other in-flight requests. The wp is updated
> successfully after the request completes.
>
> Fixed the callers with
On Wed, Aug 23, 2023 at 7:32 AM Mark Cave-Ayland <
mark.cave-ayl...@ilande.co.uk> wrote:
> On 17/08/2023 03:23, Gurchetan Singh wrote:
>
> > From: Gurchetan Singh
> >
> > This modifies the common virtio-gpu.h file have the fields and
> > defintions needed by gfxstream/rutabaga, by VirtioGpuRutaba
This adds initial support for gfxstream and cross-domain. Both
features rely on virtio-gpu blob resources and context types, which
are also implemented in this patch.
gfxstream has a long and illustrious history in Android graphics
paravirtualization. It has been powering graphics in the Android
This modifies the common virtio-gpu.h file have the fields and
defintions needed by gfxstream/rutabaga, by VirtioGpuRutabaga.
Signed-off-by: Gurchetan Singh
Tested-by: Alyssa Ross
Tested-by: Emmanouil Pitsidianakis
Reviewed-by: Emmanouil Pitsidianakis
---
v1: void *rutabaga --> struct rutabaga
From: Antonio Caggiano
The feature can be enabled when a backend wants it.
Signed-off-by: Antonio Caggiano
Reviewed-by: Marc-André Lureau
Signed-off-by: Gurchetan Singh
Tested-by: Alyssa Ross
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Akihiko Odaki
---
hw/display/virtio-gpu-base.c
This change enables rutabaga to receive virtio-gpu-3d hypercalls
when it is active.
Signed-off-by: Gurchetan Singh
Tested-by: Alyssa Ross
Tested-by: Emmanouil Pitsidianakis
Reviewed-by: Emmanouil Pitsidianakis
---
v3: Whitespace fix (Akihiko)
v9: reorder virtio_gpu_have_udmabuf() after checkin
- Add meson detection of rutabaga_gfx
- Build virtio-gpu-rutabaga.c + associated vga/pci files when
present
Signed-off-by: Gurchetan Singh
Tested-by: Alyssa Ross
Tested-by: Emmanouil Pitsidianakis
Reviewed-by: Emmanouil Pitsidianakis
---
v3: Fix alignment issues (Akihiko)
hw/display/meson.
From: "Dr. David Alan Gilbert"
Define a new capability type 'VIRTIO_PCI_CAP_SHARED_MEMORY_CFG' to allow
defining shared memory regions with sizes and offsets of 2^32 and more.
Multiple instances of the capability are allowed and distinguished
by a device-specific 'id'.
Signed-off-by: Dr. David A
From: Gurchetan Singh
Prior versions:
Changes since v11:
- Incorporated review feedback
How to build both rutabaga and gfxstream guest/host libs:
https://crosvm.dev/book/appendix/rutabaga_gfx.html
Branch containing this patch series (now on QEMU Gitlab):
https://gitlab.com/gurchetansingh/qem
This adds basic documentation for virtio-gpu.
Suggested-by: Akihiko Odaki
Signed-off-by: Gurchetan Singh
Tested-by: Alyssa Ross
Tested-by: Emmanouil Pitsidianakis
Reviewed-by: Emmanouil Pitsidianakis
---
v2: - Incorporated suggestions by Akihiko Odaki
- Listed the currently supported cap
From: Antonio Caggiano
This adds preparatory functions needed to:
- decode blob cmds
- tracking iovecs
Signed-off-by: Antonio Caggiano
Signed-off-by: Dmitry Osipenko
Signed-off-by: Gurchetan Singh
Tested-by: Alyssa Ross
Tested-by: Emmanouil Pitsidianakis
Reviewed-by: Emmanouil Pi
From: Gerd Hoffmann
Use VIRTIO_GPU_SHM_ID_HOST_VISIBLE as id for virtio-gpu.
Signed-off-by: Antonio Caggiano
Tested-by: Alyssa Ross
Acked-by: Michael S. Tsirkin
---
hw/display/virtio-gpu-pci.c| 14 ++
hw/display/virtio-gpu.c| 1 +
hw/display/virtio-vga.c| 33
We'll have future usage for a function where, given an offset of the
struct RISCVCPUConfig, the flag is updated to a certain val.
Change all existing callers to use edata->ext_enable_offset instead of
'edata'.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
target/risc
The 'any' CPU type was introduced in commit dc5bd18fa5725 ("RISC-V CPU
Core Definition"), being around since the beginning. It's not an easy
CPU to use: it's undocumented and its name doesn't tell users much about
what the CPU is supposed to bring. 'git log' doesn't help us either in
knowing what w
The RISC-V KVM driver uses a CPUCFG() macro that calculates the offset
of a certain field in the struct RISCVCPUConfig. We're going to use this
macro in target/riscv/cpu.c as well in the next patches. Make it public.
Rename it to CPU_CFG_OFFSET() for more clarity while we're at it.
Signed-off-by:
Add a new cpu_cfg_ext_is_user_set() helper to check if an extension was
set by the user in the command line. Use it inside
cpu_cfg_ext_auto_update() to verify if the user set a certain extension
and, if that's the case, do not change its value.
This will make us honor user choice instead of overwr
Let's change the other instances in realize() where we're enabling an
extension based on a certain criteria (e.g. it's a dependency of another
extension).
We're leaving icsr and ifencei being enabled during RVG for later -
we'll want to error out in that case. Every other extension enablement
duri
The code inside riscv_cpu_add_user_properties() became quite repetitive
after recent changes. Add a helper to hide the repetition away.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 27 +++
1 file changed, 11 insertions(+), 16 deletions(-)
diff --git a/
Before adding support to detect if an extension was user set we need to
handle how we're enabling extensions in riscv_init_max_cpu_extensions().
object_property_set_bool() calls the set() callback for the property,
and we're going to use this callback to set the 'multi_ext_user_opts'
hash.
This me
Add smoke tests to ensure that we'll not break the 'max' CPU type when
adding new ratified extensions to be enabled.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
tests/avocado/riscv_opensbi.py | 16
1 file changed, 16 insertions(+)
diff --git a/test
After the introduction of riscv_cpu_options[] all properties in
riscv_cpu_extensions[] are booleans. This check is now obsolete.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
dif
Our goal is to make riscv_cpu_extensions[] hold only ratified,
non-vendor extensions.
Create a new riscv_cpu_vendor_exts[] array for them, changing
riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties()
accordingly.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
The 'max' CPU type is used by tooling to determine what's the most
capable CPU a current QEMU version implements. Other archs such as ARM
implements this type. Let's add it to RISC-V.
What we consider "most capable CPU" in this context are related to
ratified, non-vendor extensions. This means tha
Create a new riscv_cpu_experimental_exts[] to store the non-ratified
extensions properties. Once they are ratified we'll move them back to
riscv_cpu_extensions[].
riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties() are
changed to keep adding non-ratified properties to users.
Signed
Enabling RVG will enable a set of extensions that we're not checking if
the user was okay enabling or not. And in this case we want to error
out, instead of ignoring, otherwise we will be inconsistent enabling RVG
without all its extensions.
After this patch, disabling ifencei or icsr while enabli
During realize() time we're activating a lot of extensions based on some
criteria, e.g.:
if (cpu->cfg.ext_zk) {
cpu->cfg.ext_zkn = true;
cpu->cfg.ext_zkr = true;
cpu->cfg.ext_zkt = true;
}
This practice resulted in at least one case where we ended up enabling
somet
Future patches will split the existing Property arrays even further, and
the existing code in riscv_cpu_add_user_properties() will start to scale
bad with it because it's dealing with KVM constraints mixed in with TCG
constraints. We're going to pay a high price to share a couple of common
lines of
Inside riscv_cpu_validate_v() we're always throwing a log message if the
user didn't set a vector version via 'vext_spec'.
We're going to include one case with the 'max' CPU where env->vext_ver
will be set in the cpu_init(). But that alone will not stop the "vector
version is not specified" messag
If we want to make better decisions when auto-enabling extensions during
realize() we need a way to tell if an user set an extension manually.
The RISC-V KVM driver has its own solution via a KVMCPUConfig struct
that has an 'user_set' flag that is set during the Property set()
callback. The set() c
We'll add a new CPU type that will enable a considerable amount of
extensions. To make it easier for us we'll do a few cleanups in our
existing riscv_cpu_extensions[] array.
Start by splitting all CPU non-boolean options from it. Create a new
riscv_cpu_options[] array for them. Add all these prope
Hi,
This is a resend of these two patch sets because they no longer apply
into Alistair's riscv-to-apply.next:
[PATCH v8 00/12] riscv: add 'max' CPU, deprecate 'any'
https://lore.kernel.org/qemu-riscv/20230815223741.433763-1-dbarb...@ventanamicro.com/
[PATCH v3 0/8] riscv: detecting user choice
Use a helper in riscv_cpu_add_kvm_properties() to eliminate some of its
code repetition.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4608fa
Add DEFINE_PROP_END_OF_LIST() and eliminate the ARRAY_SIZE() usage when
iterating in the riscv_cpu_options[] array, making it similar to what
we already do when working with riscv_cpu_extensions[].
We also have a more sophisticated motivation behind this change. In the
future we might need to expo
On 8/17/2023 2:23 PM, Peter Xu wrote:
> On Mon, Aug 14, 2023 at 11:54:26AM -0700, Steve Sistare wrote:
>> Migration of a guest in the suspended runstate is broken. The incoming
>> migration code automatically tries to wake the guest, which is wrong;
>> the guest should end migration in the same ru
On 8/17/2023 2:27 PM, Peter Xu wrote:
> On Mon, Aug 14, 2023 at 11:54:27AM -0700, Steve Sistare wrote:
>> +void vm_wakeup(void)
>> +{
>> +if (!vm_started) {
>> +vm_start();
>
> (irrelevant of the global var that I wanted to remove..)
>
> Calling vm_start() is wrong here, IMHO.
>
> I
On 8/17/2023 2:19 PM, Peter Xu wrote:
> On Wed, Aug 16, 2023 at 01:48:13PM -0400, Steven Sistare wrote:
>> On 8/14/2023 3:37 PM, Peter Xu wrote:
>>> On Mon, Aug 14, 2023 at 02:53:56PM -0400, Steven Sistare wrote:
> Can we just call vm_state_notify() earlier?
We cannot. The guest is n
On Mon, Aug 07, 2023 at 09:53:42AM +0100, Jonathan Cameron wrote:
> On Tue, 25 Jul 2023 18:39:56 +
> Fan Ni wrote:
>
> > From: Fan Ni
> >
> > Not all dpa range in the dc regions is valid to access until an extent
> > covering the range has been added. Add a bitmap for each region to
> > recor
Closing stderr earlier is good for daemonized qemu-nbd under ssh
earlier, but breaks the case where -v is being used to track what is
happening in the server, as in iotest 233.
When we know we are verbose, we do NOT want qemu_daemon to close
stderr. For management purposes, we still need to tempo
On Thu, Aug 24, 2023 at 05:47:06PM +0100, Peter Maydell wrote:
> From: Philippe Mathieu-Daudé
>
> Use autofree heap allocation instead of variable-length array on the
> stack.
>
> The codebase has very few VLAs, and if we can get rid of them all we
> can make the compiler error on new additions.
On 8/24/23 09:39, Alex Bennée wrote:
Use proper kdoc style comments for this API function.
Signed-off-by: Alex Bennée
---
include/exec/gdbstub.h | 10 ++
gdbstub/gdbstub.c | 6 --
2 files changed, 10 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson
r~
On 8/24/23 09:39, Alex Bennée wrote:
Try and make the self reported global hack a little less hackish by
providing a query function instead. As gdb_has_xml was always set if
we negotiated XML we can now use the presence of ->target_xml as the
test instead.
Signed-off-by: Alex Bennée
---
gdbstu
On 8/24/23 09:39, Alex Bennée wrote:
Try to bring up the code to more modern standards by:
- use dynamic GString built xml over a fixed buffer
- use autofree to save on explicit g_free() calls
- don't hand hack strstr to find the delimiter
Signed-off-by: Alex Bennée
---
v2
- avoid
Dangit, missed the PULL tag for v2.
The only change is fixing Anton's --author.
r~
On 8/24/23 11:28, Richard Henderson wrote:
The following changes since commit 50e7a40af372ee5931c99ef7390f5d3d6fbf6ec4:
Merge tag 'pull-target-arm-20230824' of
https://git.linaro.org/peopl
Emmanouil Pitsidianakis writes:
> This patch series adds an audio device implementing the recent virtio
> sound spec (1.2) and a corresponding PCI wrapper device.
>
> v7 can be found online at:
>
> https://github.com/epilys/qemu-virtio-snd/tree/virtio-snd-v7
>
> Main differences with v6 patch
Emmanouil Pitsidianakis writes:
> Receive guest requests in the control (CTRL) queue of the virtio sound
> device and reply with a NOT SUPPORTED error to all control commands.
>
> The receiving handler is virtio_snd_handle_ctrl(). It stores all control
> messages in the queue in the device's co
Introduce a model of Xilinx Versal's Configuration Frame Unit's Single
Frame Read port (CFU_SFR).
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
hw/misc/xlnx-versal-cfu.c | 87 +++
include/hw/misc/xlnx-versal-cfu.h | 15 ++
2 files chang
Connect the Configuration Frame Unit (CFU_APB, CFU_FDRO and CFU_SFR) to
the Versal machine.
Signed-off-by: Francisco Iglesias
Acked-by: Edgar E. Iglesias
Reviewed-by: Peter Maydell
---
hw/arm/xlnx-versal.c | 42
include/hw/arm/xlnx-versal.h | 16 +++
Introduce the Xilinx Configuration Frame Interface (CFI) for transmitting
CFI data packets between the Xilinx Configuration Frame Unit models
(CFU_APB, CFU_FDRO and CFU_SFR), the Xilinx CFRAME controller (CFRAME_REG)
and the Xilinx CFRAME broadcast controller (CFRAME_BCAST_REG) models (when
emulati
Introduce a model of Xilinx Versal's Configuration Frame controller
(CFRAME_REG).
Signed-off-by: Francisco Iglesias
---
MAINTAINERS | 2 +
hw/misc/meson.build | 1 +
hw/misc/xlnx-versal-cframe-reg.c | 685 +++
incl
Hi Peter,
On 2023-08-21 15:34, Peter Maydell wrote:
On Thu, 10 Aug 2023 at 20:16, Francisco Iglesias
wrote:
Introduce a model of Xilinx Versal's Configuration Frame controller
(CFRAME_REG).
Signed-off-by: Francisco Iglesias
---
MAINTAINERS | 2 +
hw/misc/me
Introduce a model of Xilinx Versal's Configuration Frame broadcast
controller (CFRAME_BCAST_REG).
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
hw/misc/xlnx-versal-cframe-reg.c | 161 +++
include/hw/misc/xlnx-versal-cframe-reg.h | 17 +++
2 files
Hi,
This series adds support for the Configuration Frame Unit (CFU) and the
Configuration Frame controllers (CFRAME) to the Xilinx Versal machine
([1], chapter 21) for emulaing bitstream loading and readback.
The series starts by introducing the Xilinx CFI interface that is
thereafter used by the
Introduce a model of the software programming interface (CFU_APB) of
Xilinx Versal's Configuration Frame Unit.
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
MAINTAINERS | 2 +
hw/misc/meson.build | 1 +
hw/misc/xlnx-versal-cfu.c
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