Re: [PATCH] linux-user/elfload: Set V in ELF_HWCAP for RISC-V

03.08.2023 16:14, Nathan Egge wrote: From: "Nathan Egge" Set V bit for hwcap if misa is set. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1793 Signed-off-by: Nathan Egge --- linux-user/elfload.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/linux-user/elf

[PULL 0/2] hw/nvme late fix

From: Klaus Jensen Hi, This is a fix for hw/nvme protection information discovered by Ankit late in the cycle. This is not a regression, but a long standing bug and not critical (obviously no users of this until now, no potential for crash or similar, just plain wrong). If this can make it for

[PULL 1/2] hw/nvme: fix CRC64 for guard tag

From: Ankit Kumar The nvme CRC64 generator expects the caller to pass inverted seed value. Pass inverted crc value for metadata buffer. Cc: qemu-sta...@nongnu.org Fixes: 44219b6029fc ("hw/nvme: 64-bit pi support") Signed-off-by: Ankit Kumar Signed-off-by: Klaus Jensen --- hw/nvme/dif.c | 4 ++

Re: [PATCH] target/loongarch: Split fcc register to fcc0-7 in gdbstub

add loongarch gdb maintainer. 在 2023/8/8 14:10, bibo mao 写道: > > I am not familiar with gdb, is there abi breakage? > I do not know how gdb client works with gdb server with different versions. > > Regards > Bibo Mao > > > 在 2023/8/8 13:42, Jiajie Chen 写道: >> Since GDB 13.1(GDB commit ea33521

Re: [PATCH for-8.2 v3 1/6] vfio/migration: Move from STOP_COPY to STOP in vfio_save_cleanup()

On 07/08/2023 18:53, Cédric Le Goater wrote: External email: Use caution opening links or attachments [ Adding Juan and Peter for their awareness ] On 8/2/23 10:14, Avihai Horon wrote: Changing the device state from STOP_COPY to STOP can take time as the device may need to free resources an

[PULL 2/2] docs: update hw/nvme documentation for protection information

From: Ankit Kumar Add missing entry for pif ("protection information format"). Protection information size can be 8 or 16 bytes, Update the pil entry as per the NVM command set specification. Signed-off-by: Ankit Kumar Signed-off-by: Klaus Jensen --- docs/system/devices/nvme.rst | 12

Re: [PATCH for-8.1 v10 10/14] util/selfmap: Rewrite using qemu/interval-tree.h

07.08.2023 19:37, Richard Henderson wrote: We will want to be able to search the set of mappings. For this patch, the two users iterate the tree in order. diff --git a/include/qemu/selfmap.h b/include/qemu/selfmap.h /** * read_self_maps: * * Read /proc/self/maps and return a list

Re: [PATCH] hw/nvme: fix oob memory read in fdp events log

+CC qemu-stable On Aug 3 20:44, Klaus Jensen wrote: > From: Klaus Jensen > > As reported by Trend Micro's Zero Day Initiative, an oob memory read > vulnerability exists in nvme_fdp_events(). The host-provided offset is > not verified. > > Fix this. > > This is only exploitable when Flexible D

Re: [PATCH] target/loongarch: Split fcc register to fcc0-7 in gdbstub

I am not familiar with gdb, is there abi breakage? I do not know how gdb client works with gdb server with different versions. Regards Bibo Mao 在 2023/8/8 13:42, Jiajie Chen 写道: > Since GDB 13.1(GDB commit ea3352172), GDB LoongArch changed to use > fcc0-7 instead of fcc register. This commit

Re: [PATCH 0/3] hw/nvme: bug fixes and doc update

On Aug 8 09:04, Michael Tokarev wrote: > 08.08.2023 00:27, Ankit Kumar wrote: > > This series fixes two bugs > > 1. CRC64 generation when metadata buffer is used. > > 2. Protection information disable check for Type 3 protection. > > > > This series also updates the documentaion for pi (protectio

Re: [PATCH 0/3] hw/nvme: bug fixes and doc update

08.08.2023 00:27, Ankit Kumar wrote: This series fixes two bugs 1. CRC64 generation when metadata buffer is used. 2. Protection information disable check for Type 3 protection. This series also updates the documentaion for pi (protection information), and adds missing pif (protection information

Re: [PATCH 3/3] docs: update hw/nvme documentation for protection information

On Aug 8 02:57, Ankit Kumar wrote: > Add missing entry for pif ("protection information format"). > Protection information size can be 8 or 16 bytes, Update the pil entry > as per the NVM command set specification. > > Signed-off-by: Ankit Kumar > --- > docs/system/devices/nvme.rst | 10 +++

Re: [PATCH 1/3] hw/nvme: fix CRC64 for guard tag

On Aug 8 02:57, Ankit Kumar wrote: > The nvme CRC64 generator expects the caller to pass inverted seed value. > Pass inverted crc value for metadata buffer. > > Signed-off-by: Ankit Kumar > --- > hw/nvme/dif.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/hw/nvme

Re: [PATCH 2/3] hw/nvme: fix disable pi checks for Type 3 protection

On Aug 8 02:57, Ankit Kumar wrote: > As per the NVM command set specification, the protection information > checks for Type 3 protection are disabled, only when both application > and reference tag have all bits set to 1. > > Signed-off-by: Ankit Kumar > --- > hw/nvme/dif.c | 5 +++-- > 1 file

[PATCH] target/loongarch: Split fcc register to fcc0-7 in gdbstub

Since GDB 13.1(GDB commit ea3352172), GDB LoongArch changed to use fcc0-7 instead of fcc register. This commit partially reverts commit 2f149c759 (`target/loongarch: Update gdb_set_fpu() and gdb_get_fpu()`) to match the behavior of GDB. Note that it is a breaking change for GDB 13.0 or earlier, bu

[PATCH v2 15/19] spapr: Fix machine reset deadlock from replay-record

When the machine is reset to load a new snapshot while being debugged with replay-record, it is done from another thread, so the CPU does not run the register setting operations. Set CPU registers directly in machine reset. Cc: Pavel Dovgalyuk Signed-off-by: Nicholas Piggin --- hw/ppc/spapr.c

[PATCH v2 05/19] host-utils: Add muldiv64_round_up

This will be used for converting time intervals in different base units to host units, for the purpose of scheduling timers to emulate target timers. Timers typically must not fire before their requested expiry time but may fire some time afterward, so rounding up is the right way to implement thes

[PATCH v2 10/19] target/ppc: Migrate DECR SPR

TCG does not maintain the DEC reigster in the SPR array, so it does get migrated. TCG also needs to re-start the decrementer timer on the destination machine. Load and store the decrementer into the SPR when migrating. This works for the level-triggered (book3s) decrementer, and should be compatib

[PATCH v2 17/19] tests/avocado: boot ppc64 pseries replay-record test to Linux VFS mount

This the ppc64 record-replay test is able to replay the full kernel boot so try enabling it. Acked-by: Pavel Dovgalyuk Signed-off-by: Nicholas Piggin --- tests/avocado/replay_kernel.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/tests/avocado/replay_kernel.py b/tests/a

[PATCH v2 11/19] hw/ppc: Reset timebase facilities on machine reset

Lower interrupts, delete timers, and set time facility registers back to initial state on machine reset. This is not so important for record-replay since timebase and decrementer are migrated, but it gives a cleaner reset state. Cc: Mark Cave-Ayland Cc: BALATON Zoltan Signed-off-by: Nicholas Pi

[PATCH v2 19/19] tests/avocado: ppc64 reverse debugging tests for pseries and powernv

These machines run reverse-debugging well enough to pass basic tests. Wire them up. Reviewed-by: Pavel Dovgalyuk Signed-off-by: Nicholas Piggin --- tests/avocado/reverse_debugging.py | 29 + 1 file changed, 29 insertions(+) diff --git a/tests/avocado/reverse_debuggi

[PATCH v2 16/19] spapr: Fix record-replay machine reset consuming too many events

spapr_machine_reset gets a random number to populate the device-tree rng seed with. When loading a snapshot for record-replay, the machine is reset again, and that tries to consume the random event record again, crashing due to inconsistent record Fix this by saving the seed to populate the device

[PATCH v2 14/19] target/ppc: Fix timebase reset with record-replay

Timebase save uses a random number for a legacy vmstate field, which makes rr snapshot loading unbalanced. The easiest way to deal with this is just to skip the rng if record-replay is active. Reviewed-by: Pavel Dovgalyuk Signed-off-by: Nicholas Piggin --- hw/ppc/ppc.c | 11 +-- 1 file

[PATCH v2 13/19] target/ppc: Fix CPU reservation migration for record-replay

ppc only migrates reserve_addr, so the destination machine can get a valid reservation with an incorrect reservation value of 0. Prior to commit 392d328abe753 ("target/ppc: Ensure stcx size matches larx"), this could permit a stcx. to incorrectly succeed. That commit inadvertently fixed that bug be

[PATCH v2 06/19] hw/ppc: Round up the decrementer interval when converting to ns

The rule of timers is typically that they should never expire before the timeout, but some time afterward. Rounding timer intervals up when doing conversion is the right thing to do. Under most circumstances it is impossible observe the decrementer interrupt before the dec register has triggered.

[PATCH v2 18/19] tests/avocado: reverse-debugging cope with re-executing breakpoints

The reverse-debugging test creates a trace, then replays it and: 1. Steps the first 10 instructions and records their addresses. 2. Steps backward and verifies their addresses match. 3. Runs to (near) the end of the trace. 4. Sets breakpoints on the first 10 instructions. 5. Continues backward and

[PATCH v2 12/19] hw/ppc: Read time only once to perform decrementer write

Reading the time more than once to perform an operation always increases complexity and fragility due to introduced deltas. Simplify the decrementer write by reading the clock once for the operation. Signed-off-by: Nicholas Piggin --- hw/ppc/ppc.c | 84 +--

[PATCH v2 02/19] ppc/vof: Fix missed fields in VOF cleanup

Failing to reset the of_instance_last makes ihandle allocation continue to increase, which causes record-replay replay fail to match the recorded trace. Not resetting claimed_base makes VOF eventually run out of memory after some resets. Cc: Alexey Kardashevskiy Fixes: fc8c745d501 ("spapr: Imple

[PATCH v2 09/19] hw/ppc: Always store the decrementer value

When writing a value to the decrementer that raises an exception, the irq is raised, but the value is not stored so the store doesn't appear to have changed the register when it is read again. Always store the write value to the register. Fixes: e81a982aa53 ("PPC: Clean up DECR implementation") S

[PATCH v2 for-8.2 00/19] ppc: record-replay enablement and fixes

The patches in this series has been seen a few times in various iterations. There are two main pieces, some assorted small fixes and tests for record-replay, plus a large set of decrementer fixes. I merged these into one series rather than send decrementer fixes alone first, because record-replay

[PATCH v2 07/19] hw/ppc: Avoid decrementer rounding errors

The decrementer register contains a relative time in timebase units. When writing to DECR this is converted and stored as an absolute value in nanosecond units, reading DECR converts back to relative timebase. The tb<->ns conversion of the relative part can cause rounding such that a value writen

[PATCH v2 08/19] target/ppc: Sign-extend large decrementer to 64-bits

When storing a large decrementer value with the most significant implemented bit set, it is to be treated as a negative and sign extended. This isn't hit for book3s DEC because of another bug, fixing it in the next patch exposes this one and can cause additional problems, so fix this first. It can

[PATCH v2 04/19] hw/ppc: Introduce functions for conversion between timebase and nanoseconds

These calculations are repeated several times, and they will become a little more complicated with subsequent changes. Signed-off-by: Nicholas Piggin --- hw/ppc/ppc.c | 28 ++-- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c in

[PATCH v2 03/19] hw/ppc/ppc.c: Tidy over-long lines

Signed-off-by: Nicholas Piggin --- hw/ppc/ppc.c | 19 --- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index 0e0a3d93c3..09b82f68a8 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -497,7 +497,8 @@ uint64_t cpu_ppc_load_tbl (CPUPPCState

[PATCH v2 01/19] ppc/vhyp: reset exception state when handling vhyp hcall

Convention is to reset the exception_index and error_code after handling an interrupt. The vhyp hcall handler fails to do this. This does not appear to have ill effects because cpu_handle_exception() clears exception_index later, but it is fragile and inconsistent. Reset the exception state after h

Re: [PATCH 4/7] spapr: Fix record-replay machine reset consuming too many events

On 08.08.2023 06:09, Nicholas Piggin wrote: On Sun Aug 6, 2023 at 9:46 PM AEST, Nicholas Piggin wrote: On Fri Aug 4, 2023 at 6:50 PM AEST, Pavel Dovgalyuk wrote: BTW, there is a function qemu_register_reset_nosnapshotload that can be used in similar cases. Can you just use it without changing t

Re: [PATCH 4/8] Introduce the CPU address space destruction function

Hi Igor Mammedov: The first four patches are written with reference to the patch in the public modification section of Arm's CPU Hotplug, and the Arm CPU HotPlug-related patches will be merged into the community in the near future, so the first four patches will be discarded and rebase based

[PATCH 22/24] tcg/i386: Clear dest first in tcg_out_setcond if possible

Using XOR first is both smaller and more efficient, though cannot be applied if it clobbers an input. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 17 - 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-targ

[PATCH 18/24] tcg/i386: Merge tcg_out_setcond{32,64}

Pass a rexw parameter instead of duplicating the functions. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 24 +++- 1 file changed, 7 insertions(+), 17 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index b9673b55bd..ec3c701

[PATCH 5/6] target/ppc: Implement watchpoint debug facility for v2.07S

ISA v2.07S introduced the watchpoint facility based on the DAWR0 and DAWRX0 SPRs. Implement this in TCG. Signed-off-by: Nicholas Piggin --- target/ppc/cpu.c | 59 target/ppc/cpu.h | 4 +++ target/ppc/cpu_init.c| 6 ++-- target/ppc/ex

[PATCH 02/24] tcg: Use tcg_gen_negsetcond_*

Signed-off-by: Richard Henderson --- tcg/tcg-op-gvec.c | 6 ++ tcg/tcg-op.c | 6 ++ 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index a062239804..e260a07c61 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -3692,8 +369

[PATCH 05/24] target/m68k: Use tcg_gen_negsetcond_*

Signed-off-by: Richard Henderson --- target/m68k/translate.c | 24 ++-- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index e07161d76f..37954d11a6 100644 --- a/target/m68k/translate.c +++ b/target/m68k/transla

[PATCH 04/24] target/arm: Use tcg_gen_negsetcond_*

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 22 +- target/arm/tcg/translate.c | 12 2 files changed, 13 insertions(+), 21 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 5fa1257d32..ac1

[PATCH 15/24] tcg/s390x: Implement negsetcond_*

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 4 +- tcg/s390x/tcg-target.c.inc | 78 +- 2 files changed, 54 insertions(+), 28 deletions(-) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 24e207c2d4..cd3d245be0 100644 ---

[PATCH for-8.2 00/24] tcg: Introduce negsetcond opcodes

Introduce two new setcond opcode variants which produce -1 instead of 1 when the condition. For most of our hosts, producing -1 is just as easy as 1, and avoid requiring a separate negate instruction. Use the new opcode in tcg/tcg-op-gvec.c for integral expansion of generic vector operations. I

[PATCH 03/24] target/alpha: Use tcg_gen_movcond_i64 in gen_fold_mzero

The setcond + neg + and sequence is a complex method of performing a conditional move. Signed-off-by: Richard Henderson --- target/alpha/translate.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 846f3d8091..08

[PATCH 20/24] tcg/i386: Add cf parameter to tcg_out_cmp

Add the parameter to avoid TEST and pass along to tgen_arithi. All current users pass false. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc i

[PATCH 21/24] tcg/i386: Use CMP+SBB in tcg_out_setcond

Use the carry bit to optimize some forms of setcond. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 50 +++ 1 file changed, 50 insertions(+) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 56549ff2a0..e06ac638b0 1006

[PATCH 19/24] tcg/i386: Merge tcg_out_movcond{32,64}

Pass a rexw parameter instead of duplicating the functions. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 28 +++- 1 file changed, 7 insertions(+), 21 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index ec3c7012d4..b88

[PATCH 10/24] tcg/ppc: Implement negsetcond_*

In the general case we simply negate. However with isel we may load -1 instead of 1 with no extra effort. Consolidate EQ0 and NE0 logic. Replace the NE0 zero-extension with inversion+negation of EQ0, which is never worse and may eliminate one insn. Provide a special case for -EQ0. Signed-off-b

[PATCH 24/24] tcg/i386: Implement negsetcond_*

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 4 ++-- tcg/i386/tcg-target.c.inc | 27 +++ 2 files changed, 21 insertions(+), 10 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 41df0e5ae1..1a9025d786 100644 --- a/tcg/i386/t

[PATCH 06/24] target/openrisc: Use tcg_gen_negsetcond_*

Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index a86360d4f5..7c6f80daf1 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translat

[PATCH 07/24] target/ppc: Use tcg_gen_negsetcond_*

Signed-off-by: Richard Henderson --- target/ppc/translate/fixedpoint-impl.c.inc | 6 -- target/ppc/translate/vmx-impl.c.inc| 8 +++- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.

[PATCH 08/24] target/sparc: Use tcg_gen_movcond_i64 in gen_edge

The setcond + neg + or sequence is a complex method of performing a conditional move. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 17 - 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index bd8

[PATCH 11/24] tcg/ppc: Use the Set Boolean Extension

The SETBC family of instructions requires exactly two insns for all comparisions, saving 0-3 insns per (neg)setcond. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 22 ++ 1 file changed, 22 insertions(+) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-ta

[PATCH 6/6] spapr: implement H_SET_MODE debug facilities

Wire up the H_SET_MODE debug resources to the CIABR and DAWR0 debug facilities in TCG. Signed-off-by: Nicholas Piggin --- hw/ppc/spapr_hcall.c | 57 1 file changed, 57 insertions(+) diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 9b1f2

[PATCH 2/6] target/ppc: Improve book3s branch trace interrupt for v2.07S

Improve the emulation accuracy of the single step and branch trace interrupts for v2.07S. Set SRR1[33]=1, and set SIAR to completed instruction address. Signed-off-by: Nicholas Piggin --- target/ppc/excp_helper.c | 16 +++- target/ppc/helper.h | 1 + target/ppc/translate.c |

[PATCH 23/24] tcg/i386: Use shift in tcg_out_setcond

For LT/GE vs zero, shift down the sign bit. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 15 +++ 1 file changed, 15 insertions(+) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index cca49fe63a..f68722b8a5 100644 --- a/tcg/i386/tcg-target.c.in

[PATCH 14/24] tcg/riscv: Implement negsetcond_*

Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.h | 4 ++-- tcg/riscv/tcg-target.c.inc | 45 ++ 2 files changed, 47 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index b2961fec8e..7e8ac48a7d 100644 --

[PATCH 12/24] tcg/aarch64: Implement negsetcond_*

Trivial, as aarch64 has an instruction for this: CSETM. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 4 ++-- tcg/aarch64/tcg-target.c.inc | 12 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h

[PATCH 16/24] tcg/sparc64: Implement negsetcond_*

Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.h | 4 ++-- tcg/sparc64/tcg-target.c.inc | 36 ++-- 2 files changed, 28 insertions(+), 12 deletions(-) diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h index 1faadc704b..4bbd825bd8 10

[PATCH 4/6] target/ppc: Implement breakpoint debug facility for v2.07S

ISA v2.07S introduced the breakpoint facility based on the CIABR SPR. Implement this in TCG. Signed-off-by: Nicholas Piggin --- target/ppc/cpu.c | 27 ++ target/ppc/cpu.h | 3 +++ target/ppc/cpu_init.c| 5 - target/ppc/excp_helper.c | 42

[PATCH 13/24] tcg/arm: Implement negsetcond_i32

Trivial, as we simply need to load a different constant in the conditional move. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 2 +- tcg/arm/tcg-target.c.inc | 9 + 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.

[PATCH 09/24] target/tricore: Replace gen_cond_w with tcg_gen_negsetcond_tl

Signed-off-by: Richard Henderson --- target/tricore/translate.c | 16 ++-- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 1947733870..6ae5ccbf72 100644 --- a/target/tricore/translate.c +++ b/target/tricore/t

[PATCH 17/24] tcg/i386: Merge tcg_out_brcond{32,64}

Pass a rexw parameter instead of duplicating the functions. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 110 +- 1 file changed, 49 insertions(+), 61 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 774

[PATCH 01/24] tcg: Introduce negsetcond opcodes

Introduce a new opcode for negative setcond. Signed-off-by: Richard Henderson --- docs/devel/tcg-ops.rst | 6 ++ include/tcg/tcg-op-common.h | 4 include/tcg/tcg-op.h | 2 ++ include/tcg/tcg-opc.h| 2 ++ include/tcg/tcg.h| 1 + tcg/aarch64/tcg-tar

[PATCH 3/6] target/ppc: Suppress single step interrupts on rfi-type instructions

BookS does not take single step interrupts on completion of rfi and similar (rfid, hrfid, rfscv). This is not a completely clean way to do it, but in general non-branch instructions that change NIP on completion are excluded. Signed-off-by: Nicholas Piggin --- target/ppc/translate.c | 23 +++

[PATCH 1/6] target/ppc: Remove single-step suppression inside 0x100-0xf00

Single-step interrputs are suppressed if the nip is between 0x100 and 0xf00. This has been the case for a long time and it's not clear what the intention is. Likely either an attempt to suppress trace interrupts for instructions that cause an interrupt on completion, or a workaround to prevent soft

[PATCH for-8.2 0/6] ppc: debug facility improvements

I started out looking at this to reduce divergence of TCG and KVM machines with 2nd DAWR. The divergence already exists with first DAWR, so I don't want to tie the KVM 2nd DAWR enablement to this, but it would be nice to ensure the caps and such for the 2nd DAWR will also work for TCG. I don't kno

Re: [PATCH 4/7] spapr: Fix record-replay machine reset consuming too many events

On Sun Aug 6, 2023 at 9:46 PM AEST, Nicholas Piggin wrote: > On Fri Aug 4, 2023 at 6:50 PM AEST, Pavel Dovgalyuk wrote: > > BTW, there is a function qemu_register_reset_nosnapshotload that can be > > used in similar cases. > > Can you just use it without changing the code of the reset handler? > >

[PATCH v2 2/7] tcg/ppc: Use PADDI in tcg_out_movi

PADDI can load 34-bit immediates and 34-bit pc-relative addresses. Reviewed-by: Jordan Niethe Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 51 1 file changed, 51 insertions(+) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target

[PATCH v2 7/7] tcg/ppc: Use prefixed instructions for tcg_out_goto_tb

When a direct branch is out of range, we can load the destination for the indirect branch using PLA (for 16GB worth of buffer) and PLD from the TranslationBlock for everything larger. This means the patch affects exactly one instruction: B (plus filler), PLA or PLD. Which means we can update and

[PATCH v2 5/7] tcg/ppc: Use prefixed instructions in tcg_out_dupi_vec

The prefixed instructions have a pc-relative form to use here. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 12 1 file changed, 12 insertions(+) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index b3b2e9874d..01ca5c9f39 100644 --- a/tcg/ppc/tcg

[PATCH v2 1/7] tcg/ppc: Untabify tcg-target.c.inc

Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 511e14b180..642d0fd128 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -221,7 +

[PATCH v2 3/7] tcg/ppc: Use prefixed instructions in tcg_out_mem_long

When the offset is out of range of the non-prefixed insn, but fits the 34-bit immediate of the prefixed insn, use that. Reviewed-by: Jordan Niethe Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 66 1 file changed, 66 insertions(+) diff

[PATCH v2 6/7] tcg/ppc: Disable USE_REG_TB for Power v3.1

With Power v3.1, we have pc-relative addressing and so do not require a register holding the current TB. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 01c

[PATCH for-8.2 v2 0/7] tcg/ppc: Support power10 prefixed instructions

Emit one 64-bit instruction for large constants and pc-relatives. With pc-relative addressing, we don't need REG_TB, which means we can re-enable direct branching for goto_tb. Changes for v2: * Merged Nick's adjustments for goto_tb. Only patch B/NOP, falling through to PLD for indirect bran

[PATCH v2 4/7] tcg/ppc: Use PLD in tcg_out_movi for constant pool

The prefixed instruction has a pc-relative form to use here. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 24 1 file changed, 24 insertions(+) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 61ae9d8ab7..b3b2e9874d 100644 --- a/t

[PATCH 1/2] linux-user: Split out do_mmap

New function that rejects unsupported map types and flags. In 4b840f96 we should not have accepted MAP_SHARED_VALIDATE without actually validating the rest of the flags. Fixes: 4b840f96 ("linux-user: Populate more bits in mmap_flags_tbl") Signed-off-by: Richard Henderson --- linux-user/syscall.c

[PATCH for-8.1 0/2] linux-user: Fix MAP_SHARED_VALIDATE, MAP_FIXED_NOREPLACE

Fixes LTP mmap17 (MAP_FIXED_NOREPLACE) and mmap20 (MAP_SHARED_VALIDATE), both of which were added to linux-user during the 8.1 cycle, and so would be nice to fix right away. Does not fix mmap18, which will fail depending on the guest memory map. The real kernel avoids placing new maps immediately

[PATCH 2/2] linux-user: Use ARRAY_SIZE with bitmask_transtbl

Rather than using a zero tuple to end the table, use a macro to apply ARRAY_SIZE and pass that on to the convert functions. This fixes two bugs in which the conversion functions required that both the target and host masks be non-zero in order to continue, rather than require both target and host

[RFC PATCH v2] target/i386: add support for VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE

Current QEMU can expose waitpkg to guests when it is available. However, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE is still not recognized and masked by QEMU. This can lead to an unexpected situation when a L1 hypervisor wants to expose waitpkg to a L2 guest. The L1 hypervisor can assume that VMX_S

Re: [PATCH v5 1/5] ebpf: Added eBPF map update through mmap.

On Thu, Aug 3, 2023 at 5:01 AM Andrew Melnychenko wrote: > > Changed eBPF map updates through mmaped array. > Mmaped arrays provide direct access to map data. > It should omit using bpf_map_update_elem() call, > which may require capabilities that are not present. > > Signed-off-by: Andrew Melnych

Re: [PATCH v3] net: add initial support for AF_XDP network backend

On Sat, Aug 5, 2023 at 2:20 AM Ilya Maximets wrote: > > AF_XDP is a network socket family that allows communication directly > with the network device driver in the kernel, bypassing most or all > of the kernel networking stack. In the essence, the technology is > pretty similar to netmap. But,

[PATCH QEMU v3 3/3] tests/migration: Introduce dirty-limit into guestperf

From: Hyman Huang(黄勇) Currently, guestperf does not cover the dirty-limit migration, support this feature. Note that dirty-limit requires 'dirty-ring-size' set. To enable dirty-limit, setting x-vcpu-dirty-limit-period as 500ms and x-vcpu-dirty-limit as 10MB/s: $ ./tests/migration/guestperf.py \

[PATCH QEMU v3 0/3] migration: enrich the dirty-limit test case

Ping This version is a copy of version 2 and is rebased on the master. No functional changes. The dirty-limit migration test involves many passes and takes about 1 minute on average, so put it in the slow mode of migration-test. Inspired by Peter. V2: - put the dirty-limit migration test in slow

[PATCH QEMU v3 2/3] tests/migration: Introduce dirty-ring-size option into guestperf

From: Hyman Huang(黄勇) Dirty ring size configuration is not supported by guestperf tool. Introduce dirty-ring-size (ranges in [1024, 65536]) option so developers can play with dirty-ring and dirty-limit feature easier. To set dirty ring size with 4096 during migration test: $ ./tests/migration/g

[PATCH QEMU v3 1/3] tests: Add migration dirty-limit capability test

From: Hyman Huang(黄勇) Add migration dirty-limit capability test if kernel support dirty ring. Migration dirty-limit capability introduce dirty limit capability, two parameters: x-vcpu-dirty-limit-period and vcpu-dirty-limit are introduced to implement the live migration with dirty limit. The te

Re: [PATCH v10 0/7] igb: packet-split descriptors support

On Mon, Aug 7, 2023 at 10:52 PM Tomasz Dzieciol/VIM Integration (NC) /SRPOL/Engineer/Samsung Electronics wrote: > > Hi, > > It's been a while since review was done and nothing happened with those > patches since then. > > As I understand from guide: > https://www.qemu.org/docs/master/devel/submi

Re: [PATCH v4 11/11] target/loongarch: Add loongarch32 cpu la132

On 2023/8/8 09:54, Jiajie Chen wrote: Add la132 as a loongarch32 cpu type and allow virt machine to be used with la132 instead of la464. Refactor common init logic out as loongarch_cpu_initfn_common. Signed-off-by: Jiajie Chen --- hw/loongarch/virt.c| 5 target/loongarch/cpu.c |

[PATCH v4 06/11] target/loongarch: Support LoongArch32 VPPN

VPPN of TLBEHI/TLBREHI is limited to 19 bits in LA32. Signed-off-by: Jiajie Chen --- target/loongarch/cpu-csr.h| 6 -- target/loongarch/tlb_helper.c | 23 ++- 2 files changed, 22 insertions(+), 7 deletions(-) diff --git a/target/loongarch/cpu-csr.h b/target/loongarc

[PATCH v4 08/11] target/loongarch: Reject la64-only instructions in la32 mode

LoongArch64-only instructions are marked with regard to the instruction manual Table 2. LSX instructions are not marked for now for lack of public manual. Signed-off-by: Jiajie Chen --- target/loongarch/insn_trans/trans_arith.c.inc | 32 .../loongarch/insn_trans/trans_atomic.c.inc | 7

[PATCH v4 05/11] target/loongarch: Support LoongArch32 DMW

LA32 uses a different encoding for CSR.DMW and a new direct mapping mechanism. Signed-off-by: Jiajie Chen --- target/loongarch/cpu-csr.h| 7 +++ target/loongarch/tlb_helper.c | 26 +++--- 2 files changed, 26 insertions(+), 7 deletions(-) diff --git a/target/loongarc

[PATCH v4 10/11] target/loongarch: Sign extend results in VA32 mode

In VA32 mode, BL, JIRL and PC* instructions should sign-extend the low 32 bit result to 64 bits. Signed-off-by: Jiajie Chen --- target/loongarch/insn_trans/trans_arith.c.inc | 2 +- target/loongarch/insn_trans/trans_branch.c.inc | 5 +++-- target/loongarch/translate.c | 13 +

[PATCH v4 11/11] target/loongarch: Add loongarch32 cpu la132

Add la132 as a loongarch32 cpu type and allow virt machine to be used with la132 instead of la464. Refactor common init logic out as loongarch_cpu_initfn_common. Signed-off-by: Jiajie Chen --- hw/loongarch/virt.c| 5 target/loongarch/cpu.c | 54

[PATCH v4 04/11] target/loongarch: Support LoongArch32 TLB entry

The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to zero in LoongArch32. Signed-off-by: Jiajie Chen --- target/loongarch/cpu-csr.h| 9 + target/loongarch/tlb_helper.c | 17 - 2 files changed, 17 insertions(+), 9 deletions(-) diff --git a/target/loo

[PATCH v4 07/11] target/loongarch: Add LA32 & VA32 to DisasContext

Add LA32 and VA32(32-bit Virtual Address) to DisasContext to allow the translator to reject doubleword instructions in LA32 mode for example. Signed-off-by: Jiajie Chen --- target/loongarch/cpu.h | 9 + target/loongarch/translate.c | 3 +++ target/loongarch/translate.h | 2 ++ 3 fi

[PATCH v4 01/11] target/loongarch: Add macro to check current arch

Add macro to check if the current cpucfg[1].arch equals to 1(LA32) or 2(LA64). Signed-off-by: Jiajie Chen --- target/loongarch/cpu.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index fa371ca8ba..bf0da8d5b4 100644 --- a/target/loongar

[PATCH v4 02/11] target/loongarch: Add new object class for loongarch32 cpus

Add object class for future loongarch32 cpus. It is derived from the loongarch64 object class. Signed-off-by: Jiajie Chen --- target/loongarch/cpu.c | 24 target/loongarch/cpu.h | 11 +++ 2 files changed, 35 insertions(+) diff --git a/target/loongarch/cpu.c b/ta

[PATCH v4 03/11] target/loongarch: Add GDB support for loongarch32 mode

GPRs and PC are 32-bit wide in loongarch32 mode. Signed-off-by: Jiajie Chen --- configs/targets/loongarch64-softmmu.mak | 2 +- gdb-xml/loongarch-base32.xml| 45 + target/loongarch/cpu.c | 10 +- target/loongarch/gdbstub.c |

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