On Sun Jun 4, 2023 at 8:28 PM AEST, Nicholas Piggin wrote:
> Differently-sized larx/stcx. pairs can succeed if the starting address
> matches. Add a size check to require stcx. exactly match the larx that
> established the reservation.
Hmm, question: reserve_addr is a VMSTATE field, but reserve_va
On 31/05/2023 09.13, Thomas Huth wrote:
On 09/05/2023 20.44, Peter Maydell wrote:
On Thu, 13 Apr 2023 at 17:26, Peter Maydell wrote:
On Thu, 13 Apr 2023 at 17:08, Michael Tokarev wrote:
30.03.2023 18:26, Thomas Huth wrote:
Booting a Linux kernel with the malta machine is currently broken
On 02/06/2023 22.03, Philippe Mathieu-Daudé wrote:
On 2/6/23 19:18, Thomas Huth wrote:
Let's make it easier for the users to spot network-related entries
in the summary of the meson output.
Signed-off-by: Thomas Huth
---
meson.build | 13 -
1 file changed, 8 insertions(+), 5 del
Am 31. Mai 2023 07:39:32 UTC schrieb "Philippe Mathieu-Daudé"
:
>On 31/5/23 08:36, Cédric Le Goater wrote:
>> On 5/31/23 08:17, Philippe Mathieu-Daudé wrote:
>>> +QOM tinkerers
>>>
>>> On 31/5/23 07:59, Cédric Le Goater wrote:
On 5/30/23 23:15, Philippe Mathieu-Daudé wrote:
> On 30/5/
On 01/06/2023 13:07, Michael S. Tsirkin wrote:
On Thu, May 25, 2023 at 05:03:15PM +0100, Mark Cave-Ayland wrote:
On 23/05/2023 20:56, Bernhard Beschow wrote:
This series:
* Removes dead code from omap_uart and i82378
* Resolves redundant code in the i8254 timer devices
v3:
* Drop TYPE_ISA_PA
On 04/06/2023 17:29, Laurent Vivier wrote:
Le 04/06/2023 à 15:14, Mark Cave-Ayland a écrit :
Also change the instantiation of the mac-nubus-bridge device to use
object_initialize_child() and map the Nubus address space using
memory_region_add_subregion() instead of sysbus_mmio_map().
Signed-of
On Fri, May 05, 2023 at 02:29:23PM +0800, Cindy Lu wrote:
> On Fri, May 5, 2023 at 11:29 AM Jason Wang wrote:
> >
> > Hi Cindy
> >
> > On Wed, May 3, 2023 at 5:13 PM Cindy Lu wrote:
> > >
> > > Hi All
> > > There is the RFC to support the IOMMUFD in vdpa device
> > > any comments are welcome
> >
The following changes since commit 848a6caa88b9f082c89c9b41afa975761262981d:
Merge tag 'migration-20230602-pull-request' of
https://gitlab.com/juan.quintela/qemu into staging (2023-06-02 17:33:29 -0700)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-lo
From: Jiaxun Yang
As per "Loongson 3A5000/3B5000 Processor Reference Manual",
Loongson 3A5000's IPI implementation have 4 mailboxes per
core.
However, in 78464f023b54 ("hw/loongarch/virt: Modify ipi as
percpu device"), the number of IPI mailboxes was reduced to
one, which mismatches actual hardw
On 6/4/23 19:54, Nicholas Piggin wrote:
lqarx does not set cpu_reserve, which causes stqcx. to never succeed.
Cc:qemu-sta...@nongnu.org
Fixes: 94bf2658676 ("target/ppc: Use atomic load for LQ and LQARX")
Fixes: 57b38ffd0c6 ("target/ppc: Use tcg_gen_qemu_{ld,st}_i128 for LQARX, LQ,
STQ")
Signed-
Differently-sized larx/stcx. pairs can succeed if the starting address
matches. Add a check to require the size of stcx. exactly match the larx
that established the reservation. Use the term "reserve_length" for this
state, which matches the terminology used in the ISA.
Reviewed-by: Richard Hender
Rework store conditional to avoid a branch in the success case.
Change some of the variable names and layout while here so
gen_conditional_store more closely matches gen_stqcx_.
Reviewed-by: Richard Henderson
Signed-off-by: Nicholas Piggin
---
v2:
- Reinstate lost DEF_MEMOP [Richard]
I think th
lqarx does not set cpu_reserve, which causes stqcx. to never succeed.
Cc: qemu-sta...@nongnu.org
Fixes: 94bf2658676 ("target/ppc: Use atomic load for LQ and LQARX")
Fixes: 57b38ffd0c6 ("target/ppc: Use tcg_gen_qemu_{ld,st}_i128 for LQARX, LQ,
STQ")
Signed-off-by: Nicholas Piggin
---
v2:
- Fix bu
larx and stcx. are not defined to order any memory operations.
Remove the barriers.
Reviewed-by: Richard Henderson
Signed-off-by: Nicholas Piggin
---
target/ppc/translate.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 538f
On Mon Jun 5, 2023 at 2:05 AM AEST, Richard Henderson wrote:
> On 6/4/23 03:28, Nicholas Piggin wrote:
> > lqarx does not set cpu_reserve, which causes stqcx. to never succeed.
> > Fix this and slightly rearrange gen_load_locked so the two functions
> > match more closely.
> >
> > Cc: qemu-sta...@
On Mon, Jun 5, 2023 at 12:18 AM Laurent Vivier wrote:
>
> Jason,
>
> if you agree with the changes I will merge them via the m68k branch.
Yes.
Acked-by: Jason Wang
Thanks
>
> Thanks,
> Laurent
>
> Le 04/06/2023 à 15:14, Mark Cave-Ayland a écrit :
> > This is to enable them to be used outside
@@ -3584,6 +3588,7 @@ static void gen_load_locked(DisasContext *ctx, MemOp
memop)
gen_set_access_type(ctx, ACCESS_RES);
gen_addr_reg_index(ctx, t0);
tcg_gen_mov_tl(cpu_reserve, t0);
+tcg_gen_movi_tl(cpu_reserve_size, memop_size(memop));
Not that it really matters, this pro
Le 04/06/2023 à 15:14, Mark Cave-Ayland a écrit :
Also change the instantiation of the mac-nubus-bridge device to use
object_initialize_child() and map the Nubus address space using
memory_region_add_subregion() instead of sysbus_mmio_map().
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/q800.c
On 6/4/23 03:28, Nicholas Piggin wrote:
Rework store conditional to avoid a branch in the success case.
Change some of the variable names and layout while here so
gen_conditional_store more closely matches gen_stqcx_.
Signed-off-by: Nicholas Piggin
---
target/ppc/translate.c | 65
Jason,
if you agree with the changes I will merge them via the m68k branch.
Thanks,
Laurent
Le 04/06/2023 à 15:14, Mark Cave-Ayland a écrit :
This is to enable them to be used outside of dp8393x.c.
Signed-off-by: Mark Cave-Ayland
CC: Jason Wang
Reviewed-by: Laurent Vivier
---
hw/net/dp83
Le 04/06/2023 à 15:14, Mark Cave-Ayland a écrit :
Also change the instantiation of the CPU to use object_initialize_child()
followed by a separate realisation.
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/q800.c | 18 +-
include/hw/m68k/q800.h | 3 +++
2 files change
On 6/4/23 03:28, Nicholas Piggin wrote:
larx and stcx. are not defined to order any memory operations.
Remove the barriers.
Signed-off-by: Nicholas Piggin
---
target/ppc/translate.c | 11 ---
1 file changed, 11 deletions(-)
Reviewed-by: Richard Henderson
r~
On 6/4/23 03:28, Nicholas Piggin wrote:
lqarx does not set cpu_reserve, which causes stqcx. to never succeed.
Fix this and slightly rearrange gen_load_locked so the two functions
match more closely.
Cc: qemu-sta...@nongnu.org
Fixes: 94bf2658676 ("target/ppc: Use atomic load for LQ and LQARX")
Fi
This will allow the q800-glue.h header to be included separately so that the
GLUE device can be referenced externally.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
---
MAINTAINERS | 2 +
hw/m68k/meson.build | 2 +-
hw/m68k/q800-glue.c | 252 +++
Also change the instantiation of the GLUE device to use
object_initialize_child().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
---
hw/m68k/q800.c | 24 ++--
include/hw/m68k/q800.h | 2 ++
2 files changed, 16 inse
Also change the instantiation of the SWIM device to use
object_initialize_child().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
---
hw/m68k/q800.c | 8 +---
include/hw/m68k/q800.h | 2 ++
2 files changed, 7 insertions(+), 3 deleti
Also change the instantiation of the mac-nubus-bridge device to use
object_initialize_child() and map the Nubus address space using
memory_region_add_subregion() instead of sysbus_mmio_map().
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/q800.c | 21 ++---
include/hw/m68k/q
Also change the instantiation of the ESP device to use
object_initialize_child().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
---
hw/m68k/q800.c | 9 +
include/hw/m68k/q800.h | 2 ++
2 files changed, 7 insertions(+), 4 deleti
The current use of aliased memory regions causes us 2 problems: firstly the
output of "info qom-tree" is absolutely huge and difficult to read, and
secondly we have already reached the internal limit for memory regions as
adding any new memory region into the mac-io region causes QEMU to assert
wit
Also change the instantiation of the macfb device to use
object_initialize_child().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
---
hw/m68k/q800.c | 6 --
include/hw/m68k/q800.h | 2 ++
2 files changed, 6 insertions(+), 2 deletio
Move all devices from the IO region to within the container in preparation
for updating the IO aliasing mechanism.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
---
hw/m68k/q800.c | 6 ++
include/hw/m68k/q800.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/hw/m
This brings GLUEState in line with our current QOM guidelines.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
---
hw/m68k/q800.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index 1aead224e2..bb9e857632 100
This is to enable them to be used outside of dp8393x.c.
Signed-off-by: Mark Cave-Ayland
CC: Jason Wang
Reviewed-by: Laurent Vivier
---
hw/net/dp8393x.c | 32 +
include/hw/net/dp8393x.h | 60
2 files changed, 61 insertions(+),
Also change the instantiation of the escc_orgate device to use
object_initialize_child().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
---
hw/m68k/q800.c | 16 +---
include/hw/m68k/q800.h | 2 ++
2 files changed, 11 inser
Instead use the qdev_get_child_bus() function which is intended for this exact
purpose.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
---
hw/m68k/q800.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index 14879310ca..df2765dbd1
Analysis of the MacOS toolbox ROM code shows that on startup it attempts 2
separate reads of the seconds registers with commands 0x9d...0x91 followed by
0x8d..0x81 without resetting the command to its initial value. The PRAM seconds
value is only accepted when the values of the 2 separate reads mat
A comparison between the rtc command table included in the comment and the code
itself shows that the decoding for PRAM addresses 0x0 to 0xf is being done on
the raw command, and not the shifted version held in value.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
---
hw/misc/mac_v
Also change the instantiation of the dp8393x device to use
object_initialize_child().
Signed-off-by: Mark Cave-Ayland
CC: Jason Wang
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
---
hw/m68k/q800.c | 6 --
include/hw/m68k/q800.h | 2 ++
2 files changed, 6 insert
Also change the instantiation of the VIA1 device to use
object_initialize_child().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
---
hw/m68k/q800.c | 16 +---
include/hw/m68k/q800.h | 2 ++
2 files changed, 11 insertions(+
Also change the instantiation of the ESCC device to use
object_initialize_child().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
---
hw/m68k/q800.c | 6 --
include/hw/m68k/q800.h | 2 ++
2 files changed, 6 insertions(+), 2 deletion
Also change the instantiation of the VIA2 device to use
object_initialize_child().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
---
hw/m68k/q800.c | 27 ---
include/hw/m68k/q800.h | 1 +
2 files changed, 17 in
Also change the instantiation of the CPU to use object_initialize_child()
followed by a separate realisation.
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/q800.c | 18 +-
include/hw/m68k/q800.h | 3 +++
2 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/hw/m6
This will enable us later to distinguish between QOM initialisation and machine
initialisation.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
Reviewed-by: Philippe Mathieu-Daudé
---
hw/m68k/q800.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/m68k/q8
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
---
hw/m68k/q800.c | 13 +
include/hw/m68k/q800.h | 2 ++
2 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index d0ceb64b70..f99241f
Ensure there is a space before the final closing brace for all global
properties.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
Reviewed-by: Philippe Mathieu-Daudé
---
hw/m68k/q800.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/m68k/q800.c b/h
[MCA: the original series has now been split into 2 separate parts based upon
Phil's comments re: QOM parenting for objects in Q800MachineState. Part 1
consists of the Q800MachineState patches along with QOM parenting fixes and
the 2 mac_via RTC patches.]
This series contains the remaining patches
This provides an overall container and owner for Machine-related objects such
as MemoryRegions.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
Reviewed-by: Philippe Mathieu-Daudé
---
MAINTAINERS| 1 +
hw/m68k/q800.c | 2 ++
include/hw/m68k/q800.h | 40 +++
On Fri, Jun 02, 2023 at 10:22:54PM -0500, Suravee Suthikulpanit wrote:
> Currently, pc-q35 and pc-i44fx machine models are default to use SMBIOS 2.8
> (32-bit entry point). Since SMBIOS 3.0 (64-bit entry point) is now fully
> supported since QEMU 7.0, default to use SMBIOS 3.0 for newer machine
> m
On 5/31/23 06:03, Richard Henderson wrote:
The replacement isn't ideal, as the raw count of bits
is not easily synced with exec/cpu-all.h, but it does
remove from tcg.h the target dependency on TARGET_PAGE_BITS_MIN
which is built into TLB_FLAGS_MASK.
Signed-off-by: Richard Henderson
---
inc
On 5/31/23 06:03, Richard Henderson wrote:
This will enable replacement of TARGET_INSN_START_WORDS in tcg.c.
Split out "tcg/insn-start-words.h" and use it in target/.
Signed-off-by: Richard Henderson
---
include/tcg/insn-start-words.h | 17 +
include/tcg/tcg-op.h
On 5/31/23 06:03, Richard Henderson wrote:
In preparation for compiling tcg/ only once, eliminate
the all_helpers array. Instantiate the info structs for
the generic helpers in accel/tcg/, and the structs for
the target-specific helpers in each translate.c.
Since we don't see all of the info
On Sat, 3 Jun 2023 at 15:23, Ard Biesheuvel wrote:
>
> On Sat, 3 Jun 2023 at 04:34, Richard Henderson
> wrote:
> >
> > Inspired by Ard Biesheuvel's RFC patches for accelerating AES
> > under emulation, provide a set of primitives that maps between
> > the guest and host fragments.
> >
> > There i
On 5/31/23 06:02, Richard Henderson wrote:
All uses replaced with TCGContext.addr_type.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
Reviewed-by: Anton Johansson
Differently-sized larx/stcx. pairs can succeed if the starting address
matches. Add a size check to require stcx. exactly match the larx that
established the reservation.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 1 +
target/ppc/cpu_init.c | 4 ++--
target/ppc/translate.c | 8
larx and stcx. are not defined to order any memory operations.
Remove the barriers.
Signed-off-by: Nicholas Piggin
---
target/ppc/translate.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 5195047146..77e1c5abb6 100644
--- a/
Rework store conditional to avoid a branch in the success case.
Change some of the variable names and layout while here so
gen_conditional_store more closely matches gen_stqcx_.
Signed-off-by: Nicholas Piggin
---
target/ppc/translate.c | 65 --
1 file chan
lqarx does not set cpu_reserve, which causes stqcx. to never succeed.
Fix this and slightly rearrange gen_load_locked so the two functions
match more closely.
Cc: qemu-sta...@nongnu.org
Fixes: 94bf2658676 ("target/ppc: Use atomic load for LQ and LQARX")
Fixes: 57b38ffd0c6 ("target/ppc: Use tcg_gen
On 01/06/2023 23:22, Alex Williamson wrote:
External email: Use caution opening links or attachments
On Tue, 30 May 2023 17:48:20 +0300
Avihai Horon wrote:
Add a new VFIO device property x-allow-pre-copy to keep migration
compatibility to/from older QEMU versions that don't have VFIO pre-c
58 matches
Mail list logo
