On Tue, Apr 25, 2023 at 08:42:17PM -0400, Peter Xu wrote:
> Hi, Michael, Jonathan,
>
> On Tue, Mar 07, 2023 at 08:13:53PM -0500, Michael S. Tsirkin wrote:
> > From: Jonathan Cameron
> >
> > This register in AER should be both writeable and should
> > have a default value with a couple of the err
The generated member visit neglects to emit #if around a conditional
struct member's has_ variable. For instance,
tests/qapi-schema/qapi-schema-test.json generates
#if defined(TEST_IF_STRUCT)
bool visit_type_TestIfStruct_members(Visitor *v, TestIfStruct *obj, Error
**errp)
{
--->
A struct's 'data' must be a JSON object defining the struct's members.
The QAPI code generator incorrectly accepts a JSON string instead, and
then crashes in QAPISchema._make_members() called from
._def_struct_type().
Fix to reject it: factor check_type_implicit() out of
check_type_name_or_implici
Signed-off-by: Markus Armbruster
Message-Id: <20230316071325.492471-7-arm...@redhat.com>
Reviewed-by: Eric Blake
[Commit message corrected]
---
scripts/qapi/expr.py | 14 +++---
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/scripts/qapi/expr.py b/scripts/qapi/expr.py
ind
We reject array types in certain places with "cannot be an array".
Deleting this check improves the error message to "should be a type
name" or "should be an object or type name", depending on context, so
do that.
Signed-off-by: Markus Armbruster
Message-Id: <20230316071325.492471-6-arm...@redhat
check_type() can check type names, arrays, and implicit struct types.
Callers pass flags to select from this menu. This makes the function
somewhat hard to read. Moreover, a few minor bugs are hiding in
there, as we'll see shortly.
Split it into check_type_name(), check_type_name_or_array(), and
Signed-off-by: Markus Armbruster
Message-Id: <20230316071325.492471-13-arm...@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé
---
tests/qapi-schema/qapi-schema-test.json | 3 ++-
tests/qapi-schema/qapi-schema-test.out | 2 ++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/tests/q
Positive test case
{ 'enum': 'TestIfEnum',
'data': [ 'foo', { 'name' : 'bar', 'if': 'TEST_IF_ENUM_BAR' } ],
'if': 'TEST_IF_ENUM' }
generates
#if defined(TEST_IF_ENUM)
typedef enum TestIfEnum {
TEST_IF_ENUM_FOO,
#if defined(TEST_IF_ENUM_BAR)
TEST_IF_ENU
We incorrectly report "FOO should be a type name" when it could also
be an array. Fix that.
Signed-off-by: Markus Armbruster
Message-Id: <20230316071325.492471-8-arm...@redhat.com>
Reviewed-by: Eric Blake
---
scripts/qapi/expr.py| 15 +++
tests/qapi-schema/e
From: Daniel P. Berrangé
It is possible to pass --update to tests/qapi-schema/test-qapi.py
to make it update the output files on error. This is inconvenient
to achieve though when test-qapi.py is run indirectly by make/meson.
Instead simply allow for an env variable to be set:
$ QAPI_TEST_UPDA
Union TestIfUnion is conditional on macros TEST_IF_UNION and
TEST_IF_STRUCT. It uses TestIfEnum, which is conditional on macro
TEST_IF_ENUM. If TEST_IF_UNION and TEST_IF_STRUCT are defined, but
TEST_IF_ENUM isn't, the generated code won't compile.
Command test-if-cmd is conditional an macros TES
Commit 4e99f4b12c0 (qapi: Drop simple unions) missed a bit of code
dealing with simple union branches. Drop it.
Signed-off-by: Markus Armbruster
Message-Id: <20230316071325.492471-4-arm...@redhat.com>
Reviewed-by: Eric Blake
---
scripts/qapi/expr.py | 2 +-
1 file changed, 1 insertion(+), 1 de
A union's 'discriminator' must name one of the common members.
QAPISchemaVariants.check() looks it up by its c_name(), then checks
the name matches exactly (because c_name() is not injective).
Tests union-base-empty and union-invalid-discriminator both cover the
case where lookup fails. Repurpose
From: Daniel P. Berrangé
This extends the QAPI schema validation to permit unions inside unions,
provided the checks for clashing fields pass.
Reviewed-by: Markus Armbruster
Signed-off-by: Daniel P. Berrangé
Message-Id: <20230420102619.348173-4-berra...@redhat.com>
Signed-off-by: Markus Armbru
The C code generator fails to honor 'if' conditions of command and
event arguments.
For instance, tests/qapi-schema/qapi-schema-test.json has
{ 'event': 'TEST_IF_EVENT',
'data': { 'foo': 'TestIfStruct',
'bar': { 'type': ['str'], 'if': 'TEST_IF_EVT_ARG' } },
'if': {
The following changes since commit 327ec8d6c2a2223b78d311153a471036e474c5c5:
Merge tag 'pull-tcg-20230423' of https://gitlab.com/rth7680/qemu into staging
(2023-04-23 11:20:37 +0100)
are available in the Git repository at:
https://repo.or.cz/qemu/armbru.git tags/pull-qapi-2023-04-26
for
Commit 2cae67bcb5e (qapi: Use super() now we have Python 3) converted
the code to super(). Shortly after, commit f965e8fea6a (qapi: New
special feature flag "deprecated") neglected to use super(). Convert
it now.
Signed-off-by: Markus Armbruster
Message-Id: <20230316071325.492471-3-arm...@redha
Error messages describe object members, enumeration values, features,
and variants like ROLE 'NAME', where ROLE is "member", "value",
"feature", or "branch", respectively. When the member is defined in
another type, e.g. inherited from a base type, we add "of type
'TYPE'". Example: test case stru
Commit 52a474180ae3 changed reporting of errors connected to a source
location without mentioning it in the commit message. For instance,
$ python scripts/qapi-gen.py tests/qapi-schema/unknown-escape.json
tests/qapi-schema/unknown-escape.json:3:21: unknown escape \x
became
scripts/q
在 2023/4/24 19:21, Viktor Prutyanov 写道:
The guest can disable or never enable ATS. In these cases, Device-TLB
can't be used even if enabled in QEMU. So, check ATS state before
registering IOMMU notifier and select flag depending on that. Also,
change IOMMU notifier flag if ATS state is changed.
在 2023/4/24 19:21, Viktor Prutyanov 写道:
Guest may enable or disable ATS for the device. Add logic for handling
these events.
Signed-off-by: Viktor Prutyanov
---
hw/virtio/virtio-pci.c | 12
include/hw/virtio/virtio.h | 2 ++
2 files changed, 14 insertions(+)
diff --git
在 2023/4/26 13:31, Jason Wang 写道:
在 2023/4/24 19:21, Viktor Prutyanov 写道:
According to PCIe Address Translation Services specification 5.1.3.,
ATS Control Register has Enable bit to enable/disable ATS.
Add a new field for a trigger function which is called at the Enable
bit change, so that PC
在 2023/4/24 19:21, Viktor Prutyanov 写道:
According to PCIe Address Translation Services specification 5.1.3.,
ATS Control Register has Enable bit to enable/disable ATS.
Add a new field for a trigger function which is called at the Enable
bit change, so that PCIe devices can handle ATS enable/dis
On 2023/04/26 4:28, Philippe Mathieu-Daudé wrote:
Fix the following Cocoa trivial warnings:
C compiler for the host machine: cc (clang 14.0.0 "Apple clang version 14.0.0
(clang-1400.0.29.202)")
Objective-C compiler for the host machine: clang (clang 14.0.0)
[100/334] Compiling Objecti
On Tue, Apr 25, 2023 at 07:14:34PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> On incoming migration we have the following sequence to load option
> ROM:
>
> 1. On device realize we do normal load ROM from the file
>
> 2. Than, on incoming migration we rewrite ROM from the incoming RAM
>bloc
The following instructions are added
J2_callrh
J2_junprh
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 4
target/hexagon/attribs_def.h.inc | 1 +
target/hexagon/imported/branch.idef | 7 ++-
target/hexagon/imported/encode_pp.def | 2 ++
4 files
The following instructions are added
V6_v6mpyvubs10_vxx
V6_v6mpyhubs10_vxx
V6_v6mpyvubs10
V6_v6mpyhubs10
Signed-off-by: Taylor Simpson
---
target/hexagon/mmvec/macros.h| 9 +-
target/hexagon/imported/mmvec/encode_ext.def | 8 +-
target/hexagon/imported/mmvec/e
---
tests/tcg/hexagon/v6mpy_ref.h | 161 ++
tests/tcg/hexagon/v68_hvx.c | 90 +
tests/tcg/hexagon/Makefile.target | 3 +
3 files changed, 254 insertions(+)
create mode 100644 tests/tcg/hexagon/v6mpy_ref.h
create mode 100644 tests/tcg/hexag
Tests added for the following instructions
J2_callrh
J2_jumprh
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/v73_scalar.c| 96 +++
tests/tcg/hexagon/Makefile.target | 2 +
2 files changed, 98 insertions(+)
create mode 100644 tests/tcg/hexagon/v73_s
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/v68_scalar.c| 186 ++
tests/tcg/hexagon/Makefile.target | 2 +
2 files changed, 188 insertions(+)
create mode 100644 tests/tcg/hexagon/v68_scalar.c
diff --git a/tests/tcg/hexagon/v68_scalar.c b/tests/tcg/hexag
Add support for the ELF flags
Move target/hexagon/cpu.[ch] to be v73
Change the compiler flag used by "make check-tcg"
The decbin instruction is removed in Hexagon v73, so check the
version before trying to compile the instruction.
Signed-off-by: Taylor Simpson
---
configure
The following instructions are tested
V6_vasrvuhubrndsat
V6_vasrvuhubsat
V6_vasrvwuhrndsat
V6_vasrvwuhsat
V6_vassign_tmp
V6_vcombine_tmp
V6_vmpyuhvs
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/v69_hvx.c | 318 ++
tests/tcg/hex
The following instructions are added
V6_vasrvuhubrndsat
V6_vasrvuhubsat
V6_vasrvwuhrndsat
V6_vasrvwuhsat
V6_vassign_tmp
V6_vcombine_tmp
V6_vmpyuhvs
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 12 ++
target/hexagon/attribs_def.h
The following instructions are added
L2_loadw_aq
L4_loadd_aq
R6_release_at_vi
R6_release_st_vi
S2_storew_rl_at_vi
S4_stored_rl_at_vi
S2_storew_rl_st_vi
S4_stored_rl_st_vi
The release instructions are nop's in qemu. The others behave as
loads/stores.
The encodings
Add support for new Hexagon architecture versions v68/v69/v71/v73
Taylor Simpson (9):
Hexagon (target/hexagon) Add support for v68/v69/v71/v73
Hexagon (target/hexagon) Add v68 scalar instructions
Hexagon (tests/tcg/hexagon) Add v68 scalar tests
Hexagon (target/hexagon) Add v68 HVX instruc
On Wed, Apr 26, 2023 at 12:43 AM Stefan Hajnoczi wrote:
>
> On Fri, Apr 21, 2023 at 11:36:02AM +0800, Yongji Xie wrote:
> > Hi Stefan,
> >
> > On Thu, Apr 20, 2023 at 7:39 PM Stefan Hajnoczi wrote:
> > >
> > > vduse_blk_detach_ctx() waits for in-flight requests using
> > > AIO_WAIT_WHILE(). This
ping~
在 2023/4/6 下午6:00, Song Gao 写道:
Add separate macro EXTIOI_CPUS for extioi interrupt controller, extioi
only supports 4 cpu. And set macro LOONGARCH_MAX_CPUS as 256 so that
loongarch virt machine supports more cpus.
Interrupts from external devices can only be routed cpu 0-3 because
of ext
ping ~
在 2023/4/6 下午6:00, Song Gao 写道:
ipi is used to communicate between cpus, this patch modified
loongarch ipi device as percpu deivce, so that there are
2 MemoryRegions with ipi device, rather than 2*cpus
MemoryRegions, which may be large than QDEV_MAX_MMIO if
more cpus are added on loongarc
ping ~
在 2023/4/6 下午6:00, Song Gao 写道:
When ipi mailbox is used, cpu index is decoded from iocsr register.
cpu maybe does not exist. This patch adss NULL pointer check on
ipi device.
Signed-off-by: Song Gao
---
hw/intc/loongarch_ipi.c | 31 +++
1 file changed, 19
Instead of print it to STDERR, bring the error upwards so that it can be
reported via QMP responses.
E.g.:
{ "execute": "migrate-set-capabilities" ,
"arguments": { "capabilities":
[ { "capability": "postcopy-ram", "state": true } ] } }
{ "error":
{ "class": "GenericError",
"desc": "Pos
On Wed, Apr 19, 2023 at 09:51:24PM +0200, Juan Quintela wrote:
> Peter Xu wrote:
> > Instead of print it to STDERR, bring the error upwards so that it can be
> > reported via QMP responses.
> >
> > E.g.:
> >
> > { "execute": "migrate-set-capabilities" ,
> > "arguments": { "capabilities":
> > [
在 2023/4/26 上午3:30, Richard Henderson 写道:
This header is supposed to be private to tcg and in fact
does not need to be included here at all.
Signed-off-by: Richard Henderson
---
target/loongarch/csr_helper.c | 1 -
target/loongarch/iocsr_helper.c | 1 -
2 files changed, 2 deletions(-)
Have gen_analyze_funcs mark the registers that are read by the
instruction. We also mark the implicit reads using instruction
attributes.
Signed-off-by: Taylor Simpson
---
target/hexagon/translate.h | 36 +++
target/hexagon/attribs_def.h.inc| 6 +++-
target/hex
The new_pred_value array in the CPUHexagonState is only used for
bookkeeping within the translation of a packet. With recent changes
that eliminate the need to free TCGv variables, these make more sense
to be transient and kept in DisasContext.
Suggested-by: Richard Henderson
Signed-off-by: Tayl
The pred_written variable in the CPUHexagonState is only used for
bookkeeping within the translation of a packet. With recent changes
that eliminate the need to free TCGv variables, these make more sense
to be transient and kept in DisasContext.
Suggested-by: Richard Henderson
Signed-off-by: Tay
The generated helpers for HVX use pass-by-reference, so they can't
short-circuit when the reads/writes overlap. The instructions with
overrides are OK because they use tcg_gen_gvec_*.
We add a flag has_hvx_helper to DisasContext and extend gen_analyze_funcs
to set the flag when the instruction is
When generating TCG, make sure we have read all the operand registers
before writing to the destination registers.
This is a prerequesite for short-circuiting where the source and dest
operands could be the same.
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr.c | 45 +++
The following items in the CPUHexagonState are only used for bookkeeping
within the translation of a packet. With recent changes that eliminate
the need to free TCGv variables, these make more sense to be transient
and kept in DisasContext.
The following items are moved
dczero_addr
branch
In certain cases, we can avoid the overhead of writing to hex_new_pred_value
and write directly to hex_pred. We consider predicate reads/writes when
computing ctx->need_commit. The get_result_pred() function uses this
field to decide between hex_new_pred_value and hex_pred. Then, we can
early-ex
In certain cases, we can avoid the overhead of writing to future_VRegs
and write directly to VRegs. We consider HVX reads/writes when computing
ctx->need_commit. Then, we can early-exit from gen_commit_hvx.
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr.c| 6 -
target/hexagon
The pkt_has_store_s1 field is only used for bookkeeping helpers with
a load. With recent changes that eliminate the need to free TCGv
variables, it makes more sense to make this transient.
These helpers already take the instruction slot as an argument. We
combine the slot and pkt_has_store_s1 in
In certain cases, we can avoid the overhead of writing to hex_new_value
and write directly to hex_gpr. We add need_commit field to DisasContext
indicating if the end-of-packet commit is needed. If it is not needed,
get_result_gpr() and get_result_gpr_pair() can return hex_gpr.
We pass the ctx->n
Only endloop instructions will conditionally write to a predicate.
When there is an endloop instruction, we preload the values into
new_pred_value.
The only place pred_written is needed is when HEX_DEBUG is on.
We remove the last use of check_for_attrib. However, new uses will be
introduced late
The following have overrides
S2_insert
S2_insert_rp
S2_asr_r_svw_trun
A2_swiz
These instructions have semantics that write to the destination
before all the operand reads have been completed. Therefore,
the idef-parser versions were disabled with the short-circuit patch.
Test cas
Precursor to moving new_value from the global state to DisasContext
USR will need to stay in the global state because some helpers will
set it's value
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu.h| 1 +
target/hexagon/genptr.h | 1 +
target/hexagon/macros.h
The new_value array in the CPUHexagonState is only used for bookkeeping
within the translation of a packet. With recent changes that eliminate
the need to free TCGv variables, these make more sense to be transient
and kept in DisasContext.
Suggested-by: Richard Henderson
Signed-off-by: Taylor Si
Hi, Michael, Jonathan,
On Tue, Mar 07, 2023 at 08:13:53PM -0500, Michael S. Tsirkin wrote:
> From: Jonathan Cameron
>
> This register in AER should be both writeable and should
> have a default value with a couple of the errors masked
> including the Uncorrectable Internal Error used by CXL for
These instructions have implicit reads from p0, so we don't want
them in helpers when idef-parser is off.
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 18 ++
target/hexagon/macros.h | 4
2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/target
These instructions have implicit writes to registers, so we don't
want them to be helpers when idef-parser is off.
The following instructions are overriden
S2_cabacdecbin
SA1_cmpeqi
Remove the log_pred_write function from op_helper.c
Remove references in macros.h
Signed-off-by: Taylor Si
With the overrides added in prior commits, this function is not used
Remove references in macros.h
Signed-off-by: Taylor Simpson
---
target/hexagon/macros.h| 14 --
target/hexagon/op_helper.h | 4
target/hexagon/op_helper.c | 17 -
3 files changed, 35 deleti
These instructions have implicit writes to registers, so we don't
want them to be helpers when idef-parser is off.
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 21 +++
target/hexagon/genptr.c | 44
2 files changed, 65 inse
These instructions have implicit writes to registers, so we don't
want them to be helpers when idef-parser is off.
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 32 +
target/hexagon/genptr.c | 44
2 files change
Add DisasContext arg to gen_log_reg_write_pair also
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h| 2 +-
target/hexagon/genptr.h | 2 +-
target/hexagon/genptr.c | 10 +-
target/hexagon/idef-parser/parser-helpers.c
Enable conditional compilation depending on whether idef-parser
is configured
Signed-off-by: Taylor Simpson
---
meson.build | 1 +
1 file changed, 1 insertion(+)
diff --git a/meson.build b/meson.build
index c44d05a13f..d4e438b033 100644
--- a/meson.build
+++ b/meson.build
@@ -1859,6 +1859,7 @@
This patch series achieves two major goals
Goal 1: Short-circuit packet semantics
In certain cases, we can avoid the overhead of writing to
hex_new_value and write directly to hex_gpr.
Here's a simple example of the TCG generated for
0x004000b4: 0x7800c020 { R0 = #0x1 }
Hi,
On 3/10/22 19:38, Patrick Venture wrote:
The MAC address set from Qemu wasn't being saved into the register space.
Reviewed-by: Hao Wu
Signed-off-by: Patrick Venture
---
v2: only set the registers from qemu on reset
once registers set, only read and write to them
---
hw/net/npcm7xx
On Tue, Apr 18, 2023, Ackerley Tng wrote:
> Sean Christopherson writes:
> > I agree, a pure alignment check is too restrictive, and not really what I
> > intended despite past me literally saying that's what I wanted :-) I think
> > I may have also inverted the "less alignment" statement, but luc
Store the bytes in descending order on big-endian.
Invert the logic in the multi-byte signed tests on big-endian.
Make the checks in the multi-byte signed tests stricter.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/multiarch/system/memory.c | 64 +++--
1 file changed, 4
Multiarch tests are written in C and need support for printing
characters. Instead of implementing the runtime from scratch, just
reuse the pc-bios/s390-ccw one.
Run tests with -nographic in order to enable SCLP (enable this for
the existing tests as well, since it does not hurt).
Use the default
v2: https://lists.gnu.org/archive/html/qemu-devel/2023-04/msg04154.html
v2 -> v3: The idea with sharing the QEMU headers with the tests seems
to be controversial. Just rework the test to work without
the explicit byte swaps.
v1: https://lists.gnu.org/archive/html/qemu-devel/202
On Thu, Oct 6, 2022 at 6:18 AM Peter Maydell
wrote:
> On Mon, 3 Oct 2022 at 18:38, Patrick Venture wrote:
> >
> > The MAC address set from Qemu wasn't being saved into the register space.
> >
> > Reviewed-by: Hao Wu
> > Signed-off-by: Patrick Venture
> > ---
> > v2: only set the registers from
On Tue, Apr 25, 2023 at 07:31:58PM +0200, Kevin Wolf wrote:
> This adds GRAPH_RDLOCK annotations to declare that callers of
> bdrv_refresh_limits() need to hold a reader lock for the graph because
> it accesses the children list of a node.
>
> Signed-off-by: Kevin Wolf
> ---
> include/block/bloc
On Tue, Apr 25, 2023 at 07:31:57PM +0200, Kevin Wolf wrote:
> This adds GRAPH_RDLOCK annotations to declare that callers of
> bdrv_recurse_can_replace() need to hold a reader lock for the graph
> because it accesses the children list of a node.
>
> Signed-off-by: Kevin Wolf
> ---
> include/block
On Tue, Apr 25, 2023 at 07:31:56PM +0200, Kevin Wolf wrote:
> This adds GRAPH_RDLOCK annotations to declare that callers of
> bdrv_query_block_graph_info() need to hold a reader lock for the graph
> because it accesses the children list of a node.
>
> Signed-off-by: Kevin Wolf
> ---
> include/bl
On Tue, Apr 25, 2023 at 07:31:55PM +0200, Kevin Wolf wrote:
> This adds GRAPH_RDLOCK annotations to declare that callers of
> bdrv_query_bds_stats() need to hold a reader lock for the graph because
> it accesses the children list of a node.
>
> Signed-off-by: Kevin Wolf
> ---
> block/qapi.c | 6
On Tue, Apr 25, 2023 at 07:31:54PM +0200, Kevin Wolf wrote:
> From: Emanuele Giuseppe Esposito
>
> This adds GRAPH_RDLOCK annotations to declare that callers of amend
> callbacks in BlockDriver need to hold a reader lock for the graph.
>
> Signed-off-by: Emanuele Giuseppe Esposito
> Signed-off-
On Tue, Apr 25, 2023 at 07:31:53PM +0200, Kevin Wolf wrote:
> From: Emanuele Giuseppe Esposito
>
> This adds GRAPH_RDLOCK annotations to declare that callers of
> bdrv_co_debug_event() need to hold a reader lock for the graph.
>
> Unfortunately we cannot use a co_wrapper_bdrv_rdlock, because the
On Tue, Apr 25, 2023 at 07:31:52PM +0200, Kevin Wolf wrote:
> From: Emanuele Giuseppe Esposito
>
> This adds GRAPH_RDLOCK annotations to declare that callers of
> bdrv_co_get_info() need to hold a reader lock for the graph.
>
> Signed-off-by: Emanuele Giuseppe Esposito
> Signed-off-by: Kevin Wo
On Tue, Apr 25, 2023 at 07:31:51PM +0200, Kevin Wolf wrote:
> From: Emanuele Giuseppe Esposito
>
> This adds GRAPH_RDLOCK annotations to declare that callers of
> bdrv_co_get_allocated_file_size() need to hold a reader lock for the
> graph.
>
> Signed-off-by: Emanuele Giuseppe Esposito
> Signed
On Tue, Apr 25, 2023 at 07:31:50PM +0200, Kevin Wolf wrote:
> This adds GRAPH_RDLOCK annotations to declare that functions accessing
> the parent list of a node need to hold a reader lock for the graph. As
> it happens, they already do.
>
> Signed-off-by: Kevin Wolf
> ---
> block/mirror.c | 2 +-
On Tue, Apr 25, 2023 at 07:31:49PM +0200, Kevin Wolf wrote:
> This adds GRAPH_RDLOCK annotations to declare that functions accessing
> the parent list of a node need to hold a reader lock for the graph. As
> it happens, they already do.
>
> Signed-off-by: Kevin Wolf
> ---
> block/vhdx.c | 9
On Tue, Apr 25, 2023 at 07:31:48PM +0200, Kevin Wolf wrote:
> From: Emanuele Giuseppe Esposito
>
> This adds GRAPH_RDLOCK annotations to declare that callers of
> nbd_co_do_establish_connection() need to hold a reader lock for the
> graph.
>
> Signed-off-by: Emanuele Giuseppe Esposito
> Signed-
On Tue, Apr 25, 2023 at 07:31:47PM +0200, Kevin Wolf wrote:
> The only thing nbd_co_flush() does is calling nbd_client_co_flush().
s/calling/call/
> Just use that function directly in the BlockDriver definitions and
> remove the wrapper.
>
> Signed-off-by: Kevin Wolf
> ---
> block/nbd.c | 11 +
On Tue, Apr 25, 2023 at 07:31:46PM +0200, Kevin Wolf wrote:
> Drivers were a bit confused about whether .bdrv_open can run in a
> coroutine and whether or not it holds a graph lock.
>
> It cannot keep a graph lock from the caller across the whole function
> because it both changes the graph (requi
From: Nicolas Pitre
Add CBQRI controllers to the RISC-V virt machine. The device properties
can be fully configured from the command line:
$ qemu-system-riscv64 -M virt ... \
-device riscv.cbqri.capacity,mmio_base=0x04828000[,...]
-device riscv.cbqri.bandwidth,mmio_base=0x04829000[
From: Nicolas Pitre
Add boolean property for CBQRI and imply it should be enabled for the
RISC-V virt machine.
Signed-off-by: Nicolas Pitre
Signed-off-by: Drew Fustini
---
Changes since v1:
- remove example SoC now that command line arguments supported for CBQRI
- change 'select RISC_CBQRI' to
From: Nicolas Pitre
Define structs to represent the hardware capabilities of capacity and
bandwidth controllers according to the RISC-V Capacity and Bandwidth QoS
Register Interface (CBQRI).
Link: https://github.com/riscv-non-isa/riscv-cbqri/blob/main/riscv-cbqri.pdf
Signed-off-by: Nicolas Pitre
Build the example SoC instantiation code when CBQRI_EXAMPLE_SOC is
enabled.
Signed-off-by: Nicolas Pitre
Signed-off-by: Drew Fustini
---
Note: the example SoC instantiation code is only included for reference
and it is not required anymore for the CBQRI proof-of-concept to work.
The CBQRI contro
From: Nicolas Pitre
Build the CBQRI controllers when RISC-V CBQRI is enabled by Kconfig.
Signed-off-by: Nicolas Pitre
Signed-off-by: Drew Fustini
---
Changes since v1:
- remove example SoC now that command line arguments supported for CBQRI
hw/riscv/meson.build | 2 ++
1 file changed, 2 inse
On Tue, Apr 25, 2023 at 07:31:45PM +0200, Kevin Wolf wrote:
> GRAPH_RDLOCK_GUARD() and GRAPH_RDLOCK_GUARD_MAINLOOP() only take a
> reader lock for the graph, so the correct annotation for them to use is
> TSA_ASSERT_SHARED rather than TSA_ASSERT.
The comments at the start of graph-lock.h state tha
This RFC series implements the Ssqosid extension and the sqoscfg CSR as
defined in the RISC-V Capacity and Bandwidth Controller QoS Register
Interface (CBQRI) specification [1]. Quality of Service (QoS) in this
context is concerned with shared resources on an SoC such as cache
capacity and memory b
From: Nicolas Pitre
Instantiate a hypothetical CBQRI configuration for testing purposes with
these properties:
- L2 cache controllers
- Resource type: Capacity
- NCBLKS: 12
- Number of access types: 2 (code and data)
- Usage monitoring not supported
- Capacity allocation op
From: Nicolas Pitre
Implement a capacity controller according to the Capacity and Bandwidth
QoS Register Interface (CBQRI) which supports these capabilities:
- Number of access types: 2 (code and data)
- Usage monitoring operations: CONFIG_EVENT, READ_COUNTER
- Event IDs supported: None, O
From: Kornel Dulęba
Implement the sqoscfg CSR defined by the Ssqosid ISA extension
(Supervisor-mode Quality of Service ID). The CSR contains two fields:
- Resource Control ID (RCID) used determine resource allocation
- Monitoring Counter ID (MCID) used to track resource usage
The CSR is def
From: Nicolas Pitre
Implement a bandwidth controller according to the Capacity and Bandwidth
QoS Register Interface (CBQRI) which supports these capabilities:
- Number of access types: 2 (code and data)
- Usage monitoring operations: CONFIG_EVENT, READ_COUNTER
- Event IDs supported: None,
On Tue, Apr 25, 2023 at 07:31:44PM +0200, Kevin Wolf wrote:
> For some function, parts of their interface is that are called without
> holding the graph lock. Add a new macro to document this.
Grammar is off; maybe:
For some functions, it is part of their interface to be called without
holding th
On Tue, 25 Apr 2023 at 18:37, Jonathan Cameron
wrote:
> We could explore only solving the problem for pxb-cxl for now.
> However, we would still be talking infrastructure in kernel only
> to support emulated CXL devices and I can see that being
> controversial. A normal CXL host bridge is not some
On Tue, Apr 25, 2023 at 07:31:43PM +0200, Kevin Wolf wrote:
> test-bdrv-drain contains a few test cases that are run both in coroutine
> and non-coroutine context. Running the entire code including the setup
> and shutdown in coroutines is incorrect because graph modifications can
> generally not h
On Tue, Apr 25, 2023 at 07:31:42PM +0200, Kevin Wolf wrote:
> This QMP handler runs in a coroutine, so it must use the corresponding
> no_co_wrappers instead.
>
> Signed-off-by: Kevin Wolf
> ---
> blockdev.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Eric Blake
>
On Tue, Apr 25, 2023 at 07:37:43PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> On 25.04.23 19:14, Vladimir Sementsov-Ogievskiy wrote:
> > Hi all!
> >
> > v2: simply ignore romfile on incoming migration when romsize is
> > specified.
> >
> > Here I suggest a way to solve a problem, when we have e
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