Hi,
On 2023-04-05 13:53, Alistair Francis wrote:
>
>On Mon, Mar 13, 2023 at 11:12 PM Hang Xu wrote:
>>
>> Because the starting address of ram is not necessarily 0,
>> the remaining free space in ram is
>> ram_size - (start - ram_base) instead of ram_size-start.
>
>I think this could be clea
On 2023/4/7 09:14, liweiwei wrote:
On 2023/4/7 04:22, Daniel Henrique Barboza wrote:
Hi,
This patch is going to break the sifive_u boot if I rebase
"[PATCH v6 0/9] target/riscv: rework CPU extensions validation"
on top of it, as it is the case today with the current
riscv-to-apply.next.
Using implicitly enabled extensions such as Zca/Zcf/Zcd instead of their
super extensions can simplify the extension related check. However, they
may have higher priv version than their super extensions. So we should mask
them in the isa_string based on priv version to make them invisible to user
i
Ping~
在 2023/3/28 下午5:35, Song Gao 写道:
The parameter '--disable-werror' is not required
when building the 'loongarch64-linux-user' target.
Fixes: c32b3fec34 ("target/loongarch: Update README")
Reported-by: Philippe Mathieu-Daudé
Signed-off-by: Song Gao
---
target/loongarch/README | 2 +-
1
在 2023/4/4 下午9:27, Alex Bennée 写道:
The calling function is already working with hwaddr and uint64_t so
lets avoid bringing target_ulong in if we don't need to.
Signed-off-by: Alex Bennée
---
hw/intc/loongarch_ipi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Song Ga
PRV_H has no real meaning, but just a reserved privilege mode currently.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu.h | 2 +-
target/riscv/cpu_bits.h | 2 +-
target/riscv/gdbstub.c | 2 +-
target/riscv/op_helper.c | 2 +-
4 files changed, 4 insertions(+)
This patchset tries to fix some problems in current implementation for
mstatus.MPP
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-mpp-fix-v3
v3:
* add patch 2 to remove PRV_H, and use PRV_RESERVED instead in some cases
* improve legalize_mpp and assert error message i
The MPP will be set to the least-privileged supported mode (U if
U-mode is implemented, else M).
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
---
target/riscv/op_helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/o
mstatus.MPP field is a WARL field since priv version 1.11, so we
remain it unchanged if an invalid value is written into it. And
after this, RVH shouldn't be passed to riscv_cpu_set_mode().
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu_helper.c | 8 ++--
target
On 4/6/2023 3:46 PM, Alex Bennée wrote:
>
> Fei Wu writes:
>
>> The translation ratio of host to guest instruction count is one of the
>> key performance factor of binary translation. TCG doesn't collect host
>> instruction count at present, it does collect host instruction size
>> instead, alth
On 2023/4/7 03:33, Richard Henderson wrote:
On 4/6/23 00:25, Weiwei Li wrote:
+static target_ulong legalize_mpp(CPURISCVState *env, target_ulong
old_mpp,
+ target_ulong val)
+{
+ target_ulong new_mpp = get_field(val, MSTATUS_MPP);
+ bool mpp_invalid = (ne
On 2023/4/7 03:28, Richard Henderson wrote:
On 4/6/23 00:25, Weiwei Li wrote:
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
{
- if (newpriv > PRV_M) {
+ if (newpriv > PRV_M || newpriv == PRV_H) {
g_assert_not_reached();
}
Nit: if (test) { assert_
On 2023/4/7 04:22, Daniel Henrique Barboza wrote:
Hi,
This patch is going to break the sifive_u boot if I rebase
"[PATCH v6 0/9] target/riscv: rework CPU extensions validation"
on top of it, as it is the case today with the current
riscv-to-apply.next.
The reason is that the priv spec ve
On 06.04.23 19:51, Hanna Czenczek wrote:
On 05.04.23 11:59, Vladimir Sementsov-Ogievskiy wrote:
On 04.04.23 20:32, Hanna Czenczek wrote:
On 04.04.23 10:10, Vladimir Sementsov-Ogievskiy wrote:
On 03.04.23 16:33, Hanna Czenczek wrote:
(Sorry for the rather late reply... Thanks for the review!)
On 4/5/23 18:42, Taylor Simpson wrote:
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h| 4 +-
target/hexagon/genptr.h | 10 ++---
target/hexagon/macros.h | 8
target/hexagon/genptr.c | 49 +++
On 6/4/23 19:42, Taylor Simpson wrote:
This will facilitate adding additional tests in separate .c files
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/hvx_misc.h | 178 ++
tests/tcg/hexagon/hvx_misc.c | 160 +--
tests/tcg/h
On 6/4/23 17:59, Peter Maydell wrote:
Coverity complains (CID 1507880) that the declaration "int error_code;"
in mmu_translate() is unreachable code. Since this is only a declaration,
this isn't actually a bug, but:
* it's a bear-trap for future changes, because if it was changed to
include
On Tue, Apr 04, 2023 at 06:17:45PM +0200, Kevin Wolf wrote:
> Am 04.04.2023 um 17:07 hat Michael Tokarev geschrieben:
> > 04.04.2023 16:57, Kevin Wolf пишет:
> Maybe -snapshot should error out if -blockdev is in use. You'd generally
> expect that either -blockdev is used primarily and snapshots are
Hi,
This patch is going to break the sifive_u boot if I rebase
"[PATCH v6 0/9] target/riscv: rework CPU extensions validation"
on top of it, as it is the case today with the current riscv-to-apply.next.
The reason is that the priv spec version for Zca is marked as 1_12_0, and
the priv spec ve
Hi Qianfan,
The tests look good to me and are working OK:
ARMBIAN_ARTIFACTS_CACHED=yes AVOCADO_ALLOW_LARGE_STORAGE=yes
./build/tests/venv/bin/avocado --show=app,console run -t machine:bpim2u
tests/avocado/boot_linux_console.py
(1/4)
tests/avocado/boot_linux_console.py:BootLinuxConsole.test_arm_b
On Tue, Mar 28, 2023 at 7:47 AM wrote:
> From: qianfan Zhao
>
> A64's sd register was similar to H3, and it introduced a new register
> named SAMP_DL_REG location at 0x144. The dma descriptor buffer size of
> mmc2 is only 8K and the other mmc controllers has 64K.
>
> Signed-off-by: qianfan Zhao
> -Original Message-
> From: Matheus Bernardino (QUIC)
> Sent: Thursday, April 6, 2023 2:30 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Taylor Simpson
> ; alex.ben...@linaro.org; f4...@amsat.org;
> peter.mayd...@linaro.org; Sid Manning
> Subject: [PATCH 5/7] Hexagon (gdbstub): fi
If gt_timer is enabled before cval initialization on a virtualized
setup on QEMU, cval equals (UINT64_MAX - 1). Adding an offset value
to this causes an overflow that sets timer into the past, which leads
to infinite loop, because this timer fires immediately and calls
gt_recalc_timer() once more,
On 4/6/23 08:08, Peter Maydell wrote:
So that we can avoid the "older gdb crashes" problem described in
commit 5787d17a42f7af4 and which caused us to disable reporting pauth
information via the gdbstub, newer gdb is going to implement support
for recognizing the pauth information via a new featur
On 4/6/23 00:25, Weiwei Li wrote:
+static target_ulong legalize_mpp(CPURISCVState *env, target_ulong old_mpp,
+ target_ulong val)
+{
+target_ulong new_mpp = get_field(val, MSTATUS_MPP);
+bool mpp_invalid = (new_mpp == PRV_S && !riscv_has_ext(env, RVS)) ||
+
From: Taylor Simpson
This enables LLDB to work with hexagon linux-user mode through the GDB
remote protocol.
Signed-off-by: Taylor Simpson
Signed-off-by: Matheus Tavares Bernardino
---
linux-user/hexagon/cpu_loop.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/linux-user/hex
From: Brian Cain
Signed-off-by: Brian Cain
Signed-off-by: Matheus Tavares Bernardino
---
target/hexagon/gdb_qreginfo.h | 124 ++
target/hexagon/cpu.c | 3 +
2 files changed, 127 insertions(+)
create mode 100644 target/hexagon/gdb_qreginfo.h
diff --g
From: Taylor Simpson
Co-authored-by: Brian Cain
Signed-off-by: Brian Cain
Signed-off-by: Taylor Simpson
Co-authored-by: Matheus Tavares Bernardino
Signed-off-by: Matheus Tavares Bernardino
---
target/hexagon/gdbstub.c | 60
1 file changed, 60 inserti
GDB's remote serial protocol allows stop-reply messages to be sent by
the stub either as a notification packet or as a reply to a GDB command
(provided that the cmd accepts such a response). QEMU currently does not
implement notification packets, so it should only send stop-replies
synchronously an
From: Brian Cain
Co-authored-by: Sid Manning
Signed-off-by: Sid Manning
Signed-off-by: Brian Cain
Co-authored-by: Matheus Tavares Bernardino
Signed-off-by: Matheus Tavares Bernardino
---
target/hexagon/gdbstub.c | 16
1 file changed, 16 insertions(+)
diff --git a/target/he
From: Brian Cain
Signed-off-by: Brian Cain
Signed-off-by: Matheus Tavares Bernardino
---
include/hw/core/cpu.h | 4
gdbstub/gdbstub.c | 27 +++
2 files changed, 31 insertions(+)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 821e937020..b16b
In the previous commit, we modified gdbstub.c to only send stop-reply
packets as a response to GDB commands that accept it. Now, let's add a
test for this intended behavior. Running this test before the fix from
the previous commit fails as QEMU sends a stop-reply packet
asynchronously, when GDB wa
This series allows hexagon programs to be debugged under qemu user-mode
through LLDB and qemu's gdbstub. LLDB implements the GDB remote serial
protocol, so most of the necessary changes are in the Hexagon part itself.
However, one fix is needed at the arch-independent side too. This comes
from [1],
On 4/6/23 00:25, Weiwei Li wrote:
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
{
-if (newpriv > PRV_M) {
+if (newpriv > PRV_M || newpriv == PRV_H) {
g_assert_not_reached();
}
Nit: if (test) { assert_not_reached } -> assert(!test).
which emits a
On Tue, Mar 28, 2023 at 7:48 AM wrote:
> From: qianfan Zhao
>
> Add documents for Banana Pi M2U
>
> Signed-off-by: qianfan Zhao
>
Reviewed-by: Niek Linnenbank
> ---
> docs/system/arm/bananapi_m2u.rst | 138 +++
> 1 file changed, 138 insertions(+)
> create mode 1
Hi Qianfan Zhao,
Is this change really needed as a separate patch?
Looks like it would make sense just to squash it with the original patch 01?
Regards,
Niek
On Tue, Mar 28, 2023 at 7:47 AM wrote:
> From: qianfan Zhao
>
> R40 has SAMP_DL_REG register and mmc2 controller has only 8K dma buffer
On Tue, Mar 28, 2023 at 7:47 AM wrote:
> From: qianfan Zhao
>
> The CCU provides the registers to program the PLLs and the controls
> most of the clock generation, division, distribution, synchronization
> and gating.
>
> This commit adds support for the Clock Control Unit which emulates
> a sim
Hi Qianfan Zhao,
On Tue, Mar 28, 2023 at 7:47 AM wrote:
> From: qianfan Zhao
>
> Allwinner R40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU,
> and a Mali400 MP2 GPU from ARM. It's also known as the Allwinner T3
> for In-Car Entertainment usage, A40i and A40pro are variants that
> differ
On Thu, 6 Apr 2023 11:29:34 +0200
Robin Voetter wrote:
> Hello,
>
> I am trying to use qemu to run ROCm in a virtual machine via GPU
> passthrough with vfio-pci. While this mostly works out of the box, ROCm
> requires PCIe atomics to function properly, and it seems like that this
> is a featu
The code that disables extensions if there's a priv version mismatch
uses cpu->cfg.ext_N properties to do its job.
We're aiming to not rely on cpu->cfg.ext_N props for MISA bits. Split
the MISA related verifications in a new function, removing it from
isa_edata_arr[].
We're also erroring it out i
Create a new "i" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVI. Instances of cpu->cfg.ext_i and similar are
replaced with riscv_has_ext(env, RVI).
Remove the old "i" property and 'ext_i' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Create a new "s" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVS. Instances of cpu->cfg.ext_s and similar are
replaced with riscv_has_ext(env, RVS).
Remove the old "s" property and 'ext_s' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
We don't have MISA extensions in isa_edata_arr[] anymore. Remove the
redundant 'multi_letter' field from isa_ext_data.
Suggested-by: Weiwei Li
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 132 ++---
This CPU is enabling G via cfg.ext_g and, at the same time, setting
IMAFD in set_misa() and cfg.ext_icsr.
riscv_cpu_validate_set_extensions() is already doing that, so there's no
need for cpu_init() setups to worry about setting G and its extensions.
Signed-off-by: Daniel Henrique Barboza
Review
Create a new "h" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVH. Instances of cpu->cfg.ext_h and similar are
replaced with riscv_has_ext(env, RVH).
Remove the old "h" property and 'ext_h' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
We're still have one RISCVCPUConfig MISA flag, 'ext_g'. We'll remove it
the same way we did with the others: create a "g" RISCVCPUMisaExtConfig
property, remove the old "g" property, remove all instances of 'cfg.ext_g'
and use riscv_has_ext(env, RVG).
The caveat is that we don't have RVG, so add i
Create a new "e" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVE. Instances of cpu->cfg.ext_e and similar are
replaced with riscv_has_ext(env, RVE).
Remove the old "e" property and 'ext_e' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
This function was created to move the sync between cpu->cfg.ext_N bit
changes to env->misa_ext* from the validation step to an ealier step,
giving us a guarantee that we could use either cpu->cfg.ext_N or
riscv_has_ext(env,N) in the validation.
We don't have any cpu->cfg.ext_N left that has an exi
Hi,
This new version was rebased on top of Alistair's riscv-to-apply.next @
9c60ca583cb ("hw/riscv: Add signature dump function ...").
No other changes made.
Changes from v3:
- rebased with riscv-to-apply.next @ 9c60ca583cb
- v3 link: https://lists.gnu.org/archive/html/qemu-devel/2023-03/msg0691
The function is now a no-op for all cpu_init() callers that are setting
a non-zero misa value in set_misa(), since it's no longer used to sync
cpu->cfg props with env->misa_ext bits. Remove it in those cases.
While we're at it, rename the function to match what it's actually
doing: create user pro
Create a new "v" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVV. Instances of cpu->cfg.ext_v and similar are
replaced with riscv_has_ext(env, RVV).
Remove the old "v" property and 'ext_v' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Create a new "f" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVF. Instances of cpu->cfg.ext_f and similar are
replaced with riscv_has_ext(env, RVF).
Remove the old "f" property and 'ext_f' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Create a new "m" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVM. Instances of cpu->cfg.ext_m and similar are
replaced with riscv_has_ext(env, RVM).
Remove the old "m" property and 'ext_m' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Create a new "u" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVU. Instances of cpu->cfg.ext_u and similar are
replaced with riscv_has_ext(env, RVU).
Remove the old "u" property and 'ext_u' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
When riscv_cpu_realize() starts we're guaranteed to have cpu->cfg.ext_N
properties updated. The same can't be said about env->misa_ext*, since
the user might enable/disable MISA extensions in the command line, and
env->misa_ext* won't caught these changes. The current solution is to
sync everything
Create a new "c" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVC. Instances of cpu->cfg.ext_c and similar are
replaced with riscv_has_ext(env, RVC).
Remove the old "c" property and 'ext_c' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Create a new "a" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVA. Instances of cpu->cfg.ext_a and similar are
replaced with riscv_has_ext(env, RVA).
Remove the old "a" property and 'ext_a' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Create a new "j" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVJ. Instances of cpu->cfg.ext_j and similar are
replaced with riscv_has_ext(env, RVJ).
Remove the old "j" property and 'ext_j' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Create a new "d" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVD. Instances of cpu->cfg.ext_d and similar are
replaced with riscv_has_ext(env, RVD).
Remove the old "d" property and 'ext_d' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Ever since RISCVCPUConfig got introduced users are able to set CPU extensions
in the command line. User settings are reflected in the cpu->cfg object
for later use. These properties are used in the target/riscv/cpu.c code,
most notably in riscv_cpu_validate_set_extensions(), where most of our
reali
Hello Philippe
On 4/5/23 18:04, Philippe Mathieu-Daudé wrote:
The 'kvm_sw_tlb' field shouldn't be accessed when KVM is not available.
Signed-off-by: Philippe Mathieu-Daudé
---
target/ppc/cpu.h| 2 ++
target/ppc/mmu_common.c | 4
2 files changed, 6 insertions(+)
diff --git a/t
This will facilitate adding additional tests in separate .c files
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/hvx_misc.h | 178 ++
tests/tcg/hexagon/hvx_misc.c | 160 +--
tests/tcg/hexagon/Makefile.target | 1 +
3 files chan
Queued, thanks.
Paolo
Hello!
This PR fixes use-after-free errors in util/error.c as reported by Coverity.
Regards,
Stefan
The following changes since commit 60ca584b8af0de525656f959991a440f8c191f12:
Merge tag 'pull-for-8.0-220323-1' of https://gitlab.com/stsquad/qemu into
staging (2023-03-22 17:58:12 +
Fix use-after-free errors in the code path that called error_handle(). A
call to error_handle() will now either free the passed Error 'err' or
assign it to '*errp' if '*errp' is currently NULL. This ensures that 'err'
either has been freed or is assigned to '*errp' if this function returns.
Adjust
On 4/6/23 05:09, gaosong wrote:
HI, Richard
在 2023/3/29 上午4:46, Richard Henderson 写道:
+static void do_vmuh_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
+ uint32_t vk_ofs, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen3 op[4] = {
+ {
+ .
On 05.04.23 11:59, Vladimir Sementsov-Ogievskiy wrote:
On 04.04.23 20:32, Hanna Czenczek wrote:
On 04.04.23 10:10, Vladimir Sementsov-Ogievskiy wrote:
On 03.04.23 16:33, Hanna Czenczek wrote:
(Sorry for the rather late reply... Thanks for the review!)
On 20.03.23 11:31, Vladimir Sementsov-Ogi
Peter Xu writes:
> On Tue, Apr 04, 2023 at 05:10:52PM +0200, Claudio Fontana wrote:
>> On 4/4/23 16:53, Peter Xu wrote:
>> > On Tue, Apr 04, 2023 at 10:00:16AM +0200, Claudio Fontana wrote:
>> >> Hi Peter,
>> >
>> > Hi, Claudio,
>> >
>> >>
>> >> On 4/3/23 21:26, Peter Xu wrote:
>> >>> Hi, Claud
On Thu, 2023-04-06 at 16:48 +0100, Peter Maydell wrote:
> On Thu, 2 Mar 2023 at 12:37, Paolo Bonzini wrote:
> >
> > From: David Woodhouse
> >
> > The way that Xen handles MSI PIRQs is kind of awful.
>
> > Now that this is working we can finally enable XENFEAT_hvm_pirqs and
> > let the guest us
On Mon, 7 Nov 2022 at 22:53, Michael S. Tsirkin wrote:
>
> From: Jason Wang
>
> This patch introduce ECAP_PASID via "x-pasid-mode".
Hi; Coverity points out an issue with this code (CID 1508100):
> -static guint vtd_uint64_hash(gconstpointer v)
> +static guint vtd_iotlb_hash(gconstpointer v)
>
Hi
On Thu, Apr 6, 2023 at 7:43 PM Stefan Berger wrote:
>
> Fix use-after-free errors in the code path that called error_handle(). A
> call to error_handle() will now either free the passed Error 'err' or
> assign it to '*errp' if '*errp' is currently NULL. This ensures that 'err'
> either has bee
Coverity complains (CID 1507880) that the declaration "int error_code;"
in mmu_translate() is unreachable code. Since this is only a declaration,
this isn't actually a bug, but:
* it's a bear-trap for future changes, because if it was changed to
include an initialization 'int error_code = foo;'
On 6/4/23 17:43, Stefan Berger wrote:
Fix use-after-free errors in the code path that called error_handle(). A
call to error_handle() will now either free the passed Error 'err' or
assign it to '*errp' if '*errp' is currently NULL. This ensures that 'err'
either has been freed or is assigned to '
On 6/4/23 17:37, Peter Maydell wrote:
Coverity points out (in CID 1508390) that write_bootloader has
some dead code, where we assign to 'p' and then in the following
line assign to it again. This happened as a result of the
refactoring in commit cd5066f8618b.
Fix the dead code by removing the 'v
On Thu, 6 Apr 2023 at 16:43, Stefan Berger wrote:
>
> Fix use-after-free errors in the code path that called error_handle(). A
> call to error_handle() will now either free the passed Error 'err' or
> assign it to '*errp' if '*errp' is currently NULL. This ensures that 'err'
> either has been free
On Thu, 2 Mar 2023 at 12:37, Paolo Bonzini wrote:
>
> From: David Woodhouse
>
> The way that Xen handles MSI PIRQs is kind of awful.
> Now that this is working we can finally enable XENFEAT_hvm_pirqs and
> let the guest use it all.
>
Hi; Coverity points out a logic error in this code (CID 15076
Fix use-after-free errors in the code path that called error_handle(). A
call to error_handle() will now either free the passed Error 'err' or
assign it to '*errp' if '*errp' is currently NULL. This ensures that 'err'
either has been freed or is assigned to '*errp' if this function returns.
Adjust
Coverity points out (in CID 1508390) that write_bootloader has
some dead code, where we assign to 'p' and then in the following
line assign to it again. This happened as a result of the
refactoring in commit cd5066f8618b.
Fix the dead code by removing the 'void *v' variable entirely and
instead ad
Hi
On Thu, Apr 6, 2023 at 7:00 PM Stefan Berger wrote:
>
>
>
> On 4/6/23 10:36, Peter Maydell wrote:
> > On Thu, 6 Apr 2023 at 15:13, Stefan Berger wrote:
> >> I'll be out starting tomorrow. I don't see Marc-André online.
> >>
> >> Would this be acceptable?
> >> It ensures that if error_handle()
Ping? This should go in rc4, there is not much time left to prepare a
PULL...
Best Regards,
Lukas Straub
On Tue, 4 Apr 2023 14:36:03 +
Lukas Straub wrote:
> Since ec6f3ab9, migration with compress enabled was broken, because
> the compress threads use a dummy QEMUFile which just acts as a
>
On Tue, 7 Mar 2023 at 18:28, David Woodhouse wrote:
>
> From: David Woodhouse
>
> There's no need for this to be in the Xen accel code, and as we want to
> use the Xen console support with KVM-emulated Xen we'll want to have a
> platform-agnostic version of it. Make it use GString to build up the
Stefan Berger writes:
> On 4/6/23 09:17, Peter Maydell wrote:
>> On Thu, 6 Apr 2023 at 14:16, Peter Maydell wrote:
>>>
>>> On Mon, 13 Mar 2023 at 11:47, wrote:
From: Marc-André Lureau
This can help debugging issues or develop, when error handling is
introduced.
>>
So that we can avoid the "older gdb crashes" problem described in
commit 5787d17a42f7af4 and which caused us to disable reporting pauth
information via the gdbstub, newer gdb is going to implement support
for recognizing the pauth information via a new feature name:
org.gnu.gdb.aarch64.pauth_v2
O
On Thu, Apr 06, 2023 at 08:48:34AM +0200, Thomas Huth wrote:
> On 06/04/2023 08.33, Michael Tokarev wrote:
> > 06.04.2023 00:06, Michael Roth пишет:
> > ..
> > > Re-packaged tarball based on your 7.2.1 tag is now uploaded:
> > >
> > > https://www.qemu.org/download/
> >
> > Thank you Michael!
On Thu, Apr 06, 2023 at 12:55:38PM +0200, Lukáš Doktor wrote:
> Hello Florian, folks,
>
> my CI caught ~5% regression (in 60s runs, when using 240s it was about 10%)
> in qemu-nbd performance bisected multiple-times up to
> bd2cd4a441ded163b62371790876f28a9b834317 in fio when using 4k blocks rea
On Thu, 6 Apr 2023 at 16:00, Stefan Berger wrote:
>
>
>
> On 4/6/23 10:36, Peter Maydell wrote:
> > On Thu, 6 Apr 2023 at 15:13, Stefan Berger wrote:
> >> I'll be out starting tomorrow. I don't see Marc-André online.
> >>
> >> Would this be acceptable?
> >> It ensures that if error_handle() retur
On Thu, Apr 06, 2023 at 09:54:55AM +0300, Michael Tokarev wrote:
> 06.04.2023 09:48, Thomas Huth пишет:
> ..>> There's one minor caveat still, though: it is missing in the
> > > "Full list of releases" for whatever reason. Dunno how that
> > > happened, maybe that page hasn't been (re)generated ye
On 4/6/23 10:36, Peter Maydell wrote:
On Thu, 6 Apr 2023 at 15:13, Stefan Berger wrote:
I'll be out starting tomorrow. I don't see Marc-André online.
Would this be acceptable?
It ensures that if error_handle() returns, err has been freed.
In the other two cases a copy is being made of the E
Alex Bennée writes:
> We are a bit premature in recommending -blockdev/-device as the best
> way to configure block devices. It seems there are times the more
> human friendly -drive still makes sense especially when -snapshot is
> involved.
>
> Improve the language to hopefully make things clear
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Thursday, April 6, 2023 2:24 AM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: richard.hender...@linaro.org; a...@rev.ng; a...@rev.ng; Brian Cain
> ; Matheus Bernardino (QUIC)
>
> Subject: Re: [PATCH] Hexagon (tests/tcg/hex
On Thu, 6 Apr 2023 at 15:13, Stefan Berger wrote:
> I'll be out starting tomorrow. I don't see Marc-André online.
>
> Would this be acceptable?
> It ensures that if error_handle() returns, err has been freed.
> In the other two cases a copy is being made of the Error that can then be
> used after
Am 06.04.23 um 14:39 schrieb Peter Maydell:
On Thu, 6 Apr 2023 at 13:30, Thomas Huth wrote:
The thing is: it shouldn't take that long to build QEMU and run the tests
here, theoretically. Some days ago, the job was finishing in 39 minutes:
https://gitlab.com/qemu-project/qemu/-/jobs/39734
On 4/6/23 09:17, Peter Maydell wrote:
On Thu, 6 Apr 2023 at 14:16, Peter Maydell wrote:
On Mon, 13 Mar 2023 at 11:47, wrote:
From: Marc-André Lureau
This can help debugging issues or develop, when error handling is
introduced.
Signed-off-by: Marc-André Lureau
Reviewed-by: Stefan Berg
Thanks Jonathan for quick review/comments on earlier patch, as suggested
splitting into two separate patches
https://www.mail-archive.com/qemu-devel@nongnu.org/msg952999.html
Removed the unsupported size option for cxl-type3 device, Qemu reads
the device size directly from the backend memory devic
cxl-type3 memory size is read directly from the provided memory backed end
device. Remove non existent size option
Signed-off-by: Raghu H
---
docs/system/devices/cxl.rst | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/
Currently Qemu CXL emulation support is not availabe on AARCH64 but its
available with qemu x86_64 architecture, updating the document to reflect
the supported platform.
Signed-off-by: Raghu H
---
docs/system/devices/cxl.rst | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
Hello,
I am trying to use qemu to run ROCm in a virtual machine via GPU
passthrough with vfio-pci. While this mostly works out of the box, ROCm
requires PCIe atomics to function properly, and it seems like that this
is a feature that is missing in qemu. The setup is using a simple PCie
topolo
The event filename is an absolute path. Convert it to a relative path when
writing '#line' directives, to preserve reproducibility of the generated
output when different base paths are used.
Signed-off-by: Thomas De Schampheleire
---
scripts/tracetool/backend/ftrace.py | 4 +++-
scripts/tracetoo
On Thu, 6 Apr 2023 at 14:16, Peter Maydell wrote:
>
> On Mon, 13 Mar 2023 at 11:47, wrote:
> >
> > From: Marc-André Lureau
> >
> > This can help debugging issues or develop, when error handling is
> > introduced.
> >
> > Signed-off-by: Marc-André Lureau
> > Reviewed-by: Stefan Berger
> > Messa
On Mon, 13 Mar 2023 at 11:47, wrote:
>
> From: Marc-André Lureau
>
> This can help debugging issues or develop, when error handling is
> introduced.
>
> Signed-off-by: Marc-André Lureau
> Reviewed-by: Stefan Berger
> Message-Id: <20230221124802.4103554-6-marcandre.lur...@redhat.com>
Hi; Coveri
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