On Fri, Mar 24, 2023 at 3:54 AM Eugenio Pérez wrote:
>
The title needs some tweak, I think the more appropriate one is
"introduce vhost_vdpa_call_fd()"
> This allows to reset a vhost-vdpa device from external subsystems like
> vhost-net, since it does not have any struct vhost_dev by the time we
On Fri, Mar 24, 2023 at 3:54 AM Eugenio Pérez wrote:
>
> It is always 0 and it is not useful to route call through file
> descriptor.
>
> Signed-off-by: Eugenio Pérez
Acked-by: Jason Wang
Thanks
> ---
> hw/virtio/vhost-vdpa.c | 2 +-
> hw/virtio/trace-events | 2 +-
> 2 files changed, 2 inse
On 3/27/23 22:24, Stefan Berger wrote:
Add a test case for the TPM TIS I2C device exercising most of its
functionality, including localities.
Signed-off-by: Stefan Berger
---
tests/qtest/meson.build| 3 +
tests/qtest/tpm-tis-i2c-test.c | 637 +
2 fi
On 3/27/23 22:24, Stefan Berger wrote:
Add read and write functions for accessing registers of I2C devices
connected to the Aspeed I2C controller.
Signed-off-by: Stefan Berger
Reviewed-by: Cédric Le Goater
[... ]
+#ifndef QTEST_ASPEED_H
+#define QTEST_ASPEED_H
+
+#include
+
+#define AST2
On 3/27/23 20:33, Ninad Palsule wrote:
Qemu already supports devices attached to ISA and sysbus. This drop adds
support for the I2C bus attached TPM devices. I2C model only supports
TPM2 protocol.
This commit includes changes for the common code.
- Added I2C emulation model. Logic was added in t
Am 27.03.23 um 23:09 schrieb Paolo Bonzini:
Il lun 27 mar 2023, 20:58 Philippe Mathieu-Daudé
ha scritto:
> The warning can also be suppressed if the build uses `-isystem
> /opt/homebrew/include` instead of `-I/opt/homebrew/include` as I
just
> have tested.
Is that option adde
On 3/27/23 20:33, Ninad Palsule wrote:
This is a documentation change for I2C TPM device support.
Qemu already supports devices attached to ISA and sysbus.
This drop adds support for the I2C bus attached TPM devices.
Signed-off-by: Ninad Palsule
Reviewed-by: Cédric Le Goater
On 3/27/23 20:33, Ninad Palsule wrote:
Qemu already supports devices attached to ISA and sysbus. This drop adds
support for the I2C bus attached TPM devices.
This commit includes changes for the common code.
- Added support for the new checksum registers which are required for
the I2C support
From: qianfan Zhao
Add documents for Banana Pi M2U
Signed-off-by: qianfan Zhao
---
docs/system/arm/bananapi_m2u.rst | 138 +++
1 file changed, 138 insertions(+)
create mode 100644 docs/system/arm/bananapi_m2u.rst
diff --git a/docs/system/arm/bananapi_m2u.rst b/doc
From: qianfan Zhao
Allwinner R40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU,
and a Mali400 MP2 GPU from ARM. It's also known as the Allwinner T3
for In-Car Entertainment usage, A40i and A40pro are variants that
differ in applicable temperatures range (industrial and military).
This patch
From: qianfan Zhao
Add documents for Banana Pi M2U
Signed-off-by: qianfan Zhao
---
docs/system/arm/bananapi_m2u.rst | 138 +++
1 file changed, 138 insertions(+)
create mode 100644 docs/system/arm/bananapi_m2u.rst
diff --git a/docs/system/arm/bananapi_m2u.rst b/doc
From: qianfan Zhao
R40 has SAMP_DL_REG register and mmc2 controller has only 8K dma buffer.
Fix it's compatible string.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinner-r40.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/allwinner-r40.c b/hw/arm/allwinner-r40.c
ind
From: qianfan Zhao
This patch adds minimal support for AXP-221 PMU and connect it to
bananapi M2U board.
Signed-off-by: qianfan Zhao
---
hw/arm/Kconfig| 3 +-
hw/arm/bananapi_m2u.c | 6 +
hw/misc/Kconfig | 2 +-
hw/misc/axp209.c | 238 --
From: qianfan Zhao
Add test case for booting from initrd and sd card.
Signed-off-by: qianfan Zhao
---
tests/avocado/boot_linux_console.py | 176
1 file changed, 176 insertions(+)
diff --git a/tests/avocado/boot_linux_console.py
b/tests/avocado/boot_linux_console.
From: qianfan Zhao
Types of memory that the SDRAM controller supports are DDR2/DDR3
and capacities of up to 2GiB. This commit adds emulation support
of the Allwinner R40 SDRAM controller.
This driver only support 256M, 512M and 1024M memory now.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinne
From: qianfan Zhao
R40 has two ethernet controllers named as emac and gmac. The emac is
compatibled with A10, and the GMAC is compatibled with H3.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinner-r40.c | 50 --
hw/arm/bananapi_m2u.c | 3 ++
inc
From: qianfan Zhao
*** history ***
# v1: 2023-03-21
The first version which add allwinner-r40 support, supported features:
+ ccu
+ dram controller
+ uart
+ i2c and pmic(axp221)
+ sdcard
+ emac/gmac
Also provide a test case under avocado, running quickly test:
$ AVOCADO_ALLOW_LARGE_STORAGE=ye
From: qianfan Zhao
R40 has eight UARTs, support both 16450 and 16550 compatible modes.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinner-r40.c | 31 ---
include/hw/arm/allwinner-r40.h | 8
2 files changed, 36 insertions(+), 3 deletions(-)
diff --gi
From: qianfan Zhao
TWI(i2c) is designed to be used as an interface between CPU host and the
serial 2-Wire bus. It can support all standard 2-Wire transfer, can be
operated in standard mode(100kbit/s) or fast-mode, supporting data rate
up to 400kbit/s.
Signed-off-by: qianfan Zhao
---
hw/arm/all
From: qianfan Zhao
Only a few important registers are added, especially the SRAM_VER
register.
Signed-off-by: qianfan Zhao
---
hw/arm/Kconfig| 1 +
hw/arm/allwinner-r40.c| 7 +-
hw/misc/Kconfig | 3 +
hw/misc/allwinner-sramc.c | 1
From: qianfan Zhao
A64's sd register was similar to H3, and it introduced a new register
named SAMP_DL_REG location at 0x144. The dma descriptor buffer size of
mmc2 is only 8K and the other mmc controllers has 64K.
Signed-off-by: qianfan Zhao
---
hw/sd/allwinner-sdhost.c | 70 +
From: qianfan Zhao
The CCU provides the registers to program the PLLs and the controls
most of the clock generation, division, distribution, synchronization
and gating.
This commit adds support for the Clock Control Unit which emulates
a simple read/write register interface.
Signed-off-by: qian
在 2023/3/27 14:41, Markus Armbruster 写道:
Hyman Huang writes:
在 2023/3/24 22:32, Markus Armbruster 写道:
Hyman Huang writes:
在 2023/3/24 20:11, Markus Armbruster 写道:
huang...@chinatelecom.cn writes:
From: Hyman Huang(黄勇)
Introduce migration dirty-limit capability, which can
be turned
Paolo Bonzini writes:
> I am honestly not a fan of adding a more complex option,.just because
> query-command-line-options only returns the square holes whereas here we
> got a round one.
>
> Can we imagine another functionality that would be added to -teardown? If
> not, it's not a good design.
From: Sriram Yagnaraman
Use PFRSTD to reset RSTI bit for VFs, and raise VFLRE interrupt when VF
is reset.
Signed-off-by: Sriram Yagnaraman
Signed-off-by: Jason Wang
---
hw/net/igb_core.c | 38 ++
hw/net/igb_regs.h | 3 +++
hw/net/trace-events | 2 ++
From: Sriram Yagnaraman
I would like to review and be informed on changes to igb device
Signed-off-by: Sriram Yagnaraman
Signed-off-by: Jason Wang
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 34b50b2..ef45b5e 100644
--- a/MAINTAINERS
+++
From: Akihiko Odaki
The current implementation of igb uses only part of a advanced Tx
context descriptor and first data descriptor because it misses some
features and sniffs the trait of the packet instead of respecting the
packet type specified in the descriptor. However, we will certainly
need
From: Akihiko Odaki
igb used to specify the PF as DMA requester when reading Tx packets.
This made Tx requests from VFs to be performed on the address space of
the PF, defeating the purpose of SR-IOV. Add some logic to change the
requester depending on the queue, which can be assigned to a VF.
F
From: Sriram Yagnaraman
Also introduce:
- Checks for RXDCTL/TXDCTL queue enable bits
- IGB_NUM_VM_POOLS enum (Sec 1.5: Table 1-7)
Signed-off-by: Sriram Yagnaraman
Signed-off-by: Jason Wang
---
hw/net/igb_core.c | 38 +++---
hw/net/igb_core.h | 1 +
hw/net/igb_
From: Akihiko Odaki
No segmentation should be performed if gso type is
VIRTIO_NET_HDR_GSO_NONE even if ECN bit is set.
Fixes: e263cd49c7 ("Packet abstraction for VMWARE network devices")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1544
Signed-off-by: Akihiko Odaki
Signed-off-by: Jas
From: Sriram Yagnaraman
Signed-off-by: Sriram Yagnaraman
Signed-off-by: Jason Wang
---
hw/net/igb_core.c | 41 -
1 file changed, 36 insertions(+), 5 deletions(-)
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
index 753f17b..38aa459 100644
--- a/hw/n
From: Sriram Yagnaraman
Add support for stripping/inserting VLAN for VFs.
Had to move CSUM calculation back into the for loop, since packet data
is pulled inside the loop based on strip VLAN decision for every VF.
net_rx_pkt_fix_l4_csum should be extended to accept a buffer instead for
igb. Wor
From: Sriram Yagnaraman
Please note that loopback counters for VM to VM traffic is not
implemented yet: VFGOTLBC, VFGPTLBC, VFGORLBC and VFGPRLBC.
Signed-off-by: Sriram Yagnaraman
Signed-off-by: Jason Wang
---
hw/net/igb_core.c | 26 ++
1 file changed, 22 insertions(+)
The following changes since commit e3debd5e7d0ce031356024878a0a18b9d109354a:
Merge tag 'pull-request-2023-03-24' of https://gitlab.com/thuth/qemu into
staging (2023-03-24 16:08:46 +)
are available in the git repository at:
https://github.com/jasowang/qemu.git tags/net-pull-request
for
From: Akihiko Odaki
Align the l3_hdr member of NetTxPkt by defining it as a union of
ip_header, ip6_header, and an array of octets.
Fixes: e263cd49c7 ("Packet abstraction for VMWARE network devices")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1544
Signed-off-by: Akihiko Odaki
Signe
From: Sriram Yagnaraman
RSS for VFs is only enabled if VMOLR[n].RSSE is set.
Signed-off-by: Sriram Yagnaraman
Signed-off-by: Jason Wang
---
hw/net/igb_core.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
index 38aa459..fd61c6
From: Sriram Yagnaraman
IGB uses RXDW ICR bit to indicate that rx descriptor has been written
back. This is the same as RXT0 bit in older HW.
Signed-off-by: Sriram Yagnaraman
Signed-off-by: Jason Wang
---
hw/net/e1000x_regs.h | 4
hw/net/igb_core.c| 2 +-
2 files changed, 5 insertion
On 2023/3/28 11:31, Richard Henderson wrote:
On 3/27/23 18:55, liweiwei wrote:
On 2023/3/28 02:04, Richard Henderson wrote:
On 3/27/23 03:00, Weiwei Li wrote:
@@ -1248,6 +1265,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr
address, int size,
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VAD
Hi,
I create a VM with a virtual pci device "-net nic,model=e1000", and I
attemped to read/write the bar0 of the virtual nic inside the guest
userspace by mmap the "/sys/bus/pci/devices/:xx:xx.x/resource0" to
the userspace.
What I expected is a VMEXIT should occur when I read/write the bar bu
On 2023/3/28 11:18, Richard Henderson wrote:
On 3/27/23 19:48, liweiwei wrote:
On 2023/3/28 10:20, LIU Zhiwei wrote:
On 2023/3/27 18:00, Weiwei Li wrote:
Since pointer mask works on effective address, and the xl works on the
generation of effective address, so xl related calculation should
On 3/27/23 18:55, liweiwei wrote:
On 2023/3/28 02:04, Richard Henderson wrote:
On 3/27/23 03:00, Weiwei Li wrote:
@@ -1248,6 +1265,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
On 2023/3/28 11:18, Richard Henderson wrote:
On 3/27/23 19:48, liweiwei wrote:
On 2023/3/28 10:20, LIU Zhiwei wrote:
On 2023/3/27 18:00, Weiwei Li wrote:
Since pointer mask works on effective address, and the xl works on the
generation of effective address, so xl related calculation should
在 2023/3/28 上午1:44, Richard Henderson 写道:
On 3/27/23 04:23, Tianrui Zhao wrote:
The virt addr should mask TARGET_PHYS_ADDR_SPACE_BITS to
get the phys addr, and this is used by loading kernel elf.
Signed-off-by: Tianrui Zhao
---
hw/loongarch/virt.c | 2 +-
1 file changed, 1 insertion(+), 1
On 3/27/23 19:48, liweiwei wrote:
On 2023/3/28 10:20, LIU Zhiwei wrote:
On 2023/3/27 18:00, Weiwei Li wrote:
Since pointer mask works on effective address, and the xl works on the
generation of effective address, so xl related calculation should be done
before pointer mask.
Incorrect. It ha
On 2023/3/28 10:31, LIU Zhiwei wrote:
On 2023/3/28 9:55, liweiwei wrote:
On 2023/3/28 02:04, Richard Henderson wrote:
On 3/27/23 03:00, Weiwei Li wrote:
@@ -1248,6 +1265,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr
address, int size,
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRI
This patch includes:
- VINSGR2VR.{B/H/W/D};
- VPICKVE2GR.{B/H/W/D}[U];
- VREPLGR2VR.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 33 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 110
target/loongarch/insns.decode
This patch includes:
- VMADD.{B/H/W/D};
- VMSUB.{B/H/W/D};
- VMADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- VMADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 34 ++
target/loongarch/helper.h | 36 ++
target/loongarch
This patch includes:
- VREPLVE[I].{B/H/W/D};
- VBSLL.V, VBSRL.V;
- VPACK{EV/OD}.{B/H/W/D};
- VPICK{EV/OD}.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 35 +
target/loongarch/helper.h | 18 +++
target/loongarch/insn_trans/trans_lsx.c
This patch includes:
- VSAT.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 9 ++
target/loongarch/helper.h | 9 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 105
target/loongarch/insns.decode |
This patch includes:
- VLDI.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 7 +
target/loongarch/insn_trans/trans_lsx.c.inc | 142
target/loongarch/insns.decode | 4 +
3 files changed, 153 insertions(+)
diff --git a/target/loong
This patch includes:
- VCLO.{B/H/W/D};
- VCLZ.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 9 ++
target/loongarch/helper.h | 9 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 9 ++
target/loongarch/insns.decode
Hi,
This series adds LoongArch LSX instructions, Since the LoongArch
Vol2 is not open, So we use 'RFC' title.
About Test:
V2 we use RISU test the LoongArch LSX instructions.
No problems have been found so far.
QEMU:
https://github.com/loongson/qemu/tree/tcg-old-abi-support-lsx
RISU:
http
This patch includes:
- VF{ADD/SUB/MUL/DIV}.{S/D};
- VF{MADD/MSUB/NMADD/NMSUB}.{S/D};
- VF{MAX/MIN}.{S/D};
- VF{MAXA/MINA}.{S/D};
- VFLOGB.{S/D};
- VFCLASS.{S/D};
- VF{SQRT/RECIP/RSQRT}.{S/D}.
Signed-off-by: Song Gao
---
target/loongarch/cpu.h | 4 +
target/loongarch/disas.
This patch includes:
- VHADDW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU};
- VHSUBW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 17
target/loongarch/helper.h | 17
target/loongarch/insn_trans/trans
This patch includes:
- VADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- VSUBW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- VADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 43 +
target/loongarch/helper.h | 45 ++
target/loongarch/ins
This patch includes:
- VADDA.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 5 ++
target/loongarch/helper.h | 5 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 53 +
target/loongarch/insns.decode | 5 +
This patch includes:
- VBITSEL.V;
- VBITSELI.B;
- VSET{EQZ/NEZ}.V;
- VSETANYEQZ.{B/H/W/D};
- VSETALLNEZ.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 20 +++
target/loongarch/helper.h | 13 +
target/loongarch/insn_trans/trans_lsx.c
This patch includes:
- VBITCLR[I].{B/H/W/D};
- VBITSET[I].{B/H/W/D};
- VBITREV[I].{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 25 +
target/loongarch/helper.h | 25 +
target/loongarch/insn_trans/trans_lsx.c.inc | 25 ++
This patch includes:
- VFCVT{L/H}.{S.H/D.S};
- VFCVT.{H.S/S.D};
- VFRINT[{RNE/RZ/RP/RM}].{S/D};
- VFTINT[{RNE/RZ/RP/RM}].{W.S/L.D};
- VFTINT[RZ].{WU.S/LU.D};
- VFTINT[{RNE/RZ/RP/RM}].W.D;
- VFTINT[{RNE/RZ/RP/RM}]{L/H}.L.S;
- VFFINT.{S.W/D.L}[U];
- VFFINT.S.L, VFFINT{L/H}.D.W.
Signed-off-by: Song G
This patch includes:
- VSLLWIL.{H.B/W.H/D.W};
- VSLLWIL.{HU.BU/WU.HU/DU.WU};
- VEXTL.Q.D, VEXTL.QU.DU.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 9 +
target/loongarch/helper.h | 9 +
target/loongarch/insn_trans/trans_lsx.c.inc | 21
This patch includes:
- VMSKLTZ.{B/H/W/D};
- VMSKGEZ.B;
- VMSKNZ.B.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 7 ++
target/loongarch/helper.h | 7 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 7 ++
target/loongarch/insns.decode
This patch includes:
- VSSRLRN.{B.H/H.W/W.D};
- VSSRARN.{B.H/H.W/W.D};
- VSSRLRN.{BU.H/HU.W/WU.D};
- VSSRARN.{BU.H/HU.W/WU.D};
- VSSRLRNI.{B.H/H.W/W.D/D.Q};
- VSSRARNI.{B.H/H.W/W.D/D.Q};
- VSSRLRNI.{BU.H/HU.W/WU.D/DU.Q};
- VSSRARNI.{BU.H/HU.W/WU.D/DU.Q}.
Signed-off-by: Song Gao
---
target/loonga
This patch includes:
- VSADD.{B/H/W/D}[U];
- VSSUB.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 17 +
target/loongarch/insn_trans/trans_lsx.c.inc | 17 +
target/loongarch/insns.decode | 17 +
This patch includes:
- VMAX[I].{B/H/W/D}[U];
- VMIN[I].{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 33 +++
target/loongarch/helper.h | 18 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 211
target/loongarch/i
This patch includes:
- VABSD.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 9 ++
target/loongarch/helper.h | 9 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 95 +
target/loongarch/insns.decode |
This patch includes:
- VEXTH.{H.B/W.H/D.W/Q.D};
- VEXTH.{HU.BU/WU.HU/DU.WU/QU.DU}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 9 ++
target/loongarch/helper.h | 9 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 20
target/l
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 2 ++
target/loongarch/cpu.h | 2 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 11 +++
3 files changed, 15 insertions(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index
This patch includes:
- VFRSTP[I].{B/H}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 5 +++
target/loongarch/helper.h | 5 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 5 +++
target/loongarch/insns.decode | 5 +++
target/loong
This patch includes:
- VSRLR[I].{B/H/W/D};
- VSRAR[I].{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 18
target/loongarch/helper.h | 18
target/loongarch/insn_trans/trans_lsx.c.inc | 18
target/loongarch/insns.decode
This patch includes:
- VSEQ[I].{B/H/W/D};
- VSLE[I].{B/H/W/D}[U];
- VSLT[I].{B/H/W/D/}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 43 +
target/loongarch/helper.h | 23 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 191 +++
This patch includes:
- VMUL.{B/H/W/D};
- VMUH.{B/H/W/D}[U];
- VMULW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- VMULW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 38 ++
target/loongarch/helper.h | 36 ++
target/loongarch/
Signed-off-by: Song Gao
---
target/loongarch/insn_trans/trans_lsx.c.inc | 5 +
target/loongarch/lsx_helper.c | 6 ++
target/loongarch/meson.build| 1 +
target/loongarch/translate.c| 1 +
4 files changed, 13 insertions(+)
create mode 100644 ta
This patch includes:
- VPCNT.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 5
target/loongarch/helper.h | 5
target/loongarch/insn_trans/trans_lsx.c.inc | 5
target/loongarch/insns.decode | 5
target/l
This patch includes:
- V{AND/OR/XOR/NOR/ANDN/ORN}.V;
- V{AND/OR/XOR/NOR}I.B.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 12 +
target/loongarch/helper.h | 2 +
target/loongarch/insn_trans/trans_lsx.c.inc | 50 +
target/loon
This patch includes:
- VSIGNCOV.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 5 ++
target/loongarch/helper.h | 5 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 54 +
target/loongarch/insns.decode |
This patch includes:
- VLD[X], VST[X];
- VLDREPL.{B/H/W/D};
- VSTELM.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 34 +++
target/loongarch/helper.h | 12 +
target/loongarch/insn_trans/trans_lsx.c.inc | 70 +
target/loongarch/insns.
On 2023/3/28 10:14, LIU Zhiwei wrote:
On 2023/3/27 18:00, Weiwei Li wrote:
Currently, the pc use signed-extend(in gen_set_pc*) when xl = 32. And
data address should use the same memory address space with it when
xl = 32. So we should change their address calculation to use sign-extended
addre
This patch includes:
- VADD.{B/H/W/D/Q};
- VSUB.{B/H/W/D/Q}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 23
target/loongarch/helper.h | 4 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 40 +
target/loongarch/i
This patch includes:
- VSLL[I].{B/H/W/D};
- VSRL[I].{B/H/W/D};
- VSRA[I].{B/H/W/D};
- VROTR[I].{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 36 +
target/loongarch/insn_trans/trans_lsx.c.inc | 36 +
target/loongarch/i
Introduce set_fpr() and get_fpr() and remove cpu_fpr.
Signed-off-by: Song Gao
---
.../loongarch/insn_trans/trans_farith.c.inc | 72 +++
target/loongarch/insn_trans/trans_fcmp.c.inc | 12 ++--
.../loongarch/insn_trans/trans_fmemory.c.inc | 37 ++
target/loongarch/insn_
Signed-off-by: Song Gao
---
linux-user/loongarch64/signal.c | 4 ++--
target/loongarch/cpu.c | 2 +-
target/loongarch/cpu.h | 31 +-
target/loongarch/gdbstub.c | 4 ++--
target/loongarch/machine.c | 34 -
5
This patch includes:
- VSSRLN.{B.H/H.W/W.D};
- VSSRAN.{B.H/H.W/W.D};
- VSSRLN.{BU.H/HU.W/WU.D};
- VSSRAN.{BU.H/HU.W/WU.D};
- VSSRLNI.{B.H/H.W/W.D/D.Q};
- VSSRANI.{B.H/H.W/W.D/D.Q};
- VSSRLNI.{BU.H/HU.W/WU.D/DU.Q};
- VSSRANI.{BU.H/HU.W/WU.D/DU.Q}.
Signed-off-by: Song Gao
---
target/loongarch/disa
This patch includes:
- VSRLN.{B.H/H.W/W.D};
- VSRAN.{B.H/H.W/W.D};
- VSRLNI.{B.H/H.W/W.D/D.Q};
- VSRANI.{B.H/H.W/W.D/D.Q}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 16 +++
target/loongarch/helper.h | 16 +++
target/loongarch/insn_trans/trans_l
This patch includes:
- VSRLRN.{B.H/H.W/W.D};
- VSRARN.{B.H/H.W/W.D};
- VSRLRNI.{B.H/H.W/W.D/D.Q};
- VSRARNI.{B.H/H.W/W.D/D.Q}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 16 +++
target/loongarch/helper.h | 16 +++
target/loongarch/insn_trans/tra
This patch includes:
- VILV{L/H}.{B/H/W/D};
- VSHUF.{B/H/W/D};
- VSHUF4I.{B/H/W/D};
- VPERMI.W;
- VEXTRINS.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 25 +++
target/loongarch/helper.h | 25 +++
target/loongarch/insn_trans/trans_lsx.c.
This patch includes:
- VFCMP.cond.{S/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 94 +
target/loongarch/helper.h | 5 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 32 +++
target/loongarch/insns.decode
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 18b41221a6..2263bd4fdd 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -386,6 +386,7 @@ static void loongarch_la464_init
This patch includes:
- VDIV.{B/H/W/D}[U];
- VMOD.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 17 +
target/loongarch/helper.h | 17 +
target/loongarch/insn_trans/trans_lsx.c.inc | 17 +
target/loongarch/insns.de
This patch includes:
- VADDI.{B/H/W/D}U;
- VSUBI.{B/H/W/D}U.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 14
target/loongarch/insn_trans/trans_lsx.c.inc | 37 +
target/loongarch/insns.decode | 11 ++
3 files changed, 62
This patch includes;
- VNEG.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 10 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 20
target/loongarch/insns.decode | 7 +++
3 files changed, 37 insertions(+)
diff
This patch includes:
- VAVG.{B/H/W/D}[U];
- VAVGR.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 17 ++
target/loongarch/helper.h | 18 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 197
target/loongarch/insns.d
On 2023/3/28 10:20, LIU Zhiwei wrote:
On 2023/3/27 18:00, Weiwei Li wrote:
Since pointer mask works on effective address, and the xl works on the
generation of effective address, so xl related calculation should be
done
before pointer mask.
Incorrect. It has been done.
When updating the
On 2023/3/25 18:54, Richard Henderson wrote:
From: Fei Wu
Kernel needs to access user mode memory e.g. during syscalls, the window
is usually opened up for a very limited time through MSTATUS.SUM, the
overhead is too much if tlb_flush() gets called for every SUM change.
This patch creates a
On 2023/3/25 18:54, Richard Henderson wrote:
From: Fei Wu
Currently it's assumed the 2 low bits of mmu_idx map to privilege mode,
this assumption won't last as we are about to add more mmu_idx. Here an
individual priv field is added into TB_FLAGS.
Reviewed-by: Richard Henderson
Signed-off-b
On 2023/3/25 18:54, Richard Henderson wrote:
Merge with mstatus_{fs,vs}. We might perform a redundant
assignment to one or the other field, but it's a trivial
and saves 4 bits from TB_FLAGS.
Signed-off-by: Richard Henderson
Reviewed-by: LIU Zhiwei
Zhiwei
---
target/riscv/cpu.h
On 2023/3/28 9:55, liweiwei wrote:
On 2023/3/28 02:04, Richard Henderson wrote:
On 3/27/23 03:00, Weiwei Li wrote:
@@ -1248,6 +1265,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr
address, int size,
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d
mmu_idx %d\n",
On 2023/3/27 18:00, Weiwei Li wrote:
Sign-extend the vector address when xl = 32.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/vector_helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index
On 2023/3/27 18:00, Weiwei Li wrote:
actual_address = (requested_address & ~mpmmask) | mpmbase.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/vector_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/vector_helper.c b/target/
On 2023/3/27 18:00, Weiwei Li wrote:
Since pointer mask works on effective address, and the xl works on the
generation of effective address, so xl related calculation should be done
before pointer mask.
Incorrect. It has been done.
When updating the pm_mask, we have already considered the e
On 2023/3/27 18:00, Weiwei Li wrote:
Currently, the pc use signed-extend(in gen_set_pc*) when xl = 32. And
data address should use the same memory address space with it when
xl = 32. So we should change their address calculation to use sign-extended
address when xl = 32.
Incorrect. PC sign-ext
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