On 2023/3/21 14:06, Richard Henderson wrote:
On 3/20/23 21:53, LIU Zhiwei wrote:
TS_DEAD means we will release the register allocated for this
temporary. But
at basic block ending, we can still use the allocted register.
Signed-off-by: LIU Zhiwei
Test case?
I have run an Ubuntu image af
From: Fei Wu
Kernel needs to access user mode memory e.g. during syscalls, the window
is usually opened up for a very limited time through MSTATUS.SUM, the
overhead is too much if tlb_flush() gets called for every SUM change.
This patch saves addresses accessed when SUM=1, and flushs only these
p
While it was a reasonable idea to specify no window restricitions at the
outset of the CXL emulation support, it turns out that in practice a
platform will never follow the QEMU example of specifying simultaneous
support for HDM-H and HDM-D[B] in a single window.
HDM-D mandates extra bus cycles fo
On 3/20/23 21:53, LIU Zhiwei wrote:
TS_DEAD means we will release the register allocated for this temporary. But
at basic block ending, we can still use the allocted register.
Signed-off-by: LIU Zhiwei
Test case?
r~
---
tcg/tcg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
d
On 3/20/23 10:14, Alex Bennée wrote:
This should be a tcg hook, not a sysemu hook, per the previous one.
I would very much like it to never be NULL, but instead your new
common_cpu_handle_interrupt function.
I was trying to figure out how to instantiate a default but ran into
const problems eve
On 2023/3/21 12:34, LIU Zhiwei wrote:
Vector implicitly enables zve64d, zve64f, zve32f sub extensions. As vector
only requires PRIV_1_10_0, these sub extensions should not require priv version
higher than that.
The same for Zfh.
Signed-off-by: LIU Zhiwei
LGTM.
Reviewed-by: Weiwei Li
Wei
TS_DEAD means we will release the register allocated for this temporary. But
at basic block ending, we can still use the allocted register.
Signed-off-by: LIU Zhiwei
---
tcg/tcg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index bb52bc060b..0c93e6e6
On 2023/3/19 4:04, Daniel Henrique Barboza wrote:
We're doing env->priv_spec validation and assignment at the start of
riscv_cpu_realize(), which is fine, but then we're doing a force disable
on extensions that aren't compatible with the priv version.
This second step is being done too early.
Vector implicitly enables zve64d, zve64f, zve32f sub extensions. As vector
only requires PRIV_1_10_0, these sub extensions should not require priv version
higher than that.
The same for Zfh.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.c | 8
1 file changed, 4 insertions(+), 4 deleti
On 2023/3/19 04:04, Daniel Henrique Barboza wrote:
set_misa() is setting all 'misa' related env states and nothing else.
But other functions, namely riscv_cpu_validate_set_extensions(), uses
the config object to do its job.
This creates a need to set the single letter extensions in the cfg
obje
On 2023/3/19 04:04, Daniel Henrique Barboza wrote:
Allow write_misa() to enable RVV like we did with RVG. We'll need a
riscv_cpu_enable_v() to enable all related misa bits and Z extensions.
This new helper validates the existing 'env' conf by using the existing
riscv_cpu_validate_v(). We'll als
Hi Erico,
>
> The gd_motion_event size has some calculations for the cursor position,
> which also take into account things like different size of the
> framebuffer compared to the window size.
> The use of window size makes things more difficult though, as at least
> in the case of Wayland inclu
On 2023/3/19 04:04, Daniel Henrique Barboza wrote:
Allow write_misa() to enable RVG by changing riscv_cpu_enable_g()
slighty: instead of returning void, return the current env->misa_ext
value. This is then retrieved by 'val', which will add the RVG flag
itself, and then we'll skip validation an
On Tue, Mar 21, 2023 at 12:20 AM Cindy Lu wrote:
>
> 1. The vIOMMU support will make vDPA can work in IOMMU mode. This
> will fix security issues while using the no-IOMMU mode.
> To support this feature we need to add new functions for IOMMU MR adds and
> deletes.
>
> Also since the SVQ does not s
On Tue, Mar 21, 2023 at 12:20 AM Cindy Lu wrote:
>
> The unmap ioctl doesn't accept a full 64-bit span. So need to
> add check for the section's size in vhost_vdpa_listener_region_del().
>
> Signed-off-by: Cindy Lu
Acked-by: Jason Wang
Thanks
> ---
> hw/virtio/vhost-vdpa.c | 20 +
On 2023/3/19 04:04, Daniel Henrique Barboza wrote:
We can set all RVG related extensions during realize time, before
validate_set_extensions() itself. Put it in a separated function so the
validate function already uses the updated state.
Note that we're adding an extra constraint: ext_zfinx i
On Tue, Mar 21, 2023 at 12:20 AM Cindy Lu wrote:
>
> In trace_vhost_vdpa_listener_region_del, the value for llend
> should change to int128_get64(int128_sub(llend, int128_one()))
>
> Signed-off-by: Cindy Lu
Acked-by: Jason Wang
Thanks
> ---
> hw/virtio/vhost-vdpa.c | 3 ++-
> 1 file changed,
On Tue, Mar 21, 2023 at 12:20 AM Cindy Lu wrote:
>
> To support vIOMMU in vdpa, need to exposed the function
> vhost_dev_has_iommu, vdpa will use this function to check
> if vIOMMU enable.
>
> Signed-off-by: Cindy Lu
Acked-by: Jason Wang
Thanks
> ---
> hw/virtio/vhost.c | 2 +-
> inc
On 2023/3/19 4:04, Daniel Henrique Barboza wrote:
All these generic CPUs are using the latest priv available, at this
moment PRIV_VERSION_1_12_0:
- riscv_any_cpu_init()
- rv32_base_cpu_init()
- rv64_base_cpu_init()
- rv128_base_cpu_init()
Create a new PRIV_VERSION_LATEST enum and use it in th
On 2023/3/19 4:04, Daniel Henrique Barboza wrote:
The setter is doing nothing special. Just set env->priv_ver directly.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 30 +-
1 file changed, 13 insertions(+), 17 deletions(-)
diff --git a/target/
On 2023/3/19 4:04, Daniel Henrique Barboza wrote:
This setter is doing nothing else but setting env->vext_ver. Assign the
value directly.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/target/riscv/cpu
On 2023/3/19 4:04, Daniel Henrique Barboza wrote:
The RVV verification will error out if fails and it's being done at the
end of riscv_cpu_validate_set_extensions(). Let's put it in its own
function and do it earlier.
We'll move it out of riscv_cpu_validate_set_extensions() in the near future,
On Mon, Mar 20, 2023 at 8:20 AM Vladimir Sementsov-Ogievskiy
wrote:
>
> On 20.03.23 13:54, Daniel P. Berrangé wrote:
> > The default message recv limit in asyncio is smaller than our needs, so
> > when opening connections we override it. This was done when opening a
> > connection using a socket a
On Mon, Mar 20, 2023 at 10:14:17PM +, Joe Komlodi wrote:
> Hi all,
>
> This series fixes some I2C state variables not being reset when a reset
> would happen.
>
> These stale variables would infrequently cause issues, something around
> the order of 5/1000 runs, since the machine would have t
Am 20. März 2023 15:47:33 UTC schrieb "Philippe Mathieu-Daudé"
:
>Hi Juan,
>
>On 18/3/23 18:59, Juan Quintela wrote:
>>
>> Hi
>>
>> NOTE, NOTE, NOTE
>>
>> Remember that we are back in that crazy part of the year when daylight
>> saving applies. Call is done on US timezone. If you are anyth
Am 20. März 2023 13:26:24 UTC schrieb marcandre.lur...@redhat.com:
>From: Marc-André Lureau
>
>Do not attempt to move the pointer if the widget is not yet realized.
>The mouse cursor is placed to the corner of the screen, on X11 at least,
>as x_root and y_root are then miscalculated. (this is n
If a reset comes while the SMBus device is not in its idle state, it's
possible for it to get confused on valid transactions post-reset.
Signed-off-by: Joe Komlodi
---
hw/i2c/smbus_slave.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_slave.c
in
It's possible for a reset to come in the middle of a transaction, which
causes the bus to be in an old state when a new transaction comes in.
Signed-off-by: Joe Komlodi
---
hw/i2c/core.c | 25 ++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/hw/i2c/core.c
Hi all,
This series fixes some I2C state variables not being reset when a reset
would happen.
These stale variables would infrequently cause issues, something around
the order of 5/1000 runs, since the machine would have to be reset at a
point where they would be in a state that would cause probl
Makes it more explicit that 16 bit values are being used
Signed-off-by: Titus Rwantare
---
include/qemu/bitops.h | 26 ++
1 file changed, 26 insertions(+)
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index 03213ce952..887b8f8ce8 100644
--- a/include/qemu/bi
This device has the same register layout as the pca9538, but 4 fewer
gpio pins. This commit lowers the number of pins initialised, and reuses
the pca9538 logic.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Hao Wu
Signed-off-by: Titus Rwantare
---
hw/gpio/pca_i2c_gpio.c | 18 +++
This patch series contains a set of i2c GPIO expanders,
with support for 4, 8, and 16 GPIO connections.
The devices are configured as GPIO inputs by default, but can have pins
configured to be inputs with qmp commands.
For example, the following snippet in a board file for a system,
configures a
The PCA6416 is an i2c device with 16 GPIO pins, the PCA9538 has 8 pins.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Hao Wu
Signed-off-by: Titus Rwantare
---
hw/gpio/Kconfig | 5 +
hw/gpio/meson.build | 1 +
hw/gpio/pca_i2c_gpio.c | 392
Signed-off-by: Titus Rwantare
---
hw/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index b5aed4aff5..548c10d7fc 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -406,6 +406,7 @@ config XLNX_VERSAL
config NPCM7XX
bool
+imply I2C_DEVI
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Titus Rwantare
---
hw/i2c/core.c | 8 +---
hw/i2c/trace-events | 2 +-
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
index bed594fe59..896da359f5 100644
--- a/hw/i2c/core.c
+++ b/hw/i2c/co
On 20/03/2023 15:47, Philippe Mathieu-Daudé wrote:
Hi Juan,
On 18/3/23 18:59, Juan Quintela wrote:
Hi
NOTE, NOTE, NOTE
Remember that we are back in that crazy part of the year when daylight
saving applies. Call is done on US timezone. If you are anything else,
just doublecheck that it is
On 17/3/23 16:54, Richard Henderson wrote:
Pass the address of the last byte to be changed, rather than
the first address past the last byte. This avoids overflow
when the last page of the address space is involved.
Properly truncate tb_last to the end of the page; the comment about
tb_end bein
On 17/3/23 16:54, Richard Henderson wrote:
In addition to the rename, change the semantics to be the
last byte of the guest va, rather than the following byte.
This avoids some overflow conditions.
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 11 ++-
linux-user/
On 17/3/23 16:54, Richard Henderson wrote:
We have been enforcing host page alignment for the non-R
fallback of MAX_RESERVED_VA, but failing to enforce for -R.
Signed-off-by: Richard Henderson
---
linux-user/main.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/linux-user/main.c b
On Mon, Mar 20, 2023 at 2:41 PM Bernhard Beschow wrote:
>
>
>
> Am 20. März 2023 00:05:54 UTC schrieb Jason Andryuk :
> >PCI passthrough for an HVM with a stubdom is PV PCI passthrough from
> >dom0 to the stubdom, and then QEMU passthrough of the PCI device inside
> >the stubdom. xen-pciback has
Hi Eric,
On Mon, Mar 20, 2023 at 05:51:07PM +0100, Eric Auger wrote:
> Hi Mostafa,
>
> On 2/26/23 23:06, Mostafa Saleh wrote:
> > CMD_TLBI_S2_IPA: As S1+S2 is not enabled, for now this can be the
> > same as CMD_TLBI_NH_VAA.
> >
> > CMD_TLBI_S12_VMALL: Added new function to invalidate TLB by VMID
Hi Gerd,
On Thu, 16 Mar 2023 at 04:49, Gerd Hoffmann wrote:
>
> Hi,
>
> > The README should mention that you need to use
> >
> > . edk2setup.sh
> >
> > first.
>
> The script will do that if needed.
>
> > Also you need to be in the edk2 directory, I think.
>
> Or use the --core switch, or place
Hi Eric,
On Mon, Mar 20, 2023 at 05:05:31PM +0100, Eric Auger wrote:
> > +/*
> > + * TLB lookup looks for granule and input size for a translation stage,
> > + * as only one stage is supported right now, choose the right values
> > + * from the configuration.
> > + */
> > +
On Thu, Feb 16, 2023 at 03:21:21PM +0530, Nikunj A. Dadhania wrote:
>
> > +static struct file *restrictedmem_file_create(struct file *memfd)
> > +{
> > + struct restrictedmem_data *data;
> > + struct address_space *mapping;
> > + struct inode *inode;
> > + struct file *file;
> > +
> > +
Hi Eric,
On Mon, Mar 20, 2023 at 04:14:48PM +0100, Eric Auger wrote:
> Hi Mostafa,
>
> On 2/26/23 23:06, Mostafa Saleh wrote:
> > Parse stage-2 configuration from STE and populate it in SMMUS2Cfg.
> > Validity of these value are checked when possible.
> s/these value/field values
Will do.
> >
>
Hi Eric,
On Mon, Mar 20, 2023 at 03:56:26PM +0100, Eric Auger wrote:
> Hi Mostafa,
>
> On 2/26/23 23:06, Mostafa Saleh wrote:
> > In preparation for adding stage-2 support, add Stage-2 PTW code.
> > Only Aarch64 format is supported as stage-1.
> >
> > Nesting stage-1 and stage-2 is not supported
Am 20. März 2023 00:05:54 UTC schrieb Jason Andryuk :
>PCI passthrough for an HVM with a stubdom is PV PCI passthrough from
>dom0 to the stubdom, and then QEMU passthrough of the PCI device inside
>the stubdom. xen-pciback has boolean module param passthrough which
>controls "how to export PCI
Thanks a lot. It's working fine 😁 now.
Abhishek.
On Sun, 19 Mar, 2023, 11:27 pm Cédric Le Goater, wrote:
> Hello Abhishek,
>
> On 3/18/23 18:55, Abhishek Singh Dagur wrote:
> > Hi Alex , Cédric,
> > we have tried this *option:-serial *pty* -serial *pty* -serial *pty
> *-serial *pty *-serial *pt
On Mon, 20 Mar 2023 at 13:03, Thomas Huth wrote:
>
> Hi Peter!
>
> The following changes since commit 74c581b6452394e591f13beba9fea2ec0688e2f5:
>
> Merge tag 'trivial-branch-for-8.0-pull-request' of
> https://gitlab.com/laurent_vivier/qemu into staging (2023-03-17 14:22:01
> +)
>
> are av
+)
>
> are available in the Git repository at:
>
> https://gitlab.com/kraxel/qemu.git
> tags/edk2-stable202302-20230320-pull-request
>
> for you to fetch changes up to 86305e864191123dcf87c3af639fddfc59352ac6:
>
> ed
Emilio Cota writes:
> On Fri, Mar 10, 2023 at 11:52:45 -0800, Richard Henderson wrote:
>> Changes for v2:
> (snip)
>> Richard Henderson (7):
>> tcg: Clear plugin_mem_cbs on TB exit
>> tcg: Drop plugin_gen_disable_mem_helpers from tcg_gen_exit_tb
>> include/qemu/plugin: Remove QEMU_PLUGIN_
Claudio Fontana writes:
> Hi Alex, all,
>
> again, this moves TCG-only code to common code, no?
>
> Even if this happens to work, the idea is to avoid adding unneeded accel TCG
> code to a KVM-only binary.
>
> We need to keep in mind all dimensions when we do refactorings:
>
> user-mode vs sys
Philippe Mathieu-Daudé writes:
> On 20/3/23 11:10, Alex Bennée wrote:
>> We don't want to be polluting the core run loop code with target
>> specific handling, punt it to sysemu_ops where it belongs.
>> Signed-off-by: Alex Bennée
>> ---
>> include/hw/core/sysemu-cpu-ops.h | 5 +
>> tar
Richard Henderson writes:
> On 3/20/23 03:10, Alex Bennée wrote:
>> Signed-off-by: Alex Bennée
>> ---
>> include/hw/core/sysemu-cpu-ops.h | 11 +++
>> target/i386/cpu-internal.h | 1 +
>> accel/tcg/cpu-exec-softmmu.c | 16
>> accel/tcg/cpu-exec.c
Philippe Mathieu-Daudé writes:
> On 18/3/23 12:46, Alex Bennée wrote:
>> A couple of clean-ups here:
>>- inherit from the custom runners job for artefacts
>
> "artifacts"
>
>>- call check-avocado directly
>>- add some comments to the top about setup
>> Signed-off-by: Alex Bennée
>>
Hi Mostafa,
On 2/26/23 23:06, Mostafa Saleh wrote:
> OAS used to be hardcoded to 44 bits, however according to SMMU manual
> 6.3.6 SMMU_IDR5, OAS must match the system physical address size, so
> we read it from CPU PARANGE.
>
> Remove PA_MAX and pa_range as they were not used.
>
> Add SMMUv3State
Hi,
On 2/26/23 23:06, Mostafa Saleh wrote:
> In smmuv3_notify_iova, read the granule based on translation stage
> and use VMID if valid value is sent.
>
> Signed-off-by: Mostafa Saleh
> ---
> hw/arm/smmuv3.c | 39 ++-
> hw/arm/trace-events | 2 +-
> 2 fil
On Wed, Mar 08, 2023 at 12:33:38AM +0100, Philippe Mathieu-Daudé wrote:
> On 23/2/23 17:19, Jiaxun Yang wrote:
> > 145e2198d749 ("hw/mips/gt64xxx_pci: Endian-swap using PCI_HOST_BRIDGE
> > MemoryRegionOps") converted CFGADDR/CFGDATA registers to use
> > PCI_HOST_BRIDGE's
> > accessor facility and
Hi Mostafa,
On 2/26/23 23:06, Mostafa Saleh wrote:
> CMD_TLBI_S2_IPA: As S1+S2 is not enabled, for now this can be the
> same as CMD_TLBI_NH_VAA.
>
> CMD_TLBI_S12_VMALL: Added new function to invalidate TLB by VMID.
>
> For stage-1 only commands, add a check to to throw CERROR_ILL if used
s/to to/
On 3/20/23 03:10, Alex Bennée wrote:
Signed-off-by: Alex Bennée
---
accel/tcg/cpu-exec.c | 4
1 file changed, 4 deletions(-)
Reviewed-by: Richard Henderson
r~
On 3/20/23 03:10, Alex Bennée wrote:
Although only I386 currently uses it it is not inconceivable that
other arches might find this facility useful.
Signed-off-by: Alex Bennée
---
include/hw/core/tcg-cpu-ops.h | 5 +
accel/tcg/cpu-exec.c | 29 +
targ
On 3/20/23 03:10, Alex Bennée wrote:
Signed-off-by: Alex Bennée
---
include/hw/core/sysemu-cpu-ops.h | 11 +++
target/i386/cpu-internal.h | 1 +
accel/tcg/cpu-exec-softmmu.c | 16
accel/tcg/cpu-exec.c | 31 ++-
tar
On 3/20/23 03:10, Alex Bennée wrote:
This avoids us having to make sure each exit path does an unlock.
Signed-off-by: Alex Bennée
---
accel/tcg/cpu-exec.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
Reviewed-by: Richard Henderson
r~
On Mon, 20 Mar 2023 17:05:07 +0100
Markus Armbruster wrote:
> Thomas Huth writes:
>
> > On 20/03/2023 16.31, Markus Armbruster wrote:
> >> Claudio Imbrenda writes:
> >>
> >>> The recently introduced -async-teardown commandline option was not
> >>> wired up properly and did not show up in
On 3/20/23 03:10, Alex Bennée wrote:
These are common across all versions of the system so it would help if
we could use them for common code.
Signed-off-by: Alex Bennée
---
include/exec/cpu-all.h | 52 +-
include/exec/cpu-irq.h | 83 +++
To support vIOMMU in vdpa, need to exposed the function
vhost_dev_has_iommu, vdpa will use this function to check
if vIOMMU enable.
Signed-off-by: Cindy Lu
---
hw/virtio/vhost.c | 2 +-
include/hw/virtio/vhost.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/virt
In trace_vhost_vdpa_listener_region_del, the value for llend
should change to int128_get64(int128_sub(llend, int128_one()))
Signed-off-by: Cindy Lu
---
hw/virtio/vhost-vdpa.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio/vhost-vdpa.c
ind
1. The vIOMMU support will make vDPA can work in IOMMU mode. This
will fix security issues while using the no-IOMMU mode.
To support this feature we need to add new functions for IOMMU MR adds and
deletes.
Also since the SVQ does not support vIOMMU yet, add the check for IOMMU
in vhost_vdpa_dev_st
These patches are to support vIOMMU in vdpa device
changes in V3
1. Move function vfio_get_xlat_addr to memory.c
2. Use the existing memory listener, while the MR is
iommu MR then call the function iommu_region_add/
iommu_region_del
changes in V4
1.make the comments in vfio_get_xlat_addr more gen
The unmap ioctl doesn't accept a full 64-bit span. So need to
add check for the section's size in vhost_vdpa_listener_region_del().
Signed-off-by: Cindy Lu
---
hw/virtio/vhost-vdpa.c | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/vhost-vdpa.c b
On 3/20/23 03:10, Alex Bennée wrote:
At the cost of an empty tcg_ops field for most targets we can avoid
target specific hacks in cpu-exec.c
Signed-off-by: Alex Bennée
---
include/hw/core/tcg-cpu-ops.h | 2 +-
accel/tcg/cpu-exec.c | 14 +++---
2 files changed, 8 insertions(
On 3/20/23 03:10, Alex Bennée wrote:
+int flags = CPU_DUMP_CCOP;;
Actually, since you can't turn it off, we should just remove it and the test in
i386.
r~
Hi Mostafa,
On 2/26/23 23:06, Mostafa Saleh wrote:
> Allow TLB to be tagged with VMID.
s/tlb/TLB in the commit msg.
>
> If stage-1 is only supported, VMID is set to -1 and ignored from STE
> and CMD_TLBI_NH* cmds.
>
> Update smmu_iotlb_insert trace event to have vmid.
>
> Signed-off-by: Mostafa S
On 3/20/23 03:10, Alex Bennée wrote:
+int flags = CPU_DUMP_CCOP;;
two ;
Reviewed-by: Richard Henderson
r~
On 3/20/23 07:33, Alex Bennée wrote:
Claudio Fontana writes:
On 3/20/23 14:32, Alex Bennée wrote:
Claudio Fontana writes:
How is this conditional on CONFIG_TCG? To me it looks like this breaks
!CONFIG_TCG.
Careful, the meson.build in accel/tcg/meson.build is always recursed.
Surely it
vc->gfx.w and vc->gfx.h are not updated appropriately in this code path,
which leads to a different scaling factor for rendering the cursor on
some edge cases (e.g. the focus has left and re-entered the gtk window).
This can be reproduced using vhost-user-gpu with the gtk ui on the x11
backend.
Use
The gd_motion_event size has some calculations for the cursor position,
which also take into account things like different size of the
framebuffer compared to the window size.
The use of window size makes things more difficult though, as at least
in the case of Wayland includes the size of ui eleme
Hi Mostafa,
On 2/26/23 23:06, Mostafa Saleh wrote:
> Right now, either stage-1 or stage-2 are supported, this simplifies
> how we can deal with TLBs.
> This patch makes TLB lookup work if stage-2 is enabled instead of
> stage-1.
> TLB lookup is done before a PTW, if a valid entry is found we won't
Thomas Huth writes:
> On 20/03/2023 16.31, Markus Armbruster wrote:
>> Claudio Imbrenda writes:
>>
>>> The recently introduced -async-teardown commandline option was not
>>> wired up properly and did not show up in the output of the QMP command
>>> query-command-line-options. This means that li
On 20/3/23 16:56, Philippe Mathieu-Daudé wrote:
On 20/3/23 16:26, Philippe Mathieu-Daudé wrote:
Introduce the BdrvDmgUncompressFunc type defintion. To emphasis
dmg_uncompress_bz2 and dmg_uncompress_lzfse are pointer to functions,
declare them using this new typedef.
Signed-off-by: Philippe Math
On 20/3/23 16:26, Philippe Mathieu-Daudé wrote:
Introduce the BdrvDmgUncompressFunc type defintion. To emphasis
Typo "definition".
dmg_uncompress_bz2 and dmg_uncompress_lzfse are pointer to functions,
declare them using this new typedef.
Signed-off-by: Philippe Mathieu-Daudé
---
block/dmg
On 20/3/23 16:26, Philippe Mathieu-Daudé wrote:
Introduce the BdrvDmgUncompressFunc type defintion. To emphasis
dmg_uncompress_bz2 and dmg_uncompress_lzfse are pointer to functions,
declare them using this new typedef.
Signed-off-by: Philippe Mathieu-Daudé
---
block/dmg.h | 8
block
Hi Juan,
On 18/3/23 18:59, Juan Quintela wrote:
Hi
NOTE, NOTE, NOTE
Remember that we are back in that crazy part of the year when daylight
saving applies. Call is done on US timezone. If you are anything else,
just doublecheck that it is working for you properly.
NOTE, NOTE, NOTE
Topics i
On 20/03/2023 16.31, Markus Armbruster wrote:
Claudio Imbrenda writes:
The recently introduced -async-teardown commandline option was not
wired up properly and did not show up in the output of the QMP command
query-command-line-options. This means that libvirt will have no way to
discover whet
On Mon, 20 Mar 2023 11:03:40 +0100
Cédric Le Goater wrote:
> On 3/20/23 08:35, Minwoo Im wrote:
> > VF token was introduced [1] to kernel vfio-pci along with SR-IOV
> > support [2]. This patch adds support VF token among PF and VF(s). To
> > passthu PCIe VF to a VM, kernel >= v5.7 needs this.
>
On 20/03/2023 16.27, Philippe Mathieu-Daudé wrote:
On 20/3/23 16:10, Peter Maydell wrote:
On Mon, 20 Mar 2023 at 14:02, Thomas Huth wrote:
On 20/03/2023 14.03, Thomas Huth wrote:
Hi Peter!
The following changes since commit
74c581b6452394e591f13beba9fea2ec0688e2f5:
Merge tag 'triv
On Mon, Mar 20, 2023 at 04:05:01PM +0100, Philippe Mathieu-Daudé wrote:
> Hi Emilio,
>
> On 19/3/23 15:15, Emilio Cota wrote:
> > Ping. Any feedback on these two patches?
> >
> > https://patchew.org/QEMU/20230205163758.416992-1-c...@braap.org/
> > https://lore.kernel.org/qemu-devel/20230205163758
On 20/3/23 16:23, Claudio Fontana wrote:
Hi Alex, all,
again, this moves TCG-only code to common code, no?
Oh, good point.
Even if this happens to work, the idea is to avoid adding unneeded accel TCG
code to a KVM-only binary.
Could yet another AccelSysemuCPUOps *accel struct in SysemuCPU
Claudio Imbrenda writes:
> The recently introduced -async-teardown commandline option was not
> wired up properly and did not show up in the output of the QMP command
> query-command-line-options. This means that libvirt will have no way to
> discover whether the feature is supported.
There was
On 20/3/23 16:10, Peter Maydell wrote:
On Mon, 20 Mar 2023 at 14:02, Thomas Huth wrote:
On 20/03/2023 14.03, Thomas Huth wrote:
Hi Peter!
The following changes since commit 74c581b6452394e591f13beba9fea2ec0688e2f5:
Merge tag 'trivial-branch-for-8.0-pull-request' of
https://gitlab.co
Introduce the BdrvDmgUncompressFunc type defintion. To emphasis
dmg_uncompress_bz2 and dmg_uncompress_lzfse are pointer to functions,
declare them using this new typedef.
Signed-off-by: Philippe Mathieu-Daudé
---
block/dmg.h | 8
block/dmg.c | 7 ++-
2 files changed, 6 insertions(+)
Signed-off-by: Klaus Ripke
hw/usb/dev-smartcard-reader.c:
add option for a multislot usb ccid device, similar to audio multi.
(v2 with slight formatting fix on " + ")
---
hw/usb/dev-smartcard-reader.c | 106 +-
1 file changed, 103 insertions(+), 3 deletions(-)
Hi Alex, all,
again, this moves TCG-only code to common code, no?
Even if this happens to work, the idea is to avoid adding unneeded accel TCG
code to a KVM-only binary.
We need to keep in mind all dimensions when we do refactorings:
user-mode vs sysemu,
the architecture,
the accel, in particu
Hi Mostafa,
On 2/26/23 23:06, Mostafa Saleh wrote:
> Parse stage-2 configuration from STE and populate it in SMMUS2Cfg.
> Validity of these value are checked when possible.
s/these value/field values
>
> Only AA64 tables are supported and STT is not supported.
Small Translation Tables (STT)
>
> Ac
On Mon, 20 Mar 2023 at 14:02, Thomas Huth wrote:
>
> On 20/03/2023 14.03, Thomas Huth wrote:
> > Hi Peter!
> >
> > The following changes since commit 74c581b6452394e591f13beba9fea2ec0688e2f5:
> >
> >Merge tag 'trivial-branch-for-8.0-pull-request' of
> > https://gitlab.com/laurent_vivier/qem
Hi Emilio,
On 19/3/23 15:15, Emilio Cota wrote:
Ping. Any feedback on these two patches?
https://patchew.org/QEMU/20230205163758.416992-1-c...@braap.org/
https://lore.kernel.org/qemu-devel/20230205163758.416992-1-c...@braap.org/
Happy to resend if needed.
Since we are past hard-freeze, this
On 20/3/23 15:56, Daniel P. Berrangé wrote:
On Mon, Mar 20, 2023 at 03:43:07PM +0100, Philippe Mathieu-Daudé wrote:
On 20/3/23 15:15, Daniel P. Berrangé wrote:
On Mon, Mar 20, 2023 at 01:42:46PM +, Peter Maydell wrote:
On Sat, 18 Mar 2023 at 11:46, Alex Bennée wrote:
The following chang
On 20/3/23 11:10, Alex Bennée wrote:
Although only I386 currently uses it it is not inconceivable that
other arches might find this facility useful.
Signed-off-by: Alex Bennée
---
include/hw/core/tcg-cpu-ops.h | 5 +
accel/tcg/cpu-exec.c | 29 +
tar
Hi Mostafa,
On 2/26/23 23:06, Mostafa Saleh wrote:
> In preparation for adding stage-2 support, add Stage-2 PTW code.
> Only Aarch64 format is supported as stage-1.
>
> Nesting stage-1 and stage-2 is not supported right now.
>
> HTTU is not supported, SW is expected to maintain the Access flag.
>
On Mon, Mar 20, 2023 at 03:43:07PM +0100, Philippe Mathieu-Daudé wrote:
> On 20/3/23 15:15, Daniel P. Berrangé wrote:
> > On Mon, Mar 20, 2023 at 01:42:46PM +, Peter Maydell wrote:
> > > On Sat, 18 Mar 2023 at 11:46, Alex Bennée wrote:
> > > >
> > > > The following changes since commit
> > >
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