On 06/03/2023 22:14, BALATON Zoltan wrote:
Can you explain a bit more about how the PCI interrupt lines are connected to both
the MV64361 and VT8231? The reason for asking is that I see a similar pattern in
the bonito board, but there I can't see how those lines would be used because they
can
Am 6. März 2023 12:33:31 UTC schrieb BALATON Zoltan :
>The real VIA south bridges implement a PCI IRQ router which is configured
>by the BIOS or the OS. In order to respect these configurations, QEMU
>needs to implement it as well. The real chip may allow routing IRQs from
>internal functions in
On 06/03/2023 22:00, BALATON Zoltan wrote:
On Mon, 6 Mar 2023, Mark Cave-Ayland wrote:
On 06/03/2023 12:33, BALATON Zoltan wrote:
According to the PegasosII schematics the PCI interrupt lines are
connected to both the gpp pins of the Mv64361 north bridge and the
PINT pins of the VT8231 south b
Hello guys. I would be really appreciate if you look this patch.It would be nice to merge it to new release 8.0 27.02.2023, 12:02, "Ivan Klokov" :The decoding of the slli_uw currently contains decodingerror: shamt part of opcode has six bits, not five.Fixes 3de1fb71("target/riscv: update disas.c fo
From: Akihiko Odaki
They will be useful for igb testing.
Signed-off-by: Akihiko Odaki
Reviewed-by: Thomas Huth
Signed-off-by: Jason Wang
---
tests/qtest/libqos/e1000e.c | 12
tests/qtest/libqos/e1000e.h | 12
2 files changed, 12 insertions(+), 12 deletions(-)
diff
From: Philippe Mathieu-Daudé
'has_extended_tcb_support' is accessed read-only and is present
in the class definition. No need to duplicate it in the instance
state. Directly access the class field.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Jason Wang
---
hw/net/eepro100.c | 6 +++--
From: Akihiko Odaki
e1000e understands ethernet header so fabricate something convincing.
Signed-off-by: Akihiko Odaki
Reviewed-by: Thomas Huth
Signed-off-by: Jason Wang
---
tests/qtest/e1000e-test.c | 25 +++--
tests/qtest/libqos/e1000e.h | 2 ++
2 files changed, 17 i
From: Philippe Mathieu-Daudé
'device' is accessed read-only and is present in the class
definition. No need to duplicate it in the instance state.
Directly access the class field.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Jason Wang
---
hw/net/eepro100.c | 12 ++--
1 file c
From: Philippe Mathieu-Daudé
Have all the EEPRO100-based devices share a common (abstract)
QOM parent.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Jason Wang
---
hw/net/eepro100.c | 60 ++-
1 file changed, 42 insertions(+), 18 delet
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Jason Wang
---
hw/net/eepro100.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/hw/net/eepro100.c b/hw/net/eepro100.c
index 4b5d455..722fb55 100644
--- a/hw/net/eepro100.c
+++ b/h
From: Philippe Mathieu-Daudé
If pci_add_capability() ever fail, the EEPRO100 device is broken,
which is a bug. No need to report that to the user, abort instead.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Jason Wang
---
hw/net/eepro100.c | 9 ++---
1 file changed, 2 insertions(+
From: Akihiko Odaki
Before this change, e1000e_write_packet_to_guest() allocated the
receive descriptor buffer as an array of uint8_t. This does not ensure
the buffer is sufficiently aligned.
Introduce e1000_rx_desc_union type, a union type of all receive
descriptor types to correct this.
Signe
From: Akihiko Odaki
Whether a packet will be written back to the guest depends on the
remaining space of the queue. Therefore, e1000e_rx_written_to_guest and
e1000e_rx_not_written_to_guest should log the index of the queue instead
of generated interrupts. This also removes the need of
e1000e_rx_r
From: Akihiko Odaki
The datasheet 8.19.29 "Good Packets Transmitted Count - GPTC (0x04080;
RC)" says:
> This register counts the number of good (no errors) packets
> transmitted. A good transmit packet is considered one that is 64 or
> more bytes in length (from through ,
> inclusively) in lengt
From: Akihiko Odaki
The values returned by eth_get_protocols() are used to perform RSS,
checksumming and segmentation. Even when a packet signals the use of the
protocols which these operations can be applied to, the headers for them
may not be present because of too short packet or fragmentation
From: Akihiko Odaki
igb can use this function to change its behavior depending on the
number of virtual functions currently enabled.
Signed-off-by: Gal Hammer
Signed-off-by: Marcel Apfelbaum
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Jason Wang
---
hw/p
From: Akihiko Odaki
They are duplicate of running throttling timer flags and incomplete as
the flags are not cleared when the interrupts are fired or the device is
reset.
Signed-off-by: Akihiko Odaki
Signed-off-by: Jason Wang
---
hw/net/e1000e.c | 5 ++---
hw/net/e1000e_core.c | 19 +++-
From: Akihiko Odaki
e1000e didn't perform software segmentation for loopback if virtio-net
header is enabled, which is wrong.
To fix the problem, introduce net_tx_pkt_send_custom(), which allows the
caller to specify whether offloading should be assumed or not.
net_tx_pkt_send_custom() also all
From: Akihiko Odaki
Check the payload length if checksumming to ensure the payload contains
the space for the resulting value.
This bug was found by Alexander Bulekov with the fuzzer:
https://patchew.org/QEMU/20230129053316.1071513-1-alx...@bu.edu/
The fixed test case is:
fuzz/crash_6aeaa33e721
From: Akihiko Odaki
Signed-off-by: Akihiko Odaki
Reviewed-by: Cédric Le Goater
Signed-off-by: Jason Wang
---
MAINTAINERS | 1 +
docs/system/device-emulation.rst | 1 +
docs/system/devices/igb.rst | 71
3 files changed, 73 in
From: Akihiko Odaki
The Software Developer's Manual 13.7.4.5 "Packets Transmitted (64 Bytes)
Count" says:
> This register counts the number of packets transmitted that are
> exactly 64 bytes (from through ,
> inclusively) in length.
It also says similar for the other Tx statistics registers. Ad
From: Philippe Mathieu-Daudé
Use the EEPRO100() QOM type-checking macro to avoid DO_UPCAST().
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Jason Wang
---
hw/net/eepro100.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/net/eepro100.c b/hw/net/eepro100.c
i
From: Akihiko Odaki
This change is derived from qtest for e1000e device.
Signed-off-by: Akihiko Odaki
Acked-by: Thomas Huth
Signed-off-by: Jason Wang
---
MAINTAINERS | 2 +
tests/qtest/fuzz/generic_fuzz_configs.h | 5 +
tests/qtest/igb-test.c
From: Akihiko Odaki
When virtio-net header is not set, net_rx_pkt_get_vhdr() returns
zero-filled virtio_net_hdr, which is actually valid. In fact, tap device
uses zero-filled virtio_net_hdr when virtio-net header is not provided
by the peer. Therefore, we can just remove net_rx_pkt_has_virt_hdr()
From: Akihiko Odaki
Assertions will fail if MSI-X gets disabled while a timer for MSI-X
interrupts is running so remove them to avoid abortions. Fortunately,
nothing bad happens even if the assertions won't trigger as
msix_notify(), called by timer handlers, does nothing when MSI-X is
disabled.
From: Shreesh Adiga <16567adigashre...@gmail.com>
The current implementation fails to load on a system with
libbpf 1.0 and reports that legacy map definitions in 'maps'
section are not supported by libbpf v1.0+. This commit updates
the Makefile to add BTF (-g flag) and appropriately updates
the ma
From: Akihiko Odaki
The new function qemu_get_using_vnet_hdr() allows to automatically
determine if virtio-net header is used.
Signed-off-by: Akihiko Odaki
Signed-off-by: Jason Wang
---
hw/net/e1000e_core.c | 3 +--
hw/net/net_tx_pkt.c | 19 ++-
hw/net/net_tx_pkt.h | 3 +--
From: Akihiko Odaki
igb implementation first starts off by copying e1000e code. Correct the
code style before that.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Jason Wang
---
hw/net/e1000.c | 41 ++--
hw/net/e1000e.c| 72 +
From: Akihiko Odaki
Signed-off-by: Akihiko Odaki
Acked-by: Thomas Huth
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Jason Wang
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d263e52..35682ca 100644
--- a/MAINTAINERS
+++ b/MAINTAINE
From: Akihiko Odaki
igb, a new network device emulation, will need SCTP checksum offloading.
Currently eth_get_protocols() has a bool parameter for each protocol
currently it supports, but there will be a bit too many parameters if
we add yet another protocol.
Introduce an enum type, EthL4HdrPro
From: Akihiko Odaki
The system clock is necessary to implement PTP features. While we are
not implementing PTP features for e1000e yet, we do have a plan to
implement them for igb, a new network device derived from e1000e,
so add system clock to the common base first.
Signed-off-by: Akihiko Odak
From: Akihiko Odaki
This is part of recent efforts of refactoring e1000 and e1000e.
DeviceClass's reset member is deprecated so migrate to ResettableClass.
There is no behavioral difference.
Signed-off-by: Akihiko Odaki
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-of
From: Akihiko Odaki
This automates ethtool tests for igb registers, interrupts, etc.
Signed-off-by: Akihiko Odaki
Reviewed-by: Cédric Le Goater
Signed-off-by: Jason Wang
---
MAINTAINERS| 1 +
scripts/ci/org.centos/stream/8/x86_64/test-avocado | 1 +
From: Akihiko Odaki
When a register has effective bits fewer than their width, the old code
inconsistently masked when writing or reading. Make the code consistent
by always masking when writing, and remove some code duplication.
Signed-off-by: Akihiko Odaki
Signed-off-by: Jason Wang
---
hw/n
From: Akihiko Odaki
e1000x_is_vlan_packet() had a pointer to uint8_t as a parameter, but
it does not have to be uint8_t. Change the type to void *.
Signed-off-by: Akihiko Odaki
Signed-off-by: Jason Wang
---
hw/net/e1000x_common.c | 2 +-
hw/net/e1000x_common.h | 2 +-
2 files changed, 2 inser
From: Akihiko Odaki
e1000e_set_16bit and e1000e_set_12bit look so similar so define a
generic macro.
Signed-off-by: Akihiko Odaki
Signed-off-by: Jason Wang
---
hw/net/e1000e_core.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/hw/net/e1000e_core.c b/h
From: Akihiko Odaki
Use memcpy instead of memmove to initialize registers. The initial
register templates and register table instances will never overlap.
Signed-off-by: Akihiko Odaki
Signed-off-by: Jason Wang
---
hw/net/e1000.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
From: Akihiko Odaki
This keeps Windows driver 12.18.9.23 from generating an event with ID
30. The description of the event is as follows:
> Intel(R) 82574L Gigabit Network Connection
> PROBLEM: The network adapter is configured for auto-negotiation but
> the link partner is not. This may result
From: Philippe Mathieu-Daudé
QOM already provides the TypeInfo::class_data to set
class-specific data. Use it instead of reinventing the
wheel with eepro100_get_class_by_name(). This finishes
the QDev conversion started 12 years ago in commit
40021f0888 ("pci: convert to QEMU Object Model").
Sig
From: Akihiko Odaki
The definitions for E1000_VFTA_ENTRY_SHIFT, E1000_VFTA_ENTRY_MASK, and
E1000_VFTA_ENTRY_BIT_SHIFT_MASK were copied from:
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/net/ethernet/intel/e1000/e1000_hw.h?h=v6.0.9#n306
The definitions for E1000_N
From: Akihiko Odaki
The definitions will be used by igb.
Signed-off-by: Akihiko Odaki
Signed-off-by: Jason Wang
---
include/hw/net/mii.h | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h
index 4ae4dcc..c6a767a 100644
From: Akihiko Odaki
The definitions of SW Semaphore Register were copied from:
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/net/ethernet/intel/e1000e/defines.h?h=v6.0.9#n374
Signed-off-by: Akihiko Odaki
Signed-off-by: Jason Wang
---
hw/net/e1000_regs.h | 7 +
From: Akihiko Odaki
Some definitions in the header files are invalid for igb so extract
them to new header files to keep igb from referring to them.
Signed-off-by: Gal Hammer
Signed-off-by: Marcel Apfelbaum
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Jason
From: Akihiko Odaki
e1000e_write_packet_to_guest() passes the reference of variable ba as a
pointer to an array, and that pointer indirection is just unnecessary;
all functions which uses the passed reference performs no pointer
operation on the pointer and they simply dereference the passed
poin
From: Akihiko Odaki
This is part of recent efforts of refactoring e1000 and e1000e.
DeviceClass's reset member is deprecated so migrate to ResettableClass.
There is no behavioral difference.
Signed-off-by: Akihiko Odaki
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-of
From: Akihiko Odaki
I want to know to be notified when there is a new change for e1000e
as e1000e is similar to igb and such a change may also be applicable for
igb.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Jason Wang
---
MAINTAINERS | 2 ++
1 file chan
From: Akihiko Odaki
hw/net/mii.h provides common definitions for MII.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Jason Wang
---
hw/net/fsl_etsec/etsec.c | 11 ++-
hw/net/fsl_etsec/etsec.h | 17 -
hw/net/fsl_etsec/miim.c | 5 +++--
From: Akihiko Odaki
There was no proper implementation of TCP segmentation before this
change, and net_tx_pkt relied solely on IPv4 fragmentation. Not only
this is not aligned with the specification, but it also resulted in
corrupted IPv6 packets.
This is particularly problematic for the igb, a
From: Akihiko Odaki
Use memcpy instead of memmove to initialize registers. The initial
register templates and register table instances will never overlap.
Signed-off-by: Akihiko Odaki
Signed-off-by: Jason Wang
---
hw/net/e1000e_core.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
From: Akihiko Odaki
filter-dump specifiees Ethernet as PCAP LinkType, which does not expect
virtio-net header. Having virtio-net header in such PCAP file breaks
PCAP unconsumable. Unfortunately currently there is no LinkType for
virtio-net so for now strip virtio-net header to convert the output
From: Akihiko Odaki
This change makes e1000e reset more things when software reset was
triggered. Some registers are exempted from software reset in the
datasheet and this change also implements the behavior accordingly.
Signed-off-by: Akihiko Odaki
Signed-off-by: Jason Wang
---
hw/net/e1000e
From: Akihiko Odaki
When a register has effective bits fewer than their width, the old code
inconsistently masked when writing or reading. Make the code consistent
by always masking when writing, and remove some code duplication.
Signed-off-by: Akihiko Odaki
Signed-off-by: Jason Wang
---
hw/n
From: Akihiko Odaki
net_tx_pkt_build_vheader() inspects TCP header but had no check for
the header size, resulting in an undefined behavior. Check the header
size and drop the packet if the header is too small.
Signed-off-by: Akihiko Odaki
Signed-off-by: Jason Wang
---
hw/net/e1000e_core.c |
From: Akihiko Odaki
hw/net/mii.h provides common definitions for MII.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Jason Wang
---
hw/net/e1000.c | 86 +--
hw/net/e1000_regs.h| 46 ---
h
The following changes since commit 817fd33836e73812df2f1907612b57750fcb9491:
Merge tag 'audio-pull-request' of https://gitlab.com/marcandre.lureau/qemu
into staging (2023-03-06 14:06:06 +)
are available in the git repository at:
https://github.com/jasowang/qemu.git tags/net-pull-request
On Mon, Mar 6, 2023 at 7:33 PM Eugenio Perez Martin wrote:
>
> On Mon, Mar 6, 2023 at 4:42 AM Jason Wang wrote:
> >
> > On Fri, Mar 3, 2023 at 4:58 PM Eugenio Perez Martin
> > wrote:
> > >
> > > On Fri, Mar 3, 2023 at 4:48 AM Jason Wang wrote:
> > > >
> > > >
> > > > 在 2023/3/2 03:32, Eugenio
Ping?
The patch already got the Reviewed-by from Philippe Mathieu-Daudé and Alistair
Francis.
The current log does not provide much information when (1) multiple CPUs are
involved in the bug, and (2) when the "info registers -a" is not used to collect
the context from all CPUs for comparison.
We
Il mar 7 mar 2023, 01:06 BALATON Zoltan ha scritto:
> I'm not sure I follow what you mean so I'd need a patch to see then I can
> test it with the clients I run on pegasos2.
Do you have a spec, or pointer to the morphos kernel sources, to figure out
how the hardware works?
Paolo
> Regards,
>
On 06-03-23, 10:34, Stefan Hajnoczi wrote:
> On Mon, Mar 06, 2023 at 04:40:24PM +0530, Viresh Kumar wrote:
> > +Xen mmap description
> > +
> > +
> > ++---+---+
> > +| flags | domid |
> > ++---+---+
> > +
> > +:flags: 64-bit bit field
> > +
> > +- Bit 0 is set for
On 3/6/23 18:58, Taylor Simpson wrote:
Add overrides for
SL2_jumpr31Unconditional
SL2_jumpr31_t Predicated true (old value)
SL2_jumpr31_f Predicated false (old value)
SL2_jumpr31_tnew Predicated true (new value)
SL2_jumpr31_fnew P
The following improvements are made for predicated HVX instructions
During gen_commit_hvx, unconditionally move the "new" value into
the dest
Don't set slot_cancelled
Remove runtime bookkeeping of which registers were updated
Reduce the cases where gen_log_vreg_write[_pair]
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230307025828.1612809-4-tsimp...@quicinc.com>
---
target/hexagon/gen_tcg.h | 4 +++
target/hexagon/genptr.c | 78
2 files changed, 82 insertions(+)
diff --git a/target/hexagon/gen
Made possible by new toolchain container
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230307025828.1612809-11-tsimp...@quicinc.com>
---
tests/tcg/hexagon/Makefile.target | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/tests/tcg/hexa
Add control registers (c4, c5) to clobbers list
Made possible by new toolchain container
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230307025828.1612809-9-tsimp...@quicinc.com>
---
tests/tcg/hexagon/preg_alias.c | 10 +-
1 file changed, 5 insertions(+), 5
From: Anton Johansson
Removes code paths used by COF instructions, which are no longer
processed by idef-parser.
Tested-by: Taylor Simpson
Reviewed-by: Taylor Simpson
Signed-off-by: Taylor Simpson
Signed-off-by: Anton Johansson
Message-Id: <20230131223133.8592-1-a...@rev.ng>
---
target/hexa
We assign the instruction destination register to hex_new_value[num]
instead of a TCG temp that gets copied back to hex_new_value[num].
We introduce new functions get_result_gpr[_pair] to facilitate getting
the proper destination register.
Since we preload hex_new_value for predicated instruction
Add overrides for
J2_callr
J2_callrt
J2_callrf
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230307025828.1612809-3-tsimp...@quicinc.com>
---
target/hexagon/gen_tcg.h | 6 ++
target/hexagon/macros.h | 12 +---
target/hexagon/genptr.c | 18 +
From: Richard Henderson
Merge mov with andi.
Suggested-by: Taylor Simpson
Signed-off-by: Richard Henderson
Signed-off-by: Taylor Simpson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Taylor Simpson
Message-Id: <20230306225724.2105263-1-richard.hender...@linaro.org>
---
target/hexagon/id
The following changes since commit f003dd8d81f7d88f4b1f8802309eaa76f6eb223a:
Merge tag 'pull-tcg-20230305' of https://gitlab.com/rth7680/qemu into staging
(2023-03-06 10:20:04 +)
are available in the Git repository at:
https://github.com/quic/qemu tags/pull-hex-20230306
We only need to track slot for predicated stores and predicated HVX
instructions.
Add arguments to the probe helper functions to indicate if the slot
is predicated.
Here is a simple example of the differences in the TCG code generated:
IN:
0x00400094: 0xf900c102 { if (P0) R2 = and(R0,R1)
The F2_sffms instruction [r0 -= sfmpy(r1, r2)] doesn't properly
handle -0. Previously we would negate the input operand by subtracting
from zero. Instead, we negate by changing the sign bit.
Test case added to tests/tcg/hexagon/fpstuff.c
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johanss
The pkt_has_store_s1 field in CPUHexagonState is only needed in generated
helpers for scalar load instructions. See check_noshuf and mem_load[1248]
in op_helper.c.
We add logic in gen_analyze_funcs.py to set need_pkt_has_store_s1 in
DisasContext when it is needed at runtime.
Signed-off-by: Taylo
These instructions perform a deallocframe+return (jumpr r31)
Add overrides for
L4_return
SL2_return
L4_return_t
L4_return_f
L4_return_tnew_pt
L4_return_fnew_pt
L4_return_tnew_pnt
L4_return_fnew_pnt
SL2_return_t
SL2_return_f
SL2_return_tnew
SL2_return
We create a new generator that creates an analyze_ function for
each instruction. Currently, these functions record the writes to
R, P, and C registers by calling ctx_log_reg_write[_pair] or
ctx_log_pred_write.
During gen_start_packet, we invoke the analyze_ function for
each instruction in the p
Replace __builtin_* with inline assembly
The __builtin's are subject to change with different compiler
releases, so might break
Mark arrays as aligned when accessed as HVX vectors
Clean up comments
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230307025828.161
Add overrides for
SL2_jumpr31Unconditional
SL2_jumpr31_t Predicated true (old value)
SL2_jumpr31_f Predicated false (old value)
SL2_jumpr31_tnew Predicated true (new value)
SL2_jumpr31_fnew Predicated false (new value)
Signed-off-by: Ta
The --disable-hexagon-idef-parser configuration was broken by this patch
2feacf60c23ba6 (target/hexagon: Drop tcg_temp_free from C code)
That config is not tested by CI
Fix is simple: Mark a few TCGv variables as unused
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20
Extend the analyze_ functions for HVX vector and predicate writes
Remove calls to ctx_log_vreg_write[_pair] from gen_tcg_funcs.py
During gen_start_packet, reload the predicated HVX registers into
fugure_VRegs and tmp_VRegs
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id
Hi,
On 23/02/23 7:10 pm, Daniel P. Berrangé wrote:
This extends the QAPI schema validation to permit unions inside unions,
provided the checks for clashing fields pass.
Signed-off-by: Daniel P. Berrangé
---
scripts/qapi/schema.py| 6 +-
tests/qapi-schema/meson.buil
Add signature and signature-granularity properties in spike to specify the
target
signatrue file and the line size for signature data.
Recgonize the signature section between begin_signature and end_signature
symbols
when loading elf of ACT tests. Then dump signature data in signature section
j
ACT tests play an important role in riscv tests. This patch tries to
add related support to run ACT tests.
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-act-upstream-v3
The ACT tests can be run on qemu-system-riscv32/64 with machine argument
"-M spike,signature=,signa
On Mon, 6 Mar 2023 at 02:14, Richard Henderson
wrote:
>
> The primary issue is that of overflow, where "end" for the last
> page of the 32-bit address space overflows to 0. The fix is to
> use "last" instead, which can always be represented.
>
> This requires that we adjust reserved_va as well, b
Hi Richard,
> On Mar 7, 2023, at 10:33, Richard Henderson
> wrote:
>
> On 3/6/23 18:29, Richard Henderson wrote:
>> On 3/6/23 18:14, Chen Baozi wrote:
>>> Add implementation defined registers for neoverse-n1 which
>>> would be accessed by TF-A. Since there is no DSU in Qemu,
>>> CPUCFR_EL1.SCU
We only need to track slot for predicated stores and predicated HVX
instructions.
Add arguments to the probe helper functions to indicate if the slot
is predicated.
Here is a simple example of the differences in the TCG code generated:
IN:
0x00400094: 0xf900c102 { if (P0) R2 = and(R0,R1)
We create a new generator that creates an analyze_ function for
each instruction. Currently, these functions record the writes to
R, P, and C registers by calling ctx_log_reg_write[_pair] or
ctx_log_pred_write.
During gen_start_packet, we invoke the analyze_ function for
each instruction in the p
Made possible by new toolchain container
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
---
tests/tcg/hexagon/Makefile.target | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/tests/tcg/hexagon/Makefile.target
b/tests/tcg/hexagon/Makefile.target
inde
We assign the instruction destination register to hex_new_value[num]
instead of a TCG temp that gets copied back to hex_new_value[num].
We introduce new functions get_result_gpr[_pair] to facilitate getting
the proper destination register.
Since we preload hex_new_value for predicated instruction
The idef-parser skips the change-of-flow (COF) instructions, so add
overrides
The new toolchain allows us to execute the HVX tests
New generator enables significant improvement to TCG generation for
predicated instructions by removing the need for slot_cancelled
Changes in v2
Add a new
These instructions perform a deallocframe+return (jumpr r31)
Add overrides for
L4_return
SL2_return
L4_return_t
L4_return_f
L4_return_tnew_pt
L4_return_fnew_pt
L4_return_tnew_pnt
L4_return_fnew_pnt
SL2_return_t
SL2_return_f
SL2_return_tnew
SL2_return
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
---
target/hexagon/gen_tcg.h | 4 +++
target/hexagon/genptr.c | 78
2 files changed, 82 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index fa0dbbec7d..4f84baf0
The F2_sffms instruction [r0 -= sfmpy(r1, r2)] doesn't properly
handle -0. Previously we would negate the input operand by subtracting
from zero. Instead, we negate by changing the sign bit.
Test case added to tests/tcg/hexagon/fpstuff.c
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johanss
Add overrides for
SL2_jumpr31Unconditional
SL2_jumpr31_t Predicated true (old value)
SL2_jumpr31_f Predicated false (old value)
SL2_jumpr31_tnew Predicated true (new value)
SL2_jumpr31_fnew Predicated false (new value)
Signed-off-by: Ta
Add control registers (c4, c5) to clobbers list
Made possible by new toolchain container
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
---
tests/tcg/hexagon/preg_alias.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/tests/tcg/hexagon/preg_alias.c b/
Extend the analyze_ functions for HVX vector and predicate writes
Remove calls to ctx_log_vreg_write[_pair] from gen_tcg_funcs.py
During gen_start_packet, reload the predicated HVX registers into
fugure_VRegs and tmp_VRegs
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
---
targe
The following improvements are made for predicated HVX instructions
During gen_commit_hvx, unconditionally move the "new" value into
the dest
Don't set slot_cancelled
Remove runtime bookkeeping of which registers were updated
Reduce the cases where gen_log_vreg_write[_pair]
The pkt_has_store_s1 field in CPUHexagonState is only needed in generated
helpers for scalar load instructions. See check_noshuf and mem_load[1248]
in op_helper.c.
We add logic in gen_analyze_funcs.py to set need_pkt_has_store_s1 in
DisasContext when it is needed at runtime.
Signed-off-by: Taylo
Replace __builtin_* with inline assembly
The __builtin's are subject to change with different compiler
releases, so might break
Mark arrays as aligned when accessed as HVX vectors
Clean up comments
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
---
tests/tcg/hexagon/scatter_
Add overrides for
J2_callr
J2_callrt
J2_callrf
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
---
target/hexagon/gen_tcg.h | 6 ++
target/hexagon/macros.h | 12 +---
target/hexagon/genptr.c | 18 ++
3 files changed, 25 insertions(+), 11 del
On Tue, 7 Mar 2023 02:02:52 +
Joao Martins wrote:
> According to the device DMA logging uAPI, IOVA ranges to be logged by
> the device must be provided all at once upon DMA logging start.
>
> As preparation for the following patches which will add device dirty
> page tracking, keep a record
On 3/6/23 00:46, Thomas Huth wrote:
+continuous to be supported on 32-bit arm hosts, too)
"continues"
Acked-by: Richard Henderson
r~
1 - 100 of 575 matches
Mail list logo
