One has 3 register arguments; the other has 2 plus an m3 field.
Reviewed-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.c.inc | 57 +-
1 file changed, 32 insertions(+), 25 deletions(-)
diff --git a/tcg/s390x/tcg-target.c.inc b
There is only one instruction that is applicable
to a 32-bit immediate xor.
Reviewed-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
i
This reverts 829e1376d940 ("tcg/s390: Introduce TCG_REG_TB"), and
several follow-up patches. The primary motivation is to reduce the
less-tested code paths, pre-z10. Secondarily, this allows the
unconditional use of TCG_TARGET_HAS_direct_jump, which might be more
important for performance than an
We are already assuming the existance of long-displacement, but were
not being explicit about it. This has been present since z990.
Reviewed-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.h | 6 --
tcg/s390x/tcg-target.c.inc | 15 +++
2 file
Previously we hard-coded R2 and R3.
Reviewed-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target-con-set.h | 4 ++--
tcg/s390x/tcg-target-con-str.h | 8 +--
tcg/s390x/tcg-target.c.inc | 43 +-
3 files changed, 35 insertions(+)
The size of a compiled TB is limited by the uint16_t used by
gen_insn_end_off[] -- there is no need for a 32-bit branch.
Reviewed-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.c.inc | 9 -
1 file changed, 9 deletions(-)
diff --git a/tcg/s390x/tcg-target
Since USE_REG_TB is removed, there is no need to load the
target TB address into a register.
Reviewed-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.h | 2 +-
tcg/s390x/tcg-target.c.inc | 48 +++---
2 files changed, 10 inserti
Merge maybe_out_small_movi, as it no longer has additional users.
Use is_const_p{16,32}.
Reviewed-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.c.inc | 52 --
1 file changed, 16 insertions(+), 36 deletions(-)
diff --git a/tcg
The MIE2 facility adds a 3-operand signed 64x64->128 multiply.
Reviewed-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target-con-set.h | 1 +
tcg/s390x/tcg-target.h | 2 +-
tcg/s390x/tcg-target.c.inc | 8
3 files changed, 10 insertions(+), 1 deleti
The following changes since commit aaa90fede5d10e2a3c3fc7f2df608128d2cba761:
Merge tag 'pull-tcg-20230105' of https://gitlab.com/rth7680/qemu into staging
(2023-01-06 15:40:37 +)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-2023010
Let the register allocator handle such immediates by matching
only what one insn can achieve.
Reviewed-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target-con-set.h | 1 +
tcg/s390x/tcg-target-con-str.h | 2 +
tcg/s390x/tcg-target.c.inc | 114 +
Load constants in no more than two insns, which turns
out to be faster than using the constant pool.
Suggested-by: Ilya Leoshkevich
Reviewed-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.c.inc | 23 +--
1 file changed, 17 insertions(+), 6 de
The extended-immediate facility was introduced in z9-109,
which itself was end-of-life in 2017.
Reviewed-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.h | 4 +-
tcg/s390x/tcg-target.c.inc | 231 +++--
2 files changed, 72 ins
This is andc, orc, nand, nor, eqv.
We can use nor for implementing not.
Reviewed-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target-con-set.h | 3 +
tcg/s390x/tcg-target.h | 25
tcg/s390x/tcg-target.c.inc | 102
From: Henrik Carlqvist
SUN Type 4, 5 and 5c keyboards have dip switches to choose the language
layout of the keyboard. Solaris makes an ioctl to query the value of the
dipswitches and uses that value to select keyboard layout. Also the SUN
bios like the one in the file ss5.bin uses this value to
Year 2020 I made 2 attempts to contribute this patch. Unfortunately "git
format-patch" produced crippled patches which were not possible to
apply. Some @@-lines got extra code that didn't belong in those lines.
Now I am instead trying to send my patch using sourcehut. Unfortunately,
it seems as if
On Fri, Jan 6, 2023, 5:31 AM Alex Bennée wrote:
> Are you going to be able to post the patches soon? I'd like to get the
> fixes in as early in the cycle as possible.
>
I intend to post this series on Sunday.
Thanks,
Emilio
This is a ping to the patch below.
https://patchew.org/QEMU/ty0pr0101mb42855925d8414e4773d6fa36a4...@ty0pr0101mb4285.apcprd01.prod.exchangelabs.com/
Before this commit, when GDB attached an OS working on QEMU, order of FPU
stack registers printed by GDB command 'info float' was wrong. There was a
On 1/6/23 6:04 PM, Chuck Zmudzinski wrote:
> On 1/6/23 2:08 PM, Chuck Zmudzinski wrote:
>> On 1/6/23 7:25 AM, Philippe Mathieu-Daudé wrote:
>>> On 6/1/23 12:57, Bernhard Beschow wrote:
Am 4. Januar 2023 15:35:33 UTC schrieb "Philippe Mathieu-Daudé"
:
> +Markus/Thomas
Although we still can't use ldrd and strd for all operations,
increase the chances by getting the register allocation correct.
Signed-off-by: Richard Henderson
---
v3 was patch 5 in a larger patch set:
https://lore.kernel.org/qemu-devel/2022074101.2069454-6-richard.hender...@linaro.org/
On 1/5/23 08:43, Alex Bennée wrote:
Now we have removed any target specific bits from the core gdbstub
code we only need to build it twice. We have to jump a few meson hoops
to manually define the CONFIG_USER_ONLY symbol but it seems to work.
Signed-off-by: Alex Bennée
---
gdbstub/gdbstub.c
On 1/6/23 15:43, Alex Bennée wrote:
What about cloning objects after they are realised? After all that is
what we do for the core CPUClass in user-mode.
No we don't. Where do you get that idea?
r~
On 1/5/23 08:43, Alex Bennée wrote:
+++ b/gdbstub/syscalls.c
@@ -0,0 +1,230 @@
+/*
+ * GDB Syscall Handling
+ *
+ * GDB can execute syscalls on the guests behalf, currently used by
+ * the various semihosting extensions. As this interfaces with a guest
+ * ABI we need to build it per-guest (altho
On Fri, Jan 06, 2023 at 04:36:09PM -0700, Alex Williamson wrote:
> Missing from the series is the all important question of what happens
> to "x-enable-migration" now. We have two in-kernel drivers supporting
> v2 migration, so while hardware and firmware may still be difficult to
> bring togethe
Peter Maydell writes:
> On Fri, 6 Jan 2023 at 19:29, Richard Henderson
> wrote:
>>
>> On 1/6/23 11:12, Peter Maydell wrote:
>> > The trouble with this idea is that not all instances of the same
>> > class are actually necessarily the same. For instance, if you
>> > have a system with both (a)
On Thu, 29 Dec 2022 13:03:31 +0200
Avihai Horon wrote:
> Hello,
>
> Now that QEMU 8.0 development cycle has started and MIG_DATA_SIZE ioctl
> is in kernel v6.2-rc1, I am sending v5 of this series with linux headers
> update and with the preview patches in v4 merged into this series.
>
>
>
> F
On 1/5/23 08:43, Alex Bennée wrote:
These inline helpers are all used by target specific code so move them
out of the general header so we don't needlessly pollute the rest of
the API with target specific stuff.
Note we have to include cpu.h in semihosting as it was relying on a
side effect befo
On 1/5/23 09:28, Philippe Mathieu-Daudé wrote:
static void handle_write_all_regs(GArray *params, void *user_ctx)
{
- target_ulong addr, len;
+ int reg_id;
'unsigned'?
No, match the third argument to gdb_write_register (int).
r~
On 1/5/23 08:43, Alex Bennée wrote:
This is a hangover from the original code. addr is misleading as it is
only a really a register id. While len will never exceed
MAX_PACKET_LENGTH I've used size_t as that is what strlen returns.
What has strlen got to do with it? I think it would be better t
On 1/5/23 08:43, Alex Bennée wrote:
The underlying call uses vaddr and the comms API uses unsigned long
long which will always fit. We don't need to deal in target_ulong
here.
Signed-off-by: Alex Bennée
---
gdbstub/gdbstub.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed
On 1/5/23 08:43, Alex Bennée wrote:
Currently we only support replay for softmmu mode so it is a constant
false for user-mode.
Signed-off-by: Alex Bennée
---
gdbstub/internals.h | 1 +
gdbstub/gdbstub.c | 13 ++---
gdbstub/softmmu.c | 5 +
gdbstub/user.c | 5 +
On 1/5/23 08:43, Alex Bennée wrote:
+unsigned int gdb_get_max_cpus(void)
+{
+CPUState *cpu;
+unsigned int max_cpus = 1; /* global variable max_cpus exists only in
system mode */
You can delete the out-of-date comment, since there's no global variable
anywhere.
Otherwise,
Reviewed-by:
On 1/5/23 08:43, Alex Bennée wrote:
The two implementations are different enough to encourage having a
specialisation and we can move some of the softmmu only stuff out of
gdbstub.
Signed-off-by: Alex Bennée
---
gdbstub/internals.h | 19
gdbstub/gdbstub.c | 73 +++--
On 1/6/23 2:08 PM, Chuck Zmudzinski wrote:
> On 1/6/23 7:25 AM, Philippe Mathieu-Daudé wrote:
>> On 6/1/23 12:57, Bernhard Beschow wrote:
>>>
>>>
>>> Am 4. Januar 2023 15:35:33 UTC schrieb "Philippe Mathieu-Daudé"
>>> :
+Markus/Thomas
On 4/1/23 15:44, Bernhard Beschow wrote:
>
On 1/6/23 14:14, Peter Maydell wrote:
+if (arm_feature(env, ARM_FEATURE_V7MP)) {
+cpu->mpidr_el1 |= (1u << 31); /* M */
+if (cpu->core_count == 1) {
+cpu->mpidr_el1 |= 1 << 30; /* U */
+}
+}
This is wrong, incidentally -- a single Cortex A9, A53, et
On 1/6/23 13:59, Peter Maydell wrote:
We also set some properties in code -- eg aspeed_ast2600.c clears
the 'neon' property on its CPUs, lots of the boards clear
has_el3 and has_el2, etc.
Yes indeed, but in all of those cases we want all of the cpus to act identically. Those
are all easily ha
On Fri, 6 Jan 2023 at 03:17, Richard Henderson
wrote:
>
> Changes in patch 47, to reduce execution time with --enable-debug.
> Changes in patch 19, to fix an i386 specific register allocation failure.
>
>
> r~
>
>
> The following changes since commit cb9c6a8e5ad6a1f0ce164d352e3102df46986e22:
>
>
On Fri, 6 Jan 2023 at 19:33, Richard Henderson
wrote:
>
> On 1/6/23 11:16, Peter Maydell wrote:
> > On Tue, 3 Jan 2023 at 18:24, Richard Henderson
> > wrote:
> >>
> >> Replace ARMCPU.mp_affinity with CPUARMState.cp15.mpidr_el1,
> >> setting the additional bits as required. In particular,
> >> al
On Wed, Dec 7, 2022 at 1:29 PM Maksim Davydov
wrote:
>
> Current 256KB is not enough for some real cases. As a possible solution
> limit can be chosen to be the same as libvirt (10MB)
>
> Signed-off-by: Maksim Davydov
This matches the patch accepted here:
https://gitlab.com/qemu-project/python-q
On Fri, 6 Jan 2023 at 19:29, Richard Henderson
wrote:
>
> On 1/6/23 11:12, Peter Maydell wrote:
> > The trouble with this idea is that not all instances of the same
> > class are actually necessarily the same. For instance, if you
> > have a system with both (a) a Cortex-A53 with a PMU, and
> > (b
On 1/5/23 08:43, Alex Bennée wrote:
In both user and softmmu cases we are just replying with a constant.
If the linker is paying attention it may even be able to sort optimise
the call.
Signed-off-by: Alex Bennée
---
gdbstub/internals.h | 4 +++-
gdbstub/gdbstub.c | 15 ++-
gd
On Fri, Dec 9, 2022 at 11:47 AM Philippe Mathieu-Daudé
wrote:
>
> On non-x86_64 host, if KVM is not available we get:
>
> Traceback (most recent call last):
> File "tests/vm/basevm.py", line 634, in main
> vm = vmcls(args, config=config)
> File "tests/vm/basevm.py", line 104, in __
On 1/5/23 08:43, Alex Bennée wrote:
We unfortunately handle the checking of packet acknowledgement
differently for user and softmmu modes. Abstract the user mode stuff
behind gdb_got_immediate_ack with a stub for softmmu.
Signed-off-by: Alex Bennée
---
gdbstub/internals.h | 15 +++
On Thu, 29 Dec 2022 13:03:36 +0200
Avihai Horon wrote:
> Currently, if IOMMU of a VFIO container doesn't support dirty page
> tracking, migration is blocked. This is because a DMA-able VFIO device
> can dirty RAM pages without updating QEMU about it, thus breaking the
> migration.
>
> However, t
On 1/5/23 08:43, Alex Bennée wrote:
+static int gdb_signal_table[] = {
+-1,
+-1,
+TARGET_SIGINT,
+-1,
+-1,
+TARGET_SIGTRAP
+};
+
+int gdb_signal_to_target (int sig)
+{
+if (sig < ARRAY_SIZE (gdb_signal_table))
+return gdb_signal_table[sig];
+else
+r
On Tue, Jan 3, 2023 at 5:13 PM Arthur Sengileyev
wrote:
>
> It should be possible to reuse cache built by previous iteration
> processing next executables. Already processed dependencies are
> already skipped later based on dll name.
>
> Signed-off-by: Arthur Sengileyev
> ---
> scripts/nsis.py |
On 1/5/23 08:43, Alex Bennée wrote:
@@ -60,8 +67,6 @@ typedef struct GDBState {
int signal;
#ifdef CONFIG_USER_ONLY
GDBUserState user;
-#else
-GDBSystemState system;
In patch 6 you nested this variable, and now you're undoing that.
Get this placed properly to start, as I sugge
On 1/5/23 08:43, Alex Bennée wrote:
We will be needing to use these helpers between the user and softmmu
files so declare them in the headers, add a system prefix and remove
static from the implementations.
Signed-off-by: Alex Bennée
---
gdbstub/internals.h | 25
gdbstub/gdbstub.c | 2
On 1/5/23 08:43, Alex Bennée wrote:
These will be needed from multiple places in the code. They are
declared as inline so move to the header and fix up to modern coding
style.
The only other place that messes with hex stuff at the moment is the
URI handling in utils but that would be more code c
On 1/5/23 08:43, Alex Bennée wrote:
We are about to split softmmu and user mode helpers into different
files. To facilitate this we will need to share access to the GDBState
between those files.
To keep building we have to temporarily define CONFIG_USER_ONLY just
before we include internals.h fo
On 1/5/23 08:43, Alex Bennée wrote:
In preparation for moving user/softmmu specific bits from the main
gdbstub file we need to separate the connection details into a
user/softmmu state. These will eventually be defined in their own
files.
Signed-off-by: Alex Bennée
---
gdbstub/gdbstub.c | 91 +
On 1/5/23 08:43, Alex Bennée wrote:
The check semihosting_enabled() wants to know if the guest is
currently in user mode. Unlike the other cases the test was inverted
causing us to block semihosting calls in non-EL0 modes.
Fixes: 19b26317e9 (target/arm: Honour -semihosting-config userspace=on)
S
On 1/4/23 19:04, Philippe Mathieu-Daudé wrote:
Nothing here requires access to PFlashCFI01 internal fields:
use the inherited generic DeviceState.
Signed-off-by: Philippe Mathieu-Daudé
---
Reviewed-by: Daniel Henrique Barboza
hw/riscv/virt.c | 9 +
include/hw/riscv/v
Move the ri == NULL case to the top of the function and return.
This allows the else to be removed and the code unindented.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 406 -
1 file changed, 203 insertions(+), 203 deletions(-)
diff --git
Do not encode the pointer as a constant in the opcode stream.
This pointer is specific to the cpu that first generated the
translation, which runs into problems with both hot-pluggable
cpus and user-only threads, as cpus are removed.
Perform the lookup in either helper_access_check_cp_reg,
or a ne
Here's a short-to-medium term alternative to moving all of the ARMCPU
cp_regs hash table to the ARMCPUClass, so that we're no longer leaving
dangling pointers to freed objects encoded in the compiled
TranslationBlocks. (I still think we ought to do less work at
object_{init,realize}, but that may
On 1/6/23 11:16, Peter Maydell wrote:
On Tue, 3 Jan 2023 at 18:24, Richard Henderson
wrote:
Replace ARMCPU.mp_affinity with CPUARMState.cp15.mpidr_el1,
setting the additional bits as required. In particular,
always set the U bit when there is only one cpu in the system.
Remove the mp_is_up bi
On 1/6/23 11:12, Peter Maydell wrote:
The trouble with this idea is that not all instances of the same
class are actually necessarily the same. For instance, if you
have a system with both (a) a Cortex-A53 with a PMU, and
(b) a Cortex-A53 without a PMU, then they're both instances of
the same cla
On 1/5/23 05:07, Philippe Mathieu-Daudé wrote:
This helper is trivial and is called once, directly open-code it.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/fuloong2e.c| 6 +-
hw/pci-host/bonito.c | 15 ---
include/hw/mips/mips.h | 3 ---
3 files changed, 5 ins
On Tue, 3 Jan 2023 at 18:24, Richard Henderson
wrote:
>
> Replace ARMCPU.mp_affinity with CPUARMState.cp15.mpidr_el1,
> setting the additional bits as required. In particular,
> always set the U bit when there is only one cpu in the system.
> Remove the mp_is_up bit which attempted to do the same
On 1/5/23 05:07, Philippe Mathieu-Daudé wrote:
Declare the TYPE_BONITO_PCI_HOST_BRIDGE QOM type in a
header to be able to access it from board code.
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 1 +
hw/pci-host/bonito.c | 4 +---
include/hw/pci-host/boni
On 1/5/23 05:07, Philippe Mathieu-Daudé wrote:
Since TYPE_BONITO_PCI_HOST_BRIDGE inherits the TYPE_SYSBUS
interface, use its API the manage the outgoing IRQ.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/bonito.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
On Tue, 3 Jan 2023 at 18:27, Richard Henderson
wrote:
> The specific problem I'm trying to solve is the location and
> representation of the coprocessor register hash table for ARM cpus,
> but in the process affects how cpu initialization might be done for
> all targets.
>
> At present, each cpu (
On 1/6/23 7:25 AM, Philippe Mathieu-Daudé wrote:
> On 6/1/23 12:57, Bernhard Beschow wrote:
>>
>>
>> Am 4. Januar 2023 15:35:33 UTC schrieb "Philippe Mathieu-Daudé"
>> :
>>> +Markus/Thomas
>>>
>>> On 4/1/23 15:44, Bernhard Beschow wrote:
During the last patches, TYPE_PIIX3_XEN_DEVICE turned
On Fri, 6 Jan 2023 at 18:22, Evgeny Iakovlev
wrote:
>
>
> On 1/6/2023 17:28, Peter Maydell wrote:
> > On Fri, 6 Jan 2023 at 15:44, Alex Bennée wrote:
> >> Peter Maydell writes:
> > I think the theory when the semihosting API was originally designed
> > decades ago was basically "when the guest d
On 1/5/23 05:07, Philippe Mathieu-Daudé wrote:
The PCI function #0 is an integral part of the PCI bridge,
instantiate it internally during the bridge creation.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/bonito.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
di
On 1/5/23 05:07, Philippe Mathieu-Daudé wrote:
A QOM object shouldn't poke at another object internals.
Here the PCI host bridge instantiates its PCI function #0
and sets a reference to itself (so the function can access
the bridge fields).
Pass this reference with object_property_add_const_lin
On 1/5/23 05:07, Philippe Mathieu-Daudé wrote:
To make it easier to differentiate between the Host Bridge
object and its PCI function #0, rename bonito* as bonito_pci*.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/bonito.c | 16
1 file changed, 8 insertions(+), 8 del
On Thu, Jan 5, 2023 at 8:50 PM Dongdong Zhang
wrote:
>
> Hi John,
>
> Could you help me relay these fixes?
> If I submit a pull request, I will go through company's internal review
> process again.
No problem at all. My apologies for the delay.
Staged for QEMU, with additional fix spotted by Ma
On 1/5/23 05:07, Philippe Mathieu-Daudé wrote:
To make it easier to differentiate between the Host Bridge
object and its PCI function #0, rename bonito_pcihost* as
bonito_host*.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/bonito.c | 12 ++--
1 file changed, 6 insertions(+),
On 1/5/23 05:07, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
Convert the TYPE_PCI_BONITO class to use 3-phase reset.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/bonito.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
Reviewed-by: Richard Henderson
On 1/6/23 12:46 PM, Chuck Zmudzinski wrote:
> On 1/6/23 12:35 PM, David Woodhouse wrote:
>> On Wed, 2023-01-04 at 15:44 +0100, Bernhard Beschow wrote:
>>> + if (xen_enabled()) {
>>
>> Could this perhaps be if (xen_mode != XEN_DISABLED) once we merge the
>> Xen-on-KVM series?
>
> I am not a
On 1/6/2023 17:28, Peter Maydell wrote:
On Fri, 6 Jan 2023 at 15:44, Alex Bennée wrote:
Peter Maydell writes:
The semihosting API, at least for Arm, has a modeflags string so the
guest can say whether it wants to open O_BINARY or not:
https://github.com/ARM-software/abi-aa/blob/main/semihos
On Tue, 3 Jan 2023 11:13:21 +
"Dr. David Alan Gilbert" wrote:
> * Avihai Horon (avih...@nvidia.com) wrote:
> > As part of its error flow, vfio_vmstate_change() accesses
> > MigrationState->to_dst_file without any checks. This can cause a NULL
> > pointer dereference if the error flow is taken
Since I applied this twice already to my local trees, let me ping for Ted
to make sure it's not lost..
On Mon, Dec 05, 2022 at 08:07:12PM +0800, Ted Chen wrote:
> It's convenient to dump HVA and RW/RO status of a ramblock in "info ramblock"
> for debug purpose.
>
> Before:
> Offset
On Thu, 29 Dec 2022 13:03:34 +0200
Avihai Horon wrote:
> From: Juan Quintela
IMHO, there should always be a commit log description. Why is this a
simplification? What does it allow us to do? Nothing later obviously
depends on this, why is it part of this series? Thanks,
Alex
> Signed-off-
Ilya Leoshkevich writes:
> Add ability to dump /tmp/perf-.map and jit-.dump.
> The first one allows the perf tool to map samples to each individual
> translation block. The second one adds the ability to resolve symbol
> names, line numbers and inspect JITed code.
>
> Example of use:
>
> pe
On Wed, 4 Jan 2023 at 22:04, Philippe Mathieu-Daudé wrote:
>
> Paving the road toward heterogeneous QEMU, the limitations of
> having a single machine sysbus become more apparent.
>
> The sysbus_mmio_map() API forces the caller to map a sysbus
> device to an address on the system bus (system bus h
On 1/6/23 12:35 PM, David Woodhouse wrote:
> On Wed, 2023-01-04 at 15:44 +0100, Bernhard Beschow wrote:
>> + if (xen_enabled()) {
>
> Could this perhaps be if (xen_mode != XEN_DISABLED) once we merge the
> Xen-on-KVM series?
I am not an expert and just on here as a user/tester, but I think
On Wed, 2023-01-04 at 15:44 +0100, Bernhard Beschow wrote:
> + if (xen_enabled()) {
Could this perhaps be if (xen_mode != XEN_DISABLED) once we merge the
Xen-on-KVM series?
smime.p7s
Description: S/MIME cryptographic signature
UART should be enabled in general and have RX enabled specifically to be
able to receive data from peripheral device. Same goes for transmitting
data to peripheral device and a TXE flag.
Check if UART CR register has EN and RXE or TXE bits enabled before
trying to receive or transmit data.
Signed
Evgeny Iakovlev (2):
hw/char/pl011: better handling of FIFO flags on LCR reset
hw/char/pl011: check if UART is enabled before RX or TX operation
hw/char/pl011.c | 51 ++---
include/hw/char/pl011.h | 5 +++-
2 files changed, 41 insertions(+), 15 del
Current FIFO handling code does not reset RXFE/RXFF flags when guest
resets FIFO by writing to UARTLCR register, although internal FIFO state
is reset to 0 read count. Actual flag update will happen only on next
read or write to UART. As a result of that any guest that expects RXFE
flag to be set (
Am 04.01.23 um 13:35 schrieb Thomas Huth:
The windows jobs (especially the 32-bit job) recently started to
hit the timeout limit. Bump it a little bit to ease the situation
(80 minutes is quite long already - OTOH, these jobs do not have to
wait for a job from the container stage to finish, so th
On Mon, 19 Dec 2022 at 22:08, Alexander Graf wrote:
>
> We currently only support GICv2 emulation. To also support GICv3, we will
> need to pass a few system registers into their respective handler functions.
>
> This patch adds support for HVF to call into the TCG callbacks for GICv3
> system reg
On Mon, Dec 12, 2022 at 11:22:50AM +0100, Alexandre Ghiti wrote:
> RISC-V specifies multiple sizes for addressable memory and Linux probes for
> the machine's support at startup via the satp CSR register (done in
> csr.c:validate_vm).
>
> As per the specification, sv64 must support sv57, which in
On Fri, 6 Jan 2023 at 15:44, Alex Bennée wrote:
> Peter Maydell writes:
> > The semihosting API, at least for Arm, has a modeflags string so the
> > guest can say whether it wants to open O_BINARY or not:
> > https://github.com/ARM-software/abi-aa/blob/main/semihosting/semihosting.rst#sys-open-0x
On Wed, 4 Jan 2023 at 19:01, Richard Henderson
wrote:
>
> Don't dereference CPUTLBEntryFull until we verify that
> the page is valid. Move the other user-only info field
> updates after the valid check to match.
>
> Cc: qemu-sta...@nongnu.org
> Resolves: https://gitlab.com/qemu-project/qemu/-/iss
On Mon, 26 Dec 2022 at 22:03, Strahinja Jankovic
wrote:
>
> This patch series adds missing Allwinner A10 modules needed for
> successful SPL boot:
> - Clock controller module
> - DRAM controller
> - I2C0 controller (added also for Allwinner H3 since it is the same)
> - AXP-209 connected to I2C0 bu
On 1/6/23 10:39, Peter Maydell wrote:
On Fri, 6 Jan 2023 at 15:16, Stefan Berger wrote:
On 1/6/23 07:10, Peter Maydell wrote:
I'm seeing an intermittent hang on the s390 CI runner in the
bios-tables-test test. It looks like we've deadlocked because:
Thread 3 (Thread 0x3ff8dafe900 (
On Mon, 2 Jan 2023 at 17:52, Cédric Le Goater wrote:
>
> Cortex A7 CPUs with an FPU implementing VFPv4 without NEON support
> have 16 64-bit FPU registers and not 32 registers. Let users set the
> number of VFP registers with a CPU property.
>
> The primary use case of this property is for the Cor
Peter Maydell writes:
> On Fri, 6 Jan 2023 at 10:21, Evgeny Iakovlev
> wrote:
>>
>> Windows open(2) implementation opens files in text mode by default and
>> needs a Windows-only O_BINARY flag to open files as binary. QEMU already
>> knows about that flag in osdep and it is defined to 0 on non
On Fri, 6 Jan 2023 at 15:16, Stefan Berger wrote:
>
>
>
> On 1/6/23 07:10, Peter Maydell wrote:
> > I'm seeing an intermittent hang on the s390 CI runner in the
> > bios-tables-test test. It looks like we've deadlocked because:
> >
> > * the TPM device is waiting for data on its socket that neve
On Fri, 6 Jan 2023, Bernhard Beschow wrote:
mv64361_pcihost_map_irq() is a reimplementation of
pci_swizzle_map_irq_fn(). Resolve this redundancy.
Signed-off-by: Bernhard Beschow
Reviewed-by: BALATON Zoltan
---
Testing done:
* `qemu-system-ppc -machine pegasos2 \
-rtc base
On Thu, 5 Jan 2023 at 21:53, Michael S. Tsirkin wrote:
>
> On Thu, Jan 05, 2023 at 09:04:37PM +, Peter Maydell wrote:
> > On Thu, 5 Jan 2023 at 16:32, Michael S. Tsirkin wrote:
> > >
> > > On Thu, Jan 05, 2023 at 04:56:39AM -0500, Michael S. Tsirkin wrote:
> > > > On Thu, Jan 05, 2023 at 04:1
We were using quite and old runner on our machines and running into
issues with stalling jobs. Gitlab in the meantime now reliably provide
the latest packaged versions of the runner under a stable URL. This
update:
- creates a per-arch subdir for builds
- switches from binary tarballs to deb p
On 1/6/23 07:10, Peter Maydell wrote:
I'm seeing an intermittent hang on the s390 CI runner in the
bios-tables-test test. It looks like we've deadlocked because:
* the TPM device is waiting for data on its socket that never arrives,
and it's holding the iothread lock
* QEMU is therefo
On 1/6/23 9:31 AM, Chuck Zmudzinski wrote:
> On 1/6/23 9:10 AM, Chuck Zmudzinski wrote:
>> On 1/6/23 9:03 AM, Anthony PERARD wrote:
>>> On Sun, Jan 01, 2023 at 06:52:03PM -0500, Chuck Zmudzinski wrote:
Intel specifies that the Intel IGD must occupy slot 2 on the PCI bus,
as noted in docs/
On Fri, Jan 06, 2023 at 09:10:55AM -0500, Chuck Zmudzinski wrote:
> Well, our messages almost collided! I just proposed a v7 that adds
> a check to prevent the extra processing for cases when machine is
> not xenfv and the slot does not need to be cleared because it was
> never reserved. The propos
Hi QEMU,
I am trying to use the -O function to convert a file format to vmdk, but
get the below response. Please could you help?
Bens-iMac:~ ben$ qemu-img -O output_fmt vmdk
/Users/ben/Documents/Windows11_InsiderPreview_Client_ARM64_en-us_22598.VHDX
~/Desktop/Install/Windows11ARM.vmdk
qemu-img:
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