On Wed, Nov 23, 2022 at 8:20 AM Marc-André Lureau
wrote:
>
> Hi
>
> On Wed, Nov 23, 2022 at 12:32 AM Michael S. Tsirkin wrote:
>>
>> On Tue, Nov 22, 2022 at 06:53:49PM +0400, marcandre.lur...@redhat.com wrote:
>> > From: Marc-André Lureau
>> >
>> > 851d6d1a0f ("vfio/common: remove spurious tpm-c
On Wed, Nov 23, 2022 at 11:20:41AM +0400, Marc-André Lureau wrote:
> Hi
>
> On Wed, Nov 23, 2022 at 12:32 AM Michael S. Tsirkin wrote:
>
> On Tue, Nov 22, 2022 at 06:53:49PM +0400, marcandre.lur...@redhat.com
> wrote:
> > From: Marc-André Lureau
> >
> > 851d6d1a0f ("vfio/com
Hi
On Wed, Nov 23, 2022 at 12:32 AM Michael S. Tsirkin wrote:
> On Tue, Nov 22, 2022 at 06:53:49PM +0400, marcandre.lur...@redhat.com
> wrote:
> > From: Marc-André Lureau
> >
> > 851d6d1a0f ("vfio/common: remove spurious tpm-crb-cmd misalignment
> > warning") removed the warning on vfio_listene
On Wed, Nov 23, 2022 at 03:08:25PM +0800, Jason Wang wrote:
> On Wed, Nov 23, 2022 at 2:15 PM Michael S. Tsirkin wrote:
> >
> > On Wed, Nov 23, 2022 at 01:47:04PM +0800, Jason Wang wrote:
> > > On Wed, Nov 23, 2022 at 1:26 PM Jason Wang wrote:
> > > >
> > > > On Wed, Nov 23, 2022 at 12:28 AM Eric
On Wed, Nov 23, 2022 at 2:15 PM Michael S. Tsirkin wrote:
>
> On Wed, Nov 23, 2022 at 01:47:04PM +0800, Jason Wang wrote:
> > On Wed, Nov 23, 2022 at 1:26 PM Jason Wang wrote:
> > >
> > > On Wed, Nov 23, 2022 at 12:28 AM Eric Auger wrote:
> > > >
> > > > Hi,
> > > >
> > > > On 11/22/22 10:43, Mi
Suggested-by: BALATON Zoltan
Signed-off-by: Markus Armbruster
---
hw/ppc/ppc4xx_sdram.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c
index 54bf9a2b44..a24c80b1d2 100644
--- a/hw/ppc/ppc4xx_sdram.c
+++ b/hw/ppc/ppc4xx
On Wed, Nov 23, 2022 at 07:49:53AM +0100, Stefan Weil wrote:
> Am 23.11.22 um 07:35 schrieb Stefan Weil:
> > Am 15.11.22 um 08:25 schrieb Stefan Weil:
> > > Am 05.11.22 um 11:24 schrieb Stefan Weil:
> > >
> > > > This fix is required for 32 bit host. The bug was detected by CI
> > > > for arm-linu
Am 23.11.22 um 07:35 schrieb Stefan Weil:
Am 15.11.22 um 08:25 schrieb Stefan Weil:
Am 05.11.22 um 11:24 schrieb Stefan Weil:
This fix is required for 32 bit host. The bug was detected by CI
for arm-linux, but is also relevant for i386-linux.
Reported-by: Stefan Hajnoczi
Signed-off-by: Stefa
On Fri, May 06, 2022 at 09:47:52AM -0400, Stefan Berger wrote:
>
>
> On 5/6/22 09:25, Eric Auger wrote:
> > In a subsequent patch, VFIO will need to recognize if
> > a memory region owner is a TPM CRB device. Hence VFIO
> > needs to use TPM_IS_CRB() even if CONFIG_TPM is unset. So
> > let's add a
Am 15.11.22 um 08:25 schrieb Stefan Weil:
Am 05.11.22 um 11:24 schrieb Stefan Weil:
This fix is required for 32 bit host. The bug was detected by CI
for arm-linux, but is also relevant for i386-linux.
Reported-by: Stefan Hajnoczi
Signed-off-by: Stefan Weil
---
subprojects/libvhost-user/lib
On Fri, May 06, 2022 at 03:25:08PM +0200, Eric Auger wrote:
> The CRB command buffer currently is a RAM MemoryRegion and given
> its base address alignment, it causes an error report on
> vfio_listener_region_add(). This region could have been a RAM device
> region, easing the detection of such saf
Am 21.11.22 um 23:37 schrieb Michael S. Tsirkin:
[...]
qemu-system-x86_64: ../hw/virtio/vhost-vsock-common.c:203:
vhost_vsock_common_pre_save: Assertion `!vhost_dev_is_started(&vvc->vhost_dev)'
failed.
2022-11-15 16:38:46.096+: shutting down, reason=crashed
Alex were you able to replicate
On Wed, Nov 23, 2022 at 01:47:04PM +0800, Jason Wang wrote:
> On Wed, Nov 23, 2022 at 1:26 PM Jason Wang wrote:
> >
> > On Wed, Nov 23, 2022 at 12:28 AM Eric Auger wrote:
> > >
> > > Hi,
> > >
> > > On 11/22/22 10:43, Michael S. Tsirkin wrote:
> > > > On Tue, Nov 22, 2022 at 11:01:11AM +0800, Jas
On Wed, Nov 23, 2022 at 1:26 PM Jason Wang wrote:
>
> On Wed, Nov 23, 2022 at 12:28 AM Eric Auger wrote:
> >
> > Hi,
> >
> > On 11/22/22 10:43, Michael S. Tsirkin wrote:
> > > On Tue, Nov 22, 2022 at 11:01:11AM +0800, Jason Wang wrote:
> > >> When vIOMMU is enabled, the vq->used_phys is actually
On Wed, Nov 23, 2022 at 12:28 AM Eric Auger wrote:
>
> Hi,
>
> On 11/22/22 10:43, Michael S. Tsirkin wrote:
> > On Tue, Nov 22, 2022 at 11:01:11AM +0800, Jason Wang wrote:
> >> When vIOMMU is enabled, the vq->used_phys is actually the IOVA not
> >> GPA. So we need to translate it to GPA before the
On Wed, Nov 23, 2022 at 12:50 AM Eugenio Perez Martin
wrote:
>
> On Tue, Nov 22, 2022 at 3:53 PM wrote:
> >
> > From: Marc-André Lureau
> >
> > 851d6d1a0f ("vfio/common: remove spurious tpm-crb-cmd misalignment
> > warning") removed the warning on vfio_listener_region_add() path.
> >
> > An erro
Hi Alistair,
On Wed, Nov 23, 2022 at 8:03 AM Alistair Francis wrote:
>
> On Wed, Nov 23, 2022 at 2:07 AM Bin Meng wrote:
> >
> > sstatus register dump is currently missing in riscv_cpu_dump_state().
> >
> > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1332
> > Signed-off-by: Bin Meng
We add two new configuration flags, USB_SMARTCARD_PASSTHRU and
USB_SMARTCARD_EMULATED in order to improve configurability
of these two functionalities.
Signed-off-by: Jon Maloy
---
hw/usb/Kconfig | 12
hw/usb/meson.build | 4 ++--
2 files changed, 14 insertions(+), 2 deletions(
On 11/22/22 12:57, Richard Henderson wrote:
+#define QEMU_IOTHREAD_LOCK_GUARD() \
+g_auto(IOThreadLockAuto) _iothread_lock_auto\
+= qemu_iothread_auto_lock(__FILE__, __LINE__) \
Need an extra G_GNUC_UNUSED for (some versions of?
Add cfi01 pflash device for LoongArch virt machine
Signed-off-by: Xiaojuan Yang
---
hw/loongarch/Kconfig| 1 +
hw/loongarch/acpi-build.c | 18 +
hw/loongarch/virt.c | 80 -
include/hw/loongarch/virt.h | 5 +++
4 files changed, 103 i
From: Xiang Chen
Currently the number of MSI vectors comes from register PCI_MSI_FLAGS
which should be power-of-2 in qemu, in some scenaries it is not the same as
the number that driver requires in guest, for example, a PCI driver wants
to allocate 6 MSI vecotrs in guest, but as the limitation, i
> From: Klaus Jensen
> Sent: Wednesday, November 9, 2022 12:40 AM
>
> On Oct 21 16:10, clay.may...@kioxia.com wrote:
> > From: Clay Mayers
> >
> > ZNS controllers have the option to limit the time a zone can remain in
> > the active state. It begins with a background process in the controller
>
On Wed, Nov 23, 2022 at 2:07 AM Bin Meng wrote:
>
> sstatus register dump is currently missing in riscv_cpu_dump_state().
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1332
> Signed-off-by: Bin Meng
>
> ---
>
> target/riscv/cpu.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --g
In CPUID registers exposed to userspace, some registers were missing
and some fields were not exposed. This patch aligns exposed ID
registers and their fields with what the upstream kernel currently
exposes.
Specifically, the following new ID registers/fields are exposed to
userspace:
ID_AA64PFR
On 22/11/22 21:57, Richard Henderson wrote:
Create a couple of wrappers for locking/unlocking the iothread lock.
Signed-off-by: Richard Henderson
---
include/qemu/main-loop.h | 39 +++
1 file changed, 39 insertions(+)
+#define QEMU_IOTHREAD_LOCK_GUARD(
Reviewed-by: Paolo Bonzini
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
hw/mips/mips_int.c | 37 ++---
1 file changed, 14 insertions(+), 23 deletions(-)
diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c
index 2db5e10fe0..c22598d353
Create a couple of wrappers for locking/unlocking the iothread lock.
Signed-off-by: Richard Henderson
---
include/qemu/main-loop.h | 39 +++
1 file changed, 39 insertions(+)
diff --git a/include/qemu/main-loop.h b/include/qemu/main-loop.h
index 3c9a9a982d..73
The ARM GICv3 TRM describes that the ITLinesNumber field of GICD_TYPER
register:
"indicates the maximum SPI INTID that the GIC implementation supports"
As SPI #0 is absolute IRQ #32, the max SPI INTID should have accounted
for the internal 16x SGI's and 16x PPI's. However, the original GICv3
mod
The ARM GICv3 TRM describes that the ITLinesNumber field of GICD_TYPER
register:
"indicates the maximum SPI INTID that the GIC implementation supports"
As SPI #0 is absolute IRQ #32, the max SPI INTID should have accounted
for the internal 16x SGI's and 16x PPI's. However, the original GICv3
mo
In addition, use tcg_enabled instead of !kvm_enabled.
Reviewed-by: Paolo Bonzini
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Richard Henderson
---
target/ppc/helper_regs.c | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
diff -
Simplify the usage of qemu_mutex_lock_iothread.
Split out for ease of review.
Changes for v2:
* Add WITH_QEMU_IOTHREAD_LOCK and use it a couple of places.
This re-implements patch 1, so r-b's dropped.
r~
Richard Henderson (7):
qemu/main-loop: Introduce QEMU_IOTHREAD_LOCK_GUARD,
WITH
Please disregard this one. Sent in error.
On 11/22/2022 2:18 PM, Luke Starrett wrote:
The ARM GICv3 TRM describes that the ITLinesNumber field of GICD_TYPER
register:
"indicates the maximum SPI INTID that the GIC implementation supports"
As SPI #0 is absolute IRQ #32, the max SPI INTID should
Narrow the scope of the lock to the actual read/write,
moving the cpu_transation_failed call outside the lock.
Reviewed-by: Paolo Bonzini
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 23 ++-
1 file changed, 6 insertions(+), 1
Reviewed-by: Paolo Bonzini
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/cpu_helper.c | 22 +++---
1 file changed, 7 insertions(+), 15 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_h
Reviewed-by: Paolo Bonzini
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Richard Henderson
---
hw/ppc/ppc.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index dc86c1c7db..4e816c68c7 100644
--
Reviewed-by: Paolo Bonzini
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Richard Henderson
---
target/ppc/excp_helper.c | 11 +--
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
On 22/11/22 2:53 pm, Daniel P. Berrangé wrote:
On Mon, Nov 21, 2022 at 01:40:27PM +0100, Juan Quintela wrote:
Het Gala wrote:
To prevent double data encoding of uris, instead of passing transport
mechanisms, host address and port all together in form of a single string
and writing different
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
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Description: PGP signature
On Tue, Nov 22, 2022 at 06:53:49PM +0400, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau
>
> 851d6d1a0f ("vfio/common: remove spurious tpm-crb-cmd misalignment
> warning") removed the warning on vfio_listener_region_add() path.
>
> An error is reported for vhost-vdpa case:
> qemu-k
* Juan Quintela (quint...@redhat.com) wrote:
> We split the function into to:
>
> - state_pending_estimate: We estimate the remaining state size without
> stopping the machine.
>
> - state pending_exact: We calculate the exact amount of remaining
> state.
>
> The only "device" that implement
On 21/11/22 6:10 pm, Juan Quintela wrote:
Het Gala wrote:
To prevent double data encoding of uris, instead of passing transport
mechanisms, host address and port all together in form of a single string
and writing different parsing functions, we intend the user to explicitly
mention most of t
On 11/22/2022 10:12 AM -0800, Richard Henderson wrote:
> On 11/21/22 18:48, Zhuojia Shen wrote:
> > In CPUID registers exposed to userspace, some registers were missing
> > and some fields were not exposed. This patch aligns exposed ID
> > registers and their fields with what Linux exposes current
On 11/22/2022 06:26 PM +, Peter Maydell wrote:
> On Tue, 22 Nov 2022 at 03:05, Zhuojia Shen
> wrote:
> >
> > In CPUID registers exposed to userspace, some registers were missing
> > and some fields were not exposed. This patch aligns exposed ID
> > registers and their fields with what Linux
On Mon, Nov 21, 2022 at 11:32:13AM +0100, Gerd Hoffmann wrote:
> Current seabios code will only enable and use the 64bit pci io window in
> case it runs out of space in the 32bit pci mmio window below 4G.
>
> This patch will also enable the 64bit pci io window when
> (a) RAM above 4G is present,
On 22/11/22 19:21, Philippe Mathieu-Daudé wrote:
On 18/11/22 10:47, Richard Henderson wrote:
Adding a vector type will make it easier to handle i386
have_atomic16 via AVX.
Signed-off-by: Richard Henderson
---
include/qemu/int128.h | 10 +-
1 file changed, 5 insertions(+), 5 deletion
On Tue, 22 Nov 2022 at 03:05, Zhuojia Shen wrote:
>
> In CPUID registers exposed to userspace, some registers were missing
> and some fields were not exposed. This patch aligns exposed ID
> registers and their fields with what Linux exposes currently.
>
> Specifically, the following new ID regist
On 18/11/22 10:47, Richard Henderson wrote:
Adding a vector type will make it easier to handle i386
have_atomic16 via AVX.
Signed-off-by: Richard Henderson
---
include/qemu/int128.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/qemu/int128.h b/include
On 11/22/22 10:14, Philippe Mathieu-Daudé wrote:
I'd feel safer if we assign TCG_TYPE_I32 .. TCG_TYPE_V256 in TCGType,
just in case.
What do you mean?
-- >8 --
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
@@ -289,8 +289,8 @@ typedef struct TCGPool {
typedef enum TCGType {
- TCG_TYP
On 22/11/22 17:54, Richard Henderson wrote:
On 11/22/22 03:30, Philippe Mathieu-Daudé wrote:
On 11/11/22 08:40, Richard Henderson wrote:
Add a helper function for computing the size of a type.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 16
tcg/tcg.c |
On 11/21/22 18:48, Zhuojia Shen wrote:
In CPUID registers exposed to userspace, some registers were missing
and some fields were not exposed. This patch aligns exposed ID
registers and their fields with what Linux exposes currently.
Specifically, the following new ID registers/fields are expose
Signed-off-by: Richard Henderson
Message-Id: <2022074101.2069454-27-richard.hender...@linaro.org>
[PMD: Split from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé
---
tcg/tcg.c | 83 +--
1 file changed, 44 insertions(+), 39 deletions(-)
In the unlikely case of invalid typecode mask, the function
will abort instead of returning a NULL pointer.
Signed-off-by: Richard Henderson
Message-Id: <2022074101.2069454-27-richard.hender...@linaro.org>
[PMD: Split from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé
---
tcg/tcg.c |
From: Richard Henderson
Instead of requiring a separate hash table lookup,
put a pointer to the CIF into TCGHelperInfo.
Signed-off-by: Richard Henderson
Message-Id: <2022074101.2069454-27-richard.hender...@linaro.org>
[PMD: Split from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé
---
Hi Richard,
Your "Move ffi_cif pointer into TCGHelperInfo" patch was
not obvious (to me) at first, so I split it in 3 trivial
patches.
Philippe Mathieu-Daudé (2):
tcg: Convert typecode_to_ffi from array to function
tcg: Factor init_ffi_layouts() out of tcg_context_init()
Richard Henderson (1
On 11/22/22 06:35, Peter Maydell wrote:
+/*
+ * Here we have the architectural atomicity of the operation.
+ * However, when executing in a serial context, we need no extra
+ * host atomicity in order to avoid racing. This reduction
+ * avoids looping with cpu_loop_exit_atomi
On Tue, Nov 22, 2022 at 4:13 AM Jason Wang wrote:
>
> On Mon, Nov 21, 2022 at 6:11 PM Stefano Garzarella
> wrote:
> >
> > Commit 69e1c14aa2 ("virtio: core: vq reset feature negotation support")
> > enabled VIRTIO_F_RING_RESET by default for all virtio devices.
> >
> > This feature is not current
* Juan Quintela (quint...@redhat.com) wrote:
> So remove it everywhere.
>
> Signed-off-by: Juan Quintela
Reviewed-by: Dr. David Alan Gilbert
> ---
> include/migration/register.h | 6 ++
> migration/savevm.h | 2 +-
> hw/s390x/s390-stattrib.c | 2 +-
> hw/vfio/migration
On Tue, Nov 22, 2022 at 12:16:08PM -0500, Peter Xu wrote:
> On Tue, Nov 22, 2022 at 10:12:25PM +0530, manish.mishra wrote:
> >
> > On 22/11/22 10:03 pm, Peter Xu wrote:
> > > On Tue, Nov 22, 2022 at 11:29:05AM -0500, Peter Xu wrote:
> > > > On Tue, Nov 22, 2022 at 11:10:18AM -0500, Peter Xu wrote:
On Tue, Nov 22, 2022 at 09:13:44AM +0100, Klaus Jensen wrote:
> There are several bugs in the async cancel code for the Format command.
>
> Firstly, cancelling a format operation neglects to set iocb->ret as well
> as clearing the iocb->aiocb after cancelling the underlying aiocb which
> causes th
On Tue, Nov 22, 2022 at 10:12:25PM +0530, manish.mishra wrote:
>
> On 22/11/22 10:03 pm, Peter Xu wrote:
> > On Tue, Nov 22, 2022 at 11:29:05AM -0500, Peter Xu wrote:
> > > On Tue, Nov 22, 2022 at 11:10:18AM -0500, Peter Xu wrote:
> > > > On Tue, Nov 22, 2022 at 09:01:59PM +0530, manish.mishra wro
On Mon, Nov 14, 2022 at 08:20:10PM +0100, Marek Marczykowski-Górecki wrote:
> diff --git a/hw/xen/xen_pt.c b/hw/xen/xen_pt.c
> index 0ec7e52183..269bd26109 100644
> --- a/hw/xen/xen_pt.c
> +++ b/hw/xen/xen_pt.c
> @@ -255,6 +255,7 @@ static void xen_pt_pci_write_config(PCIDevice *d,
> uint32_t addr
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
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Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
signature.asc
Description: PGP signature
On Nov 21 22:02, Alex Bennée wrote:
>
> Aaron Lindsay writes:
>
> > Sorry, left off the very end of my timeline:
> >
> > On Nov 18 16:58, Aaron Lindsay wrote:
> >> I have, so far, discovered the following timeline:
> >> 1. My plugin receives a instruction execution callback for a load
> >>in
On Tue, Nov 22, 2022 at 09:27:52PM +0530, manish.mishra wrote:
>
> On 22/11/22 2:53 pm, Daniel P. Berrangé wrote:
> > For our future sanity I think we need to define a brand new migration
> > protocol which is bidirectional from the start. A large number of the
> > MigrateParameters would become o
On 11/22/22 03:30, Philippe Mathieu-Daudé wrote:
On 11/11/22 08:40, Richard Henderson wrote:
Add a helper function for computing the size of a type.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 16
tcg/tcg.c | 26 --
2 files chan
On Tue, Nov 22, 2022 at 3:53 PM wrote:
>
> From: Marc-André Lureau
>
> 851d6d1a0f ("vfio/common: remove spurious tpm-crb-cmd misalignment
> warning") removed the warning on vfio_listener_region_add() path.
>
> An error is reported for vhost-vdpa case:
> qemu-kvm: vhost_vdpa_listener_region_add re
On 22/11/22 10:03 pm, Peter Xu wrote:
On Tue, Nov 22, 2022 at 11:29:05AM -0500, Peter Xu wrote:
On Tue, Nov 22, 2022 at 11:10:18AM -0500, Peter Xu wrote:
On Tue, Nov 22, 2022 at 09:01:59PM +0530, manish.mishra wrote:
On 22/11/22 8:19 pm, Daniel P. Berrangé wrote:
On Tue, Nov 22, 2022 at 09:
From: Ard Biesheuvel
The LPA2 extension implements 52-bit virtual addressing for 4k and 16k
translation granules, and for the former, this means an additional level
of translation is needed. This means we start counting at -1 instead of
0 when doing a walk, and so 'level' is now a signed quantity
tags/pull-target-arm-20221122
for you to fetch changes up to 15f8f4671afd22491ce99d28a296514717fead4f:
target/arm: Use signed quantity to represent VMSAv8-64 translation level
(2022-11-22 16:10:25 +)
target-arm:
* Fix brok
In get_phys_addr_with_struct(), we call get_phys_addr_twostage() if
the CPU supports EL2. However, we don't check here that stage 2 is
actually enabled. Instead we only check that inside
get_phys_addr_twostage() to skip stage 2 translation. This means
that even if stage 2 is disabled we still te
On Tue, Nov 22, 2022 at 11:29:05AM -0500, Peter Xu wrote:
> On Tue, Nov 22, 2022 at 11:10:18AM -0500, Peter Xu wrote:
> > On Tue, Nov 22, 2022 at 09:01:59PM +0530, manish.mishra wrote:
> > >
> > > On 22/11/22 8:19 pm, Daniel P. Berrangé wrote:
> > > > On Tue, Nov 22, 2022 at 09:41:01AM -0500, Pete
On Tue, Nov 22, 2022 at 11:10:18AM -0500, Peter Xu wrote:
> On Tue, Nov 22, 2022 at 09:01:59PM +0530, manish.mishra wrote:
> >
> > On 22/11/22 8:19 pm, Daniel P. Berrangé wrote:
> > > On Tue, Nov 22, 2022 at 09:41:01AM -0500, Peter Xu wrote:
> > > > On Tue, Nov 22, 2022 at 02:38:53PM +0530, manish
Hi,
On 11/22/22 10:43, Michael S. Tsirkin wrote:
> On Tue, Nov 22, 2022 at 11:01:11AM +0800, Jason Wang wrote:
>> When vIOMMU is enabled, the vq->used_phys is actually the IOVA not
>> GPA. So we need to translate it to GPA before the syncing otherwise we
>> may hit the following crash since IOVA c
On Tue, 22 Nov 2022 at 15:55, Ard Biesheuvel wrote:
>
> The LPA2 extension implements 52-bit virtual addressing for 4k and 16k
> translation granules, and for the former, this means an additional level
> of translation is needed. This means we start counting at -1 instead of
> 0 when doing a walk,
On Tue, Nov 22, 2022 at 09:01:59PM +0530, manish.mishra wrote:
>
> On 22/11/22 8:19 pm, Daniel P. Berrangé wrote:
> > On Tue, Nov 22, 2022 at 09:41:01AM -0500, Peter Xu wrote:
> > > On Tue, Nov 22, 2022 at 02:38:53PM +0530, manish.mishra wrote:
> > > > On 22/11/22 2:30 pm, Daniel P. Berrangé wrote
Hi Marc-André,
On 11/22/22 15:53, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau
>
> 851d6d1a0f ("vfio/common: remove spurious tpm-crb-cmd misalignment
> warning") removed the warning on vfio_listener_region_add() path.
>
> An error is reported for vhost-vdpa case:
> qemu-kvm: vhost_
sstatus register dump is currently missing in riscv_cpu_dump_state().
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1332
Signed-off-by: Bin Meng
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d14e95c9dc..80d76f
On 22/11/22 2:53 pm, Daniel P. Berrangé wrote:
On Mon, Nov 21, 2022 at 01:40:27PM +0100, Juan Quintela wrote:
Het Gala wrote:
To prevent double data encoding of uris, instead of passing transport
mechanisms, host address and port all together in form of a single string
and writing different
On Nov 21 18:22, Richard Henderson wrote:
> On 11/21/22 13:51, Alex Bennée wrote:
> >
> > Aaron Lindsay writes:
> >
> > > On Nov 15 22:36, Alex Bennée wrote:
> > > > Aaron Lindsay writes:
> > > > > I believe the code *should* always reset `cpu->plugin_mem_cbs` to
> > > > > NULL at the
> > > >
The LPA2 extension implements 52-bit virtual addressing for 4k and 16k
translation granules, and for the former, this means an additional level
of translation is needed. This means we start counting at -1 instead of
0 when doing a walk, and so 'level' is now a signed quantity, and should
be typed a
On Tue, 22 Nov 2022 at 14:21, Peter Maydell wrote:
>
> On Mon, 21 Nov 2022 at 19:02, Ard Biesheuvel wrote:
> >
> > On Mon, 21 Nov 2022 at 19:51, Peter Maydell
> > wrote:
> > >
> > > On Mon, 21 Nov 2022 at 17:43, Ard Biesheuvel wrote:
> > > >
> > > > The LPA2 extension implements 52-bit virtual
BALATON Zoltan writes:
> On Tue, 22 Nov 2022, Markus Armbruster wrote:
>> Tweak the semantic patch to drop redundant parenthesis around the
>> return expression.
>>
>> Coccinelle drops a comment in hw/rdma/vmw/pvrdma_cmd.c; restored
>> manually.
>>
>> Coccinelle messes up vmdk_co_create(), not su
On 22/11/22 8:19 pm, Daniel P. Berrangé wrote:
On Tue, Nov 22, 2022 at 09:41:01AM -0500, Peter Xu wrote:
On Tue, Nov 22, 2022 at 02:38:53PM +0530, manish.mishra wrote:
On 22/11/22 2:30 pm, Daniel P. Berrangé wrote:
On Sat, Nov 19, 2022 at 09:36:14AM +, manish.mishra wrote:
MSG_PEEK reads
On 11/11/22 08:40, Richard Henderson wrote:
We will shortly have the possibility of more that two outputs,
though only for calls (for which preferences are moot). Avoid
direct references to op->output_pref[] when possible.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 5 +
t
On 11/11/22 08:40, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/tci.c| 1 -
tcg/tci/tcg-target.c.inc | 4
2 files changed, 5 deletions(-)
Since commit 7b7d8b2d9a ("tcg/tci: Use ffi for calls")?
Reviewed-by: Philippe Mathieu-Daudé
On 11/11/22 08:40, Richard Henderson wrote:
Better to re-use the existing function for copying ops.
Signed-off-by: Richard Henderson
---
accel/tcg/plugin-gen.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 11/11/22 08:40, Richard Henderson wrote:
We copied all of the arguments in copy_op_nocheck.
We only need to replace the one argument that we change.
Signed-off-by: Richard Henderson
---
accel/tcg/plugin-gen.c | 2 --
1 file changed, 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 22/11/22 15:53, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
851d6d1a0f ("vfio/common: remove spurious tpm-crb-cmd misalignment
warning") removed the warning on vfio_listener_region_add() path.
An error is reported for vhost-vdpa case:
qemu-kvm: vhost_vdpa_listener_region_add
On Tue, 22 Nov 2022 at 15:04, Philippe Mathieu-Daudé wrote:
>
> On 21/11/22 17:42, Max Filippov wrote:
> > On Mon, Nov 21, 2022 at 6:01 AM Markus Armbruster wrote:
> >> .../xtensa/core-dsp3400/xtensa-modules.c.inc | 136 +-
> >> target/xtensa/core-lx106/xtensa-modules.c.inc |
On 22/11/22 14:49, Markus Armbruster wrote:
Tweak the semantic patch to drop redundant parenthesis around the
return expression.
Coccinelle drops a comment in hw/rdma/vmw/pvrdma_cmd.c; restored
manually.
Coccinelle messes up vmdk_co_create(), not sure why. Change dropped,
will be done manually
On 22/11/22 14:49, Markus Armbruster wrote:
Cc: Fam Zheng
Cc: Kevin Wolf
Cc: Hanna Reitz
Cc: qemu-bl...@nongnu.org
Signed-off-by: Markus Armbruster
---
block/vmdk.c | 28 +++-
1 file changed, 11 insertions(+), 17 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 21/11/22 17:42, Max Filippov wrote:
On Mon, Nov 21, 2022 at 6:01 AM Markus Armbruster wrote:
.../xtensa/core-dsp3400/xtensa-modules.c.inc | 136 +-
target/xtensa/core-lx106/xtensa-modules.c.inc | 16 +--
These files are generated and were imported from xtensa configurat
From: Marc-André Lureau
851d6d1a0f ("vfio/common: remove spurious tpm-crb-cmd misalignment
warning") removed the warning on vfio_listener_region_add() path.
An error is reported for vhost-vdpa case:
qemu-kvm: vhost_vdpa_listener_region_add received unaligned region
Skip the CRB device.
Fixes:
On 22/11/22 09:58, Markus Armbruster wrote:
Thomas Huth writes:
On 21/11/2022 17.32, Markus Armbruster wrote:
Philippe Mathieu-Daudé writes:
On 21/11/22 15:36, Peter Maydell wrote:
On Mon, 21 Nov 2022 at 14:03, Markus Armbruster wrote:
Tweak the semantic patch to drop redundant parenth
On Tue, Nov 22, 2022 at 09:41:01AM -0500, Peter Xu wrote:
> On Tue, Nov 22, 2022 at 02:38:53PM +0530, manish.mishra wrote:
> >
> > On 22/11/22 2:30 pm, Daniel P. Berrangé wrote:
> > > On Sat, Nov 19, 2022 at 09:36:14AM +, manish.mishra wrote:
> > > > MSG_PEEK reads from the peek of channel, Th
On Mon, 21 Nov 2022 at 15:08, Timofey Kutergin wrote:
>
> cortex-a55 is one of newer armv8.2+ CPUs supporting native
> Privileged Access Never (PAN) feature. Using this CPU
> provides access to this feature without using fictitious "max"
> CPU.
>
> Signed-off-by: Timofey Kutergin
Thanks;
On Tue, Nov 22, 2022 at 02:38:53PM +0530, manish.mishra wrote:
>
> On 22/11/22 2:30 pm, Daniel P. Berrangé wrote:
> > On Sat, Nov 19, 2022 at 09:36:14AM +, manish.mishra wrote:
> > > MSG_PEEK reads from the peek of channel, The data is treated as
> > > unread and the next read shall still retu
On Fri, 18 Nov 2022 at 09:50, Richard Henderson
wrote:
>
> Create ldst_atomicity.c.inc.
>
> Not required for user-only code loads, because we've ensured that
> the page is read-only before beginning to translate code.
>
> Signed-off-by: Richard Henderson
> +/**
> + * required_atomicity:
> + *
>
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