[PULL 2/4] target/i386: introduce function to set rounding mode from FPCW or MXCSR bits

2022-10-22 Thread Paolo Bonzini
VROUND, FSTCW and STMXCSR all have to perform the same conversion from x86 rounding modes to softfloat constants. Since the ISA is consistent on the meaning of the two-bit rounding modes, extract the common code into a wrapper for set_float_rounding_mode. Reviewed-by: Philippe Mathieu-Daudé Revi

[PULL 4/4] target/i386: implement FMA instructions

2022-10-22 Thread Paolo Bonzini
The only issue with FMA instructions is that there are _a lot_ of them (30 opcodes, each of which comes in up to 4 versions depending on VEX.W and VEX.L; a total of 96 possibilities). However, they can be implement with only 6 helpers, two for scalar operations and four for packed operations. (Sca

[PULL 3/4] target/i386: implement F16C instructions

2022-10-22 Thread Paolo Bonzini
F16C only consists of two instructions, which are a bit peculiar nevertheless. First, they access only the low half of an YMM or XMM register for the packed-half operand; the exact size still depends on the VEX.L flag. This is similar to the existing avx_movx flag, but not exactly because avx_movx

[PULL 1/4] target/i386: decode-new: avoid out-of-bounds access to xmm_regs[-1]

2022-10-22 Thread Paolo Bonzini
If the destination is a memory register, op->n is -1. Going through tcg_gen_gvec_dup_imm path is both useless (the value has been stored by the gen_* function already) and wrong because of the out-of-bounds access. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by

[PULL 0/4] x86 TCG patches for 2022-10-22

2022-10-22 Thread Paolo Bonzini
The following changes since commit 214a8da23651f2472b296b3293e619fd58d9e212: Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2022-10-18 11:14:31 -0400) are available in the Git repository at: https://gitlab.com/bonzini/qemu.git tags/for-upstream for you to fetch c

Re: [PATCH 1/3] accel/tcg: Add a quicker check for breakpoints

2022-10-22 Thread Richard Henderson
On 10/22/22 03:01, Leandro Lupori wrote: Profiling QEMU during Fedora 35 for PPC64 boot revealed that a considerable amount of time was being spent in check_for_breakpoints() (0.61% of total time on PPC64 and 2.19% on amd64), even though it was just checking that its queue was empty and returning

Re: [PATCH v6 00/10] Introduce new acpi/smbios avocado tests using biosbits

2022-10-22 Thread Ani Sinha
On Fri, Oct 21, 2022 at 9:32 PM Alex Bennée wrote: > > Ani Sinha writes: > > > On Fri, 21 Oct, 2022, 5:52 pm Ani Sinha, wrote: > > > > On Fri, 21 Oct, 2022, 5:26 pm Alex Bennée, > wrote: > > > > Ani Sinha writes: > > > > > On Fri, Oct 21, 2022 at 3:10 PM Michael S. Tsirkin > wrote: > > >

[PULL 2/2] m68k: write bootinfo as rom section and re-randomize on reboot

2022-10-22 Thread Laurent Vivier
From: "Jason A. Donenfeld" Rather than poking directly into RAM, add the bootinfo block as a proper ROM, so that it's restored when rebooting the system. This way, if the guest corrupts any of the bootinfo items, but then tries to reboot, it'll still be restored back to normal as expected. Then,

[PULL 1/2] m68k: rework BI_VIRT_RNG_SEED as BI_RNG_SEED

2022-10-22 Thread Laurent Vivier
From: "Jason A. Donenfeld" Following a change on the kernel side (see link), pass BI_RNG_SEED instead of BI_VIRT_RNG_SEED. This should have no impact on compatibility, as there will simply be no effect if it's an old kernel, which is how things have always been. We then use this as an opportunity

Re: [PATCH] Revert "accel/tcg: Init TCG cflags in vCPU thread handler"

2022-10-22 Thread Richard Henderson
On 10/22/22 02:34, Peter Maydell wrote: Commit a82fd5a4ec24d was intended to be a code cleanup, but unfortunately it has a bug. It moves the initialization of the TCG cflags from the "start a new vcpu" function to the thread handler; this is fine when each vcpu has its own thread, but when we are

[PATCH] tcg/riscv: Fix range matched by TCG_CT_CONST_M12

2022-10-22 Thread Richard Henderson
We were matching a signed 13-bit range, not a 12-bit range. Expand the commentary within the function and be explicit about all of the ranges. Reported-by: LIU Zhiwei Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 19 --- 1 file changed, 16 insertions(+), 3 de

Re: [PATCH] Revert "accel/tcg: Init TCG cflags in vCPU thread handler"

2022-10-22 Thread Richard Henderson
On 10/22/22 02:34, Peter Maydell wrote: Commit a82fd5a4ec24d was intended to be a code cleanup, but unfortunately it has a bug. It moves the initialization of the TCG cflags from the "start a new vcpu" function to the thread handler; this is fine when each vcpu has its own thread, but when we are

Re: [PATCH v2] target/i386: Fix caculation of LOCK NEG eflags

2022-10-22 Thread Richard Henderson
On 10/22/22 16:12, Qi Hu wrote: In sequence: --- lock negl -0x14(%rbp) pushf pop%rax --- %rax will obtain the wrong value becasue the "lock neg" caculates the wrong eflags. The "s->T0" is updated by the wrong value. You can use this to do some test: --- #include int main() { __volatile

[PULL 0/2] M68k for 7.2 patches

2022-10-22 Thread Laurent Vivier
u-m68k.git tags/m68k-for-7.2-pull-request for you to fetch changes up to d3c7b59be912d257ae7773eb3f1127f81a710a4d: m68k: write bootinfo as rom section and re-randomize on reboot (2022-10-22 09:58:24 +0200) Pull request m68k branc

Re: [PATCH v4] m68k: write bootinfo as rom section and re-randomize on reboot

2022-10-22 Thread Richard Henderson
On Sat, 22 Oct 2022, 08:33 Laurent Vivier, wrote: > Le 17/10/2022 à 22:29, Jason A. Donenfeld a écrit : > > > Notes: > - don't send your patch as a reply to a previous version > - add an history: > > v4: replace (void *)(((unsigned long)base + 3) & ~3) by > (void *)(((uintptr_t)bas