When QEMU is started with `-daemonize`, all stdio descriptors get
redirected to `/dev/null`. This basically means that anything
printed with `error_report()` and friends is lost.
One could hope that passing `-D ${logfile}` would cause the messages
to go to `${logfile}`, as the documentation tends
On Fri, Oct 14, 2022 at 09:01:02AM +0800, Zeng Guang wrote:
> PING again !
> This QEMU patch is to optimize max APIC ID set for current VM session
> introduced since linux v6.0. It's also compatible with previous linux
> version.
>
> Thanks.
>
> On 9/5/2022 9:27 AM, Zeng Guang wrote:
> > Kindly P
I also came across the Interrupt Coalescing feature in NVMe (5.21.1.8 in
Spec 1.4c). It seems to suggest an algorithm based on thresholds for the
maximum interrupt delay time and minimum number of coalesced interrupts.
Klaus, based on your experience, how does this algorithm work? Is is
commonly u
On Wed, Oct 12, 2022 at 11:15 AM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> Since commit 4047368938f6 "accel/tcg: Introduce tlb_set_page_full" we
> have been seeing this assert
>
> ../accel/tcg/cputlb.c:1294: tlb_set_page_with_attrs: Assertion
> `is_power_of_2(size)' failed.
>
>
Similar to the ARM64, LoongArch has PC-relative instructions such as
PCADDU18I. These instructions can be used to support direct jump for
LoongArch. Additionally, if instruction "B offset" can cover the target
address(target is within ±128MB range), a single "B offset" plus a nop
will be used by "t
On 2022/10/14 02:52, Richard Henderson wrote:
On 10/13/22 20:01, Qi Hu wrote:
Similar to the ARM64, LoongArch has PC-relative instructions such as
PCADDU18I. These instructions can be used to support direct jump for
LoongArch. Additionally, if instruction "B offset" can cover the target
addres
On Thu, Oct 13, 2022 at 10:48 PM Michael S. Tsirkin wrote:
>
> On Thu, Oct 13, 2022 at 04:00:57PM +0200, Laurent Vivier wrote:
> > When virtio-net is used with the socket netdev backend, the backend
> > can be busy and not able to collect new packets.
> >
> > In this case, net_socket_receive() ret
When the system reboots, the rng-seed that the FDT has should be
re-randomized, so that the new boot gets a new seed. Since the FDT is in
the ROM region at this point, we add a hook right after the ROM has been
added, so that we have a pointer to that copy of the FDT.
Cc: Aleksandar Rikalo
Cc: Pa
When the system reboots, the rng-seed that the FDT has should be
re-randomized, so that the new boot gets a new seed. Since the FDT is in
the ROM region at this point, we add a hook right after the ROM has been
added, so that we have a pointer to that copy of the FDT.
Cc: Peter Maydell
Cc: qemu-.
When the system reboots, the rng-seed that the FDT has should be
re-randomized, so that the new boot gets a new seed. Since the FDT is in
the ROM region at this point, we add a hook right after the ROM has been
added, so that we have a pointer to that copy of the FDT.
Cc: Stafford Horne
Signed-of
When the system reboots, the rng-seed that the FDT has should be
re-randomized, so that the new boot gets a new seed. Since the FDT is in
the ROM region at this point, we add a hook right after the ROM has been
added, so that we have a pointer to that copy of the FDT.
Cc: Yoshinori Sato
Signed-of
When the system reboots, the rng-seed that the FDT has should be
re-randomized, so that the new boot gets a new seed. Several
architectures require this functionality, so export a function for
injecting a new seed into the given FDT.
Cc: Alistair Francis
Cc: David Gibson
Signed-off-by: Jason A.
Snapshot loading only expects to call deterministic handlers, not
non-deterministic ones. So introduce a way of registering handlers that
won't be called when reseting for snapshots.
Signed-off-by: Jason A. Donenfeld
---
hw/arm/aspeed.c| 4 ++--
hw/arm/mps2-tz.c | 4 ++--
When the system reboots, the rng seed that QEMU passes should be
re-randomized, so that the new boot gets a new seed. This series wires
that up for FDT.
Then, since the record&replay subsystem makes use of reset as well, we
add a new reset cause for record&replay, so that we can avoid
re-randomizi
When the system reboots, the rng-seed that the FDT has should be
re-randomized, so that the new boot gets a new seed. Since the FDT is in
the ROM region at this point, we add a hook right after the ROM has been
added, so that we have a pointer to that copy of the FDT.
Cc: Palmer Dabbelt
Cc: Alist
Snapshot loading is supposed to be deterministic, so we shouldn't
re-randomize the various seeds used.
Signed-off-by: Jason A. Donenfeld
---
hw/i386/x86.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 1148f70c03..bd50a064a3 100644
--- a/h
On Fri, Oct 14, 2022 at 05:13:58AM +1100, Richard Henderson wrote:
> On 10/12/22 13:46, Jason A. Donenfeld wrote:
> > When the system reboots, the rng seed that QEMU passes should be
> > re-randomized, so that the new boot gets a new seed. This series wires
> > that up for FDT.
> >
> > Then, since
PING again !
This QEMU patch is to optimize max APIC ID set for current VM session
introduced since linux v6.0. It's also compatible with previous linux
version.
Thanks.
On 9/5/2022 9:27 AM, Zeng Guang wrote:
Kindly PING!
On 8/25/2022 10:52 AM, Zeng Guang wrote:
Specify maximum possible AP
On Tue, Oct 11, 2022 at 11:07:59AM +0100, Jonathan Cameron wrote:
> On Mon, 10 Oct 2022 15:29:41 -0700
> ira.we...@intel.com wrote:
>
> > From: Ira Weiny
> >
> > To facilitate testing of guest software add mock events and code to
> > support iterating through the event logs.
> >
> > Signed-off-
Context included below from prior discussion
- `cxl create-region` would fail on inability to allocate memory
- traced this down to the memory region being marked RESERVED
- E820 map marks the CXL fixed memory window as RESERVED
Re: x86 errors, I found that region worked with this pat
Jason,
On 10/12/2022 10:02 PM, Jason Wang wrote:
在 2022/10/12 13:59, Si-Wei Liu 写道:
On 10/11/2022 8:09 PM, Jason Wang wrote:
On Tue, Oct 11, 2022 at 1:18 AM Si-Wei Liu
wrote:
On 10/8/2022 10:43 PM, Jason Wang wrote:
On Sat, Oct 8, 2022 at 5:04 PM Si-Wei Liu
wrote:
Similar to other vh
On Tue, Oct 11, 2022 at 10:13:17AM +0100, Jonathan Cameron wrote:
> On Mon, 10 Oct 2022 15:29:40 -0700
> ira.we...@intel.com wrote:
>
> > From: Ira Weiny
> >
> > UUID's are defined as network byte order fields. No static initializer
> > was available for UUID's in their standard big endian form
On Tue, Oct 11, 2022 at 10:03:00AM +0100, Jonathan Cameron wrote:
> On Mon, 10 Oct 2022 15:29:39 -0700
> ira.we...@intel.com wrote:
>
> > From: Ira Weiny
> >
> > Gcc requires constant versions of cpu_to_le* calls.
> >
> > Add a 64 bit version.
> >
> > Signed-off-by: Ira Weiny
>
> Seems reaso
On Tue, Oct 11, 2022 at 04:45:57PM +0100, Peter Maydell wrote:
> On Tue, 11 Oct 2022 at 16:22, Richard Henderson
> wrote:
> > On 10/11/22 02:48, Peter Maydell wrote:
> > > This is kind of a weird API, because:
> > > * it only exists for little-endian, not big-endian
> > > * we use it in exactl
On Wed, Sep 28, 2022 at 5:06 AM dinglimin
wrote:
>
> Jump statements, such as return and continue let you
> change the default flow of program execution,
> but jump statements that direct the control flow to
> the original direction are just a waste of keystrokes.
>
> Signed-off-by: dinglimin
> -
Extracted from a patch by Paul Brook .
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
tests/tcg/i386/Makefile.target | 2 +-
tests/tcg/i386/test-avx.c | 201 ++---
tests/tcg/i386/test-avx.py | 5 +-
3 files changed, 113 insertions(+), 95
From: Paul Brook
Include AVX, AVX2 and VAES in the guest cpuid features supported by TCG.
Signed-off-by: Paul Brook
Message-Id: <20220424220204.2493824-40-p...@nowt.org>
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.c | 10 +-
1 file changed, 5 inser
With all SSE (and AVX!) instructions now implemented in disas_insn_new,
it's possible to remove gen_sse, as well as the helpers for instructions
that now use gvec.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/ops_sse.h| 124 ---
target/i386/ops_sse_he
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/fpu_helper.c | 78 ++--
1 file changed, 75 insertions(+), 3 deletions(-)
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
index 5f3f7a1085..7670739abe 100644
-
On Fri, Jul 29, 2022 at 3:01 PM Alberto Faria wrote:
> Performance isn't great, but with some more optimization, the analyzer
> should be fast enough to be used iteratively during development, given
> that it avoids reanalyzing unmodified translation units, and that users
> can restrict the set of
Here the code is a bit uglier due to the truncation and extension
of registers to and from 32-bit. There is also a mistake in the
manual with respect to the size of the memory operand of CVTPS2PI
and CVTTPS2PI, reported by Ricky Zhou.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
The more complicated ones here are d6-d7, e6-e7, f7. The others
are trivial.
For LDDQU, using gen_load_sse directly might corrupt the register if
the second part of the load fails. Therefore, add a custom X86_TYPE_WM
value; like X86_TYPE_W it does call gen_load(), but it also rejects a
value of
This adds another kind of weirdness when you thought you had seen it all:
an opcode byte that comes _after_ the address, not before. It's not
worth adding a new X86_SPECIAL_* constant for it, but it's actually
not unlike VCMP; so, forgive me for exploiting the similarity and just
deciding to dispa
Nothing special going on here, for once.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 5 +++
target/i386/tcg/emit.c.inc | 75
target/i386/tcg/translate.c | 1 +
3 files changed, 81 insertions(+)
There are several special cases here:
1) extending moves have different widths for the helpers vs. for the
memory loads, and the width for memory loads depends on VEX.L too.
This is represented by X86_SPECIAL_AVXExtMov.
2) some instructions, such as variable-width shifts, select the vector elemen
Compared to Paul's implementation, the new decoder will use a different approach
to implement AVX's merging of dst with src1 on scalar operations. Adjust the
helpers to provide this functionality.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/ops_sse.h | 16 ++
These are mostly floating-point SSE operations. The odd ones out
are MOVMSK and CVTxx2yy, the others are straightforward.
Unary operations are a bit special in AVX because they have 2 operands
for PD/PS operands (VEX. must be b), and 3 operands for SD/SS.
They are handled using X86_OP_GRO
Compared to Paul's implementation, the new decoder will use a different approach
to implement AVX's merging of dst with src1 on scalar operations. Adjust the
old SSE decoder to be compatible with new-style helpers.
The affected instructions are CVTSx2Sx, ROUNDSx, RSQRTSx, SQRTSx, RCPSx.
Reviewed
Three-byte opcodes from the 0F3Ah area all have an immediate byte which
is usually unsigned. Clarify in the helper code that it is unsigned;
the new decoder treats immediates as signed by default, and seeing
an intN_t in the prototype might give the wrong impression that one
can use decode->immedi
From: Richard Henderson
As pmovmskb is used by strlen et al, this is the third
highest overhead sse operation at %0.8.
Signed-off-by: Richard Henderson
[Reorganize to generate code for any vector size. - Paolo]
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/emit.c.inc | 88 +
The more complicated operations here are insertions and extractions.
Otherwise, there are just more entries than usual because the PS/PD/SS/SD
variations are encoded in the opcode rater than in the prefixes.
These three-byte opcodes also include AVX new instructions, whose
implementation in the he
Because these are the only VEX instructions that QEMU supports, the
new decoder is entered on the first byte of a valid VEX prefix, and VEX
decoding only needs to be done in decode-new.c.inc.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 59
The new implementation of SSE will cover AVX from the get go, so include
the 24 extra comparison operators that are only available with the VEX
prefix.
Based on a patch by Paul Brook .
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/ops_sse.h| 38 +++
These are exactly the same as the non-VEX version, but one has to be careful
that only VEX.L=0 is allowed.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 25 +
target/i386/tcg/emit.c.inc | 20
These are mostly moves, and yet are a total pain. The main issue
is that:
1) some instructions are selected by mod==11 (register operand)
vs. mod=00/01/10 (memory operand)
2) stores to memory are two-operand operations, while the 3-register
and load-from-memory versions operate on the entire con
This includes shifts by immediate, which use bits 3-5 of the ModRM byte
as an opcode extension. With the exception of 128-bit shifts, they are
implemented using gvec.
This also covers VZEROALL and VZEROUPPER, which use the same opcode
as EMMS. If we were wanting to optimize out gen_clear_ymmh th
These are more simple integer instructions present in both MMX and SSE/AVX,
with no holes that were later occupied by newer instructions.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 28
target/i386/tcg/emit.c.in
The new implementation of SSE will cover AVX from the get go, because
all the work for the helper functions is already done. We just need to
build them.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/helper.h | 2 ++
target/i386/ops_sse.h| 5 +
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 164 ++-
target/i386/tcg/decode-new.h | 32 ++
target/i386/tcg/emit.c.inc | 37 ++-
target/i386/tcg/translate.c | 18 ++--
4 files changed, 239
These are a mixed batch, including the first two horizontal
(66 and F2 only) operations, more moves, and SSE4a extract/insert.
Because SSE4a is pretty rare, I chose to leave the helper as they are,
but it is possible to unify them by loading index and length from the
source XMM register and genera
Add to the helpers all the operands that are needed to implement AVX.
Extracted from a patch by Paul Brook .
Message-Id: <20220424220204.2493824-26-p...@nowt.org>
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/ops_sse.h| 173 +---
On Tue, Sep 27, 2022 at 6:56 AM Peter Maydell wrote:
>
> On Tue, 27 Sept 2022 at 11:12, Jean-Philippe Brucker
> wrote:
> > The node name of the gpio-key devicetree node should be "key-poweroff":
> >
> > gpio-keys: 'poweroff' does not match any of the regexes:
> > '^(button|event|key|switch|(bu
These are both MMX and SSE/AVX instructions, except for vmovdqu. In both
cases the inputs and output is in s->ptr{0,1,2}, so the only difference
between MMX, SSE, and AVX is which helper to call.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc |
From: Paul Brook
Adjust all #ifdefs to match the ones in ops_sse.h.
Signed-off-by: Paul Brook
Message-Id: <20220424220204.2493824-23-p...@nowt.org>
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/ops_sse_header.h | 114 +++
1 file c
From: Paul Brook
Add a new hflag bit to determine whether AVX instructions are allowed
Signed-off-by: Paul Brook
Message-Id: <20220424220204.2493824-4-p...@nowt.org>
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.h| 3 +++
target/i386/helper.c
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 55
target/i386/tcg/decode-new.h | 20
2 files changed, 75 insertions(+)
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-ne
TCG will shortly implement VAES instructions, so add the relevant feature
word to the DisasContext.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/tra
Many SSE and AVX instructions are only valid with specific prefixes
(none, 66, F3, F2). Introduce a direct way to encode this in the
decoding table to avoid using decode groups too much.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 37 +
The new decoder is based on three principles:
- use mostly table-driven decoding, using tables derived as much as possible
from the Intel manual. Centralizing the decode the operands makes it
more homogeneous, for example all immediates are signed. All modrm
handling is in one function, an
Both PC-relative translation blocks and XSAVE state support in linux-user
signal handlers are in; as mentioned in the post of v2, this is the time
for a (mostly) final version of the AVX patches, with more review comments
addressed and a few more bugs fixed.
Paolo
v2->v3:
- removed patches that a
Add generic code generation that takes care of preparing operands
around calls to decode.e.gen in a table-driven manner, so that ALU
operations need not take care of that.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 33 ++-
target/i386
ldq takes a pointer to the first byte to load the 64-bit word in;
ldo takes a pointer to the first byte of the ZMMReg. Make them
consistent, which will be useful in the new SSE decoder's
load/writeback routines.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/tr
From: Richard Henderson
This will be used for emission and endian adjustments of gvec operations.
Signed-off-by: Richard Henderson
Message-Id: <2022083722.1697758-2-richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.h | 56 --
On Tue, Sep 27, 2022 at 6:28 AM Peter Maydell wrote:
>
> On Tue, 27 Sept 2022 at 11:12, Jean-Philippe Brucker
> wrote:
> >
> > The devicetree specification requires that nodes use a generic name
> > where appropriate. Fix the corresponding dt-validate warnings:
>
> Either:
> (1) guests are lookin
On 03/10/2022 23:08, BALATON Zoltan wrote:
On Thu, 29 Sep 2022, Mark Cave-Ayland wrote:
On 25/09/2022 10:16, BALATON Zoltan wrote:
On Sun, 25 Sep 2022, Mark Cave-Ayland wrote:
On 17/09/2022 00:07, BALATON Zoltan wrote:
Some lines can be dropped making the code flow simpler and easier to
foll
Queued, thanks.
Paolo
On Thu, Oct 13, 2022 at 11:31:30PM +0300, Andrey Zhadchenko wrote:
> Although QEMU virtio is quite fast, there is still some room for
> improvements. Disk latency can be reduced if we handle virito-blk requests
> in host kernel istead of passing them to QEMU. The patch adds vhost-blk
> backend whic
On Thu, Oct 13, 2022 at 10:35 PM Alex Bennée wrote:
>
>
> Paolo Bonzini writes:
>
> > Signed-off-by: Paolo Bonzini
> > ---
> > configure | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/configure b/configure
> > index f4ff1cf305..a5af9c524f 100755
> > --- a/configure
> > +++ b/
This conflicts with "hyperv: fix SynIC SINT assertion failure on
guest reset", but the resolution is simply to do the change in a new
function x86_cpu_after_reset(); adjusted and queued, thanks.
Paolo
Queued, thanks.
Paolo
On 10/12/22 22:18, Ilya Leoshkevich wrote:
Add ability to dump /tmp/perf-.map and jit-.dump.
The first one allows the perf tool to map samples to each individual
translation block. The second one adds the ability to resolve symbol
names, line numbers and inspect JITed code.
Example of use:
Queued, thanks.
Paolo
Although QEMU virtio is quite fast, there is still some room for
improvements. Disk latency can be reduced if we handle virito-blk requests
in host kernel istead of passing them to QEMU. The patch adds vhost-blk
backend which sets up vhost-blk kernel module to process requests.
test setup and resu
Paolo Bonzini writes:
> Signed-off-by: Paolo Bonzini
> ---
> configure | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/configure b/configure
> index f4ff1cf305..a5af9c524f 100755
> --- a/configure
> +++ b/configure
> @@ -2474,6 +2474,9 @@ echo "HOST_CC=$host_cc" >> $config_host_ma
Sending second version of this patchset as @stefanha requested.
The main difference from the previous version is added vhost
multithreading support.
Also I must note currently there are several problems which
I intend to reconsider/fix later:
- vmsd is present but migration is not supported
- Bl
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
signature.asc
Description: PGP signature
This avoids the unfortunate effect of building pc-bios blobs
even for targets the user isn't interested in.
Due to the bi-arch nature of x86 and PPC firmware, check for the
desired target by hand, and don't just look for the compilation target
in $target_list.
Signed-off-by: Paolo Bonzini
---
c
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
signature.asc
Description: PGP signature
On 10/13/22 21:48, Alex Bennée wrote:
+ case " $target_list " in
+" $1 ") ;;
+*) return 1 ;;
+ esac
+
this of course prevents building of roms by actually disabling all
target compilers...
Yeah, two asterisks are missing. I'll send out a proper patch.
Paolo
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
signature.asc
Description: PGP signature
On 10/13/22 15:43, Michal Privoznik wrote:
When determining the endiandness of the target architecture we're
building for a small program is compiled, which in an obfuscated
way declares two strings. Then, we look which string is in
correct order (using strings binary) and deduct the endiandness.
Alex Bennée writes:
> This avoids the unfortunate effect of always builds the pc-bios blobs
> for targets the user isn't interested in.
>
> Suggested-by: Paolo Bonzini
> Signed-off-by: Alex Bennée
> ---
> configure | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/configure b/con
> > /* For now, no memory side cache, plausiblish numbers */
> > -*dslbis_nonvolatile1 = (CDATDslbis) {
> > +*dslbis1 = (CDATDslbis) {
> > .header = {
> > .type = CDAT_TYPE_DSLBIS,
> > -.length = sizeof(*dslbis_nonvolatile1),
> > +.length =
On 13.10.2022 19:18, Peter Maydell wrote:
The semantic difference between the deprecated device_legacy_reset()
function and the newer device_cold_reset() function is that the new
function resets both the device itself and any qbuses it owns,
whereas the legacy function resets just the device itse
On 10/14/22 07:52, Philippe Mathieu-Daudé wrote:
+/* Sign extend the displacement with 21 bits. */
+delta = l & 0x1F;
+if (delta & 0x10) {
+delta |= ~0x1F;
+}
delta = sextract32(l, 0, 21);
r~
Make list traversal work when a callback removes a notifier
mid-traversal. This is a cleanup to prevent bugs in the future.
Signed-off-by: Stefan Hajnoczi
Reviewed-by: David Hildenbrand
---
hw/core/numa.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/core/numa.
Emulated devices and other BlockBackend users wishing to take advantage
of blk_register_buf() all have the same repetitive job: register
RAMBlocks with the BlockBackend using RAMBlockNotifier.
Add a BlockRAMRegistrar API to do this. A later commit will use this
from hw/block/virtio-blk.c.
Signed-
Registering an I/O buffer is only a performance optimization hint but it
is still necessary to return errors when it fails.
Later patches will need to detect errors when registering buffers but an
immediate advantage is that error_report() calls are no longer needed in
block driver .bdrv_register_
Block drivers may optimize I/O requests accessing buffers previously
registered with bdrv_register_buf(). Checking whether all elements of a
request's QEMUIOVector are within previously registered buffers is
expensive, so we need a hint from the user to avoid costly checks.
Add a BDRV_REQ_REGISTER
The only implementor of bdrv_register_buf() is block/nvme.c, where the
size is not needed when unregistering a buffer. This is because
util/vfio-helpers.c can look up mappings by address.
Future block drivers that implement bdrv_register_buf() may not be able
to do their job given only the buffer
Register guest RAM using BlockRAMRegistrar and set the
BDRV_REQ_REGISTERED_BUF flag so block drivers can optimize memory
accesses in I/O requests.
This is for vdpa-blk, vhost-user-blk, and other I/O interfaces that rely
on DMA mapping/unmapping.
Signed-off-by: Stefan Hajnoczi
---
include/hw/vir
When a RAMBlockNotifier is added, ->ram_block_added() is called with all
existing RAMBlocks. There is no equivalent ->ram_block_removed() call
when a RAMBlockNotifier is removed.
The util/vfio-helpers.c code (the sole user of RAMBlockNotifier) is fine
with this asymmetry because it does not rely o
Avoid bounce buffers when QEMUIOVector elements are within previously
registered bdrv_register_buf() buffers.
The idea is that emulated storage controllers will register guest RAM
using bdrv_register_buf() and set the BDRV_REQ_REGISTERED_BUF on I/O
requests. Therefore no blkio_map_mem_region() cal
libblkio (https://gitlab.com/libblkio/libblkio/) is a library for
high-performance disk I/O. It currently supports io_uring,
virtio-blk-vhost-user, and virtio-blk-vhost-vdpa with additional drivers
under development.
One of the reasons for developing libblkio is that other applications
besides QEM
The blkio block driver will need to look up the file descriptor for a
given pointer. This is possible in softmmu builds where the RAMBlock API
is available for querying guest RAM.
Add stubs so tools like qemu-img that link the block layer still build
successfully. In this case there is no guest RA
When a coroutine wakes up it may determine that it must re-queue.
Normally coroutines are pushed onto the back of the CoQueue, but for
fairness it may be necessary to push it onto the front of the CoQueue.
Add a flag to specify that the coroutine should be pushed onto the front
of the CoQueue. A l
Use the enum type so GDB displays the enum members instead of printing a
numeric constant.
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Stefano Garzarella
---
include/block/block_int-common.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/block/block_int-comm
Add a function to get the file descriptor for a RAMBlock. Device
emulation code typically uses the MemoryRegion APIs but vhost-style code
may use RAMBlock directly for sharing guest memory with another process.
This new API will be used by the libblkio block driver so it can share
guest memory via
v7:
- Add nvme-io_uring and virtio-blk-vhost-user syntax examples to commit
description [Markus]
- Add missing nvme-io_uring QAPI [Markus, Alberto]
- Rename mem-regions-pinned to may-pin-mem-regions [Alberto]
- Fix value/bs->bl.max_iov mix-up [Stefano]
v6:
- Add untested nvme-io_uring driver. Plea
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