On 10/10/2022 10.52, Lev Kujawski wrote:
Verify that the ATA command READ NATIVE MAX ADDRESS returns the last
valid CHS tuple for the native device rather than any limit
established by INITIALIZE DEVICE PARAMETERS.
Signed-off-by: Lev Kujawski
---
tests/qtest/ide-test.c | 47 ++
On 10/10/22 19:01, Daniel Wagner wrote:
On Tue, May 11, 2021 at 06:12:47PM +0200, Hannes Reinecke wrote:
On 5/11/21 6:03 PM, Klaus Jensen wrote:
On May 11 16:54, Hannes Reinecke wrote:
On 5/11/21 3:37 PM, Klaus Jensen wrote:
On May 11 15:12, Hannes Reinecke wrote:
On 5/11/21 2:22 PM, Klaus J
On 2022/10/12 11:09, Alistair Francis wrote:
On Wed, Oct 12, 2022 at 12:50 PM LIU Zhiwei
wrote:
Reviewed-by: LIU Zhiwei
Thanks!
By the way, we missed one related patch that once had been picked to riscv-next
patch.
The patch v3:
https://lore.kernel.org/all/ceeb4037-6d17-0a09-f35a-eaf3280
On 10/11/2022 8:09 PM, Jason Wang wrote:
On Tue, Oct 11, 2022 at 1:18 AM Si-Wei Liu wrote:
On 10/8/2022 10:43 PM, Jason Wang wrote:
On Sat, Oct 8, 2022 at 5:04 PM Si-Wei Liu wrote:
Similar to other vhost backends, vhostfd can be passed to vhost-vdpa
backend as another parameter to instan
Only the pmp index that be checked by pmp_hart_has_privs can be used
by pmp_get_tlb_size to avoid an error pmp index.
Before modification, we may use an error pmp index. For example,
we check address 0x4fc, and the size 0x4 in pmp_hart_has_privs. If there
is an pmp rule, valid range is [0x4fc, 0x5
Hi,
This is a rework of jitdump and perfmap patches from Vanderson and
Alex:
- jitdump: https://wiki.qemu.org/Features/TCGCodeQuality
v1: https://lists.gnu.org/archive/html/qemu-devel/2019-08/msg02676.html
v2:
https://lore.kernel.org/qemu-devel/20190830121903.17585-1-vanderson...@gmail.com/
Add ability to dump /tmp/perf-.map and jit-.dump.
The first one allows the perf tool to map samples to each individual
translation block. The second one adds the ability to resolve symbol
names, line numbers and inspect JITed code.
Example of use:
perf record qemu-x86_64 -perfmap ./a.out
On Wed, Oct 12, 2022 at 6:55 AM Jason A. Donenfeld wrote:
>
> When the system reboots, the rng-seed that the FDT has should be
> re-randomized, so that the new boot gets a new seed. Since the FDT is in
> the ROM region at this point, we add a hook right after the ROM has been
> added, so that we h
On Wed, Oct 12, 2022 at 6:57 AM Jason A. Donenfeld wrote:
>
> When the system reboots, the rng-seed that the FDT has should be
> re-randomized, so that the new boot gets a new seed. Several
> architectures require this functionality, so export a function for
> injecting a new seed into the given F
On Tue, 11 Oct 2022, Miguel Luis wrote:
> Step 3 from bios-tables-test.c documented procedure.
>
> Signed-off-by: Miguel Luis
Acked-by: Ani Sinha
> ---
> tests/qtest/bios-tables-test-allowed-diff.h | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/tests/qtest/bios-tables-test-
On Tue, 11 Oct 2022, Miguel Luis wrote:
> Step 6 & 7 of the bios-tables-test.c documented procedure.
>
> Differences between disassembled ASL files for MADT:
>
> @@ -11,9 +11,9 @@
> */
>
> [000h 4]Signature : "APIC"[Multiple APIC
> Description Table (MADT)]
>
On Tue, Oct 11, 2022 at 1:18 AM Si-Wei Liu wrote:
>
>
>
> On 10/8/2022 10:43 PM, Jason Wang wrote:
>
> On Sat, Oct 8, 2022 at 5:04 PM Si-Wei Liu wrote:
>
> Similar to other vhost backends, vhostfd can be passed to vhost-vdpa
> backend as another parameter to instantiate vhost-vdpa net client.
> T
On Wed, Oct 12, 2022 at 12:50 PM LIU Zhiwei
wrote:
>
> Reviewed-by: LIU Zhiwei
Thanks!
>
> By the way, we missed one related patch that once had been picked to
> riscv-next patch.
>
> The patch v3:
> https://lore.kernel.org/all/ceeb4037-6d17-0a09-f35a-eaf328033...@c-sky.com/T/#m183e4430bda408bc
Reviewed-by: LIU Zhiwei
By the way, we missed one related patch that once had been picked to riscv-next
patch.
The patch v3:
https://lore.kernel.org/all/ceeb4037-6d17-0a09-f35a-eaf328033...@c-sky.com/T/#m183e4430bda408bc3a2b2751aa94eff7fc02e23c
The patch v4:
https://lists.gnu.org/archive/html/
On Tue, Oct 11, 2022 at 10:48:58AM +0100, Fuad Tabba wrote:
> Hi,
>
> On Thu, Sep 15, 2022 at 3:38 PM Chao Peng wrote:
> >
> > If CONFIG_HAVE_KVM_PRIVATE_MEM=y, userspace can register/unregister the
> > guest private memory regions through KVM_MEMORY_ENCRYPT_{UN,}REG_REGION
> > ioctls. The patch
On 2022/10/7 21:48, Michael S. Tsirkin wrote:
> On Thu, Sep 22, 2022 at 09:11:40PM +0800, Yicong Yang wrote:
>> From: Yicong Yang
>>
>> Currently we'll always generate a cluster node no matter user has
>> specified '-smp clusters=X' or not. Cluster is an optional level
>> and it's unncessary to bu
On 2022/10/9 14:46, wangyanan (Y) wrote:
> Hi Yicong,
>
> On 2022/9/22 21:11, Yicong Yang wrote:
>> From: Yicong Yang
>>
>> Currently we'll always generate a cluster node no matter user has
>> specified '-smp clusters=X' or not. Cluster is an optional level
>> and it's unncessary to build it if us
'lock_user' allocates a host buffer to shadow a target buffer,
'unlock_user' copies that host buffer back to the target and frees the
host memory. If the completion function uses the target buffer, it
must be called after unlock_user to ensure the data are present.
This caused the arm-compatible T
On Wed, Oct 12, 2022 at 4:05 AM Laurent Vivier wrote:
>
> On 10/9/22 07:52, Jason Wang wrote:
> > On Thu, Oct 6, 2022 at 7:21 PM Michael S. Tsirkin wrote:
> >>
> >> On Wed, Oct 05, 2022 at 06:20:34PM +0200, Laurent Vivier wrote:
> >>> "-netdev socket" only supports inet sockets.
> >>>
> >>> It's
From: Alistair Francis
Since commit 4047368938f6 "accel/tcg: Introduce tlb_set_page_full" we
have been seeing this assert
../accel/tcg/cputlb.c:1294: tlb_set_page_with_attrs: Assertion
`is_power_of_2(size)' failed.
When running Tock on the OpenTitan machine.
The issue is that pmp_get_tlb_
There are three high memory regions, which are VIRT_HIGH_REDIST2,
VIRT_HIGH_PCIE_ECAM and VIRT_HIGH_PCIE_MMIO. Their base addresses
are floating on highest RAM address. However, they can be disabled
in several cases.
(1) One specific high memory region is disabled by developer by
toggling vms-
This renames variable 'size' to 'region_size' in virt_set_high_memmap().
Its counterpart ('region_base') will be introduced in next patch.
No functional change intended.
Signed-off-by: Gavin Shan
Reviewed-by: Eric Auger
Reviewed-by: Cornelia Huck
Tested-by: Zhenyu Zhang
---
hw/arm/virt.c | 1
This introduces virt_get_high_memmap_enabled() helper, which returns
the pointer to vms->highmem_{redists, ecam, mmio}. The pointer will
be used in the subsequent patches.
No functional change intended.
Signed-off-by: Gavin Shan
Tested-by: Zhenyu Zhang
---
hw/arm/virt.c | 32 ++
After the improvement to high memory region address assignment is
applied, the memory layout can be changed, introducing possible
migration breakage. For example, VIRT_HIGH_PCIE_MMIO memory region
is disabled or enabled when the optimization is applied or not, with
the following configuration.
p
This introduces variable 'region_base' for the base address of the
specific high memory region. It's the preparatory work to optimize
high memory region address assignment.
No functional change intended.
Signed-off-by: Gavin Shan
Reviewed-by: Eric Auger
Reviewed-by: Cornelia Huck
Tested-by: Zh
This introduces virt_set_high_memmap() helper. The logic of high
memory region address assignment is moved to the helper. The intention
is to make the subsequent optimization for high memory region address
assignment easier.
No functional change intended.
Signed-off-by: Gavin Shan
Reviewed-by: E
There are three high memory regions, which are VIRT_HIGH_REDIST2,
VIRT_HIGH_PCIE_ECAM and VIRT_HIGH_PCIE_MMIO. Their base addresses
are floating on highest RAM address. However, they can be disabled
in several cases.
(1) One specific high memory region is disabled by developer by
toggling vms-
On 10/12/22 12:45 AM, Eric Auger wrote:
On 10/5/22 00:47, Gavin Shan wrote:
On 10/4/22 6:41 PM, Cornelia Huck wrote:
On Tue, Oct 04 2022, Gavin Shan wrote:
This introduces virt_get_high_memmap_enabled() helper, which returns
the pointer to vms->highmem_{redists, ecam, mmio}. The pointer will
On Mon, Oct 3, 2022 at 2:18 PM Jim Shu wrote:
>
> This patchset fixes hard-coded maximum priority of interrupt priority
> register and also changes this register to WARL field to align the PLIC
> spec.
>
> Changelog:
>
> v3:
> * fix opposite of power-of-2 max priority checking expression.
>
> v2
On Fri, Sep 30, 2022 at 1:34 PM Wilfred Mallawa
wrote:
>
> From: Wilfred Mallawa
>
> The remaining patches in this series address:
> - Coverity issues for `ibex_spi`
> - Adds rw1c functionality
>
> Changes since V4:
> - Fixup compiler warning for unused variable `data` in
Add a field for QemuMutex to remember the locked status, then assert
properly when CONFIG_DEBUG_MUTEX enabled on illegal unlocks.
The pthread library is by default quite loose on this by allowing the
unlock to quietly succeed. But that could cause the follow up things very
unpredictable so if the
The new _timedwait() version of qemu cond/mutex doesn't trigger the
DEBUG_MUTEX paths; enable it too.
Cc: Yury Kotov
Signed-off-by: Peter Xu
---
util/qemu-thread-posix.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/util/qemu-thread-posix.c b/util/qemu-thread-posix.c
i
NOTE: mark patchset RFC because "make check" will easily fail; but I didn't
yet dig into why as I'm not familiar with the code paths that triggers, it
can be bugs hidden or something I missed. So RFC to just have some thoughts.
The first patch converts the new timedwait to use DEBUG_MUTEX paths t
On Tue, Oct 4, 2022 at 7:25 PM Sunil V L wrote:
>
> This series adds the support to boot S-mode FW like EDK2 from the flash. The
> S-mode firmware should be kept in pflash unit 1.
>
> When -kernel (and -initrd) option is also provided along with the flash,
> the kernel (and initrd) will be loaded
On Fri, Oct 07, 2022 at 12:09:40PM +0100, Daniel P. Berrangé wrote:
> On Fri, Oct 07, 2022 at 11:45:56AM +0100, Daniel P. Berrangé wrote:
> > On Fri, Oct 07, 2022 at 06:11:25AM -0400, Michael S. Tsirkin wrote:
> > > On Fri, Oct 07, 2022 at 09:07:17AM +0100, Daniel P. Berrangé wrote:
> > > > On Thu,
On Tue, Oct 11, 2022 at 05:19:11PM -0400, Gregory Price wrote:
> Summary of Changes:
> 1) Correction of PCI_CLASS from STORAGE_EXPRESS to MEMORY_CXL on init
> 2) Add CXL_CAPACITY_MULTIPLIER definition to replace magic numbers
> 3) Refactor CDAT DSMAS Initialization for multi-region initialization
>
With the new code to send pages in rp-return thread, there's little help to
keep lots of the old code on maintaining the preempt state in migration
thread, because the new way should always be faster..
Then if we'll always send pages in the rp-return thread anyway, we don't
need those logic to mai
With all the facilities ready, send the requested page directly in the
rp-return thread rather than queuing it in the request queue, if and only
if postcopy preempt is enabled. It can achieve so because it uses separate
channel for sending urgent pages. The only shared data is bitmap and it's
pro
Am 4. Oktober 2022 09:23:51 UTC schrieb Sunil V L :
>To boot S-mode firmware payload like EDK2 from persistent
>flash storage, qemu needs to pass the flash address as the
>next_addr in fw_dynamic_info to the opensbi.
>
>When both -kernel and -pflash options are provided in command line,
>the kernel
Helper to init PSS structures.
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Peter Xu
---
migration/ram.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/migration/ram.c b/migration/ram.c
index d81dd3fdac..44967e72b2 100644
--- a/migration/ram.c
+++ b/migra
Removing referencing to RAMState.f in compress_page_with_multi_thread() and
flush_compressed_data().
Compression code by default isn't compatible with having >1 channels (or it
won't currently know which channel to flush the compressed data), so to
make it simple we always flush on the default to_
Migration code has a lot to do with host pages. Teaching PSS core about
the idea of host page helps a lot and makes the code clean. Meanwhile,
this prepares for the future changes that can leverage the new PSS helpers
that this patch introduces to send host page in another thread.
Three more fie
Since we use PageSearchStatus to represent a channel, it makes perfect
sense to keep last_sent_block (aka, leverage RAM_SAVE_FLAG_CONTINUE) to be
per-channel rather than global because each channel can be sending
different pages on ramblocks.
Hence move it from RAMState into PageSearchStatus.
Rev
Now with rs->pss we can already cache channels in pss->pss_channels. That
pss_channel contains more infromation than rs->f because it's per-channel.
So rs->f could be replaced by rss->pss[RAM_CHANNEL_PRECOPY].pss_channel,
while rs->f itself is a bit vague now.
Note that vanilla postcopy still sen
Adds explicit examples for --persistent-memdev and --volatile-memdev
Signed-off-by: Gregory Price
---
docs/system/devices/cxl.rst | 53 ++--
tests/qtest/cxl-test.c | 81 +++--
2 files changed, 110 insertions(+), 24 deletions(-)
diff --git
The 2nd check on RAM_SAVE_FLAG_CONTINUE is a bit redundant. Use a boolean
to be clearer.
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Peter Xu
---
migration/ram.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/migration/ram.c b/migration/ram.c
index 562646609e..
Introduce pss_channel for PageSearchStatus, define it as "the migration
channel to be used to transfer this host page".
We used to have rs->f, which is a mirror to MigrationState.to_dst_file.
After postcopy preempt initial version, rs->f can be dynamically changed
depending on which channel we wa
We used to allocate PSS structure on the stack for precopy when sending
pages. Make it static, so as to describe per-channel ram migration status.
Here we declared RAM_CHANNEL_MAX instances, preparing for postcopy to use
it, even though this patch has not yet to start using the 2nd instance.
Thi
This commit enables each CXL Type-3 device to contain one volatile
memory region and one persistent region.
Two new properties have been added to cxl-type3 device initialization:
[volatile-memdev] and [persistent-memdev]
The existing [memdev] property has been deprecated and will default the
To prepare for thread-safety on page accountings, at least below counters
need to be accessed only atomically, they are:
ram_counters.transferred
ram_counters.duplicate
ram_counters.normal
ram_counters.postcopy_bytes
There are a lot of other counters but they won't
Based-on: <20221004182430.97638-1-pet...@redhat.com>
[PATCH v2 0/5] migration: Bug fixes (prepare for preempt-full)
Tree is here:
https://github.com/xzpeter/qemu/tree/preempt-full
RFC: https://lore.kernel.org/r/20220829165659.96046-1-pet...@redhat.com
v1: https://lore.kernel.org/r/2022092022
Don't take the bitmap mutex when sending pages, or when being throttled by
migration_rate_limit() (which is a bit tricky to call it here in ram code,
but seems still helpful).
It prepares for the possibility of concurrently sending pages in >1 threads
using the function ram_save_host_page() becaus
Remove usage of magic numbers when accessing capacity fields and replace
with CXL_CAPACITY_MULTIPLIER, matching the kernel definition.
Signed-off-by: Gregory Price
Reviewed-by: Davidlohr Bueso
---
hw/cxl/cxl-mailbox-utils.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
d
The major change is to replace "!save_page_use_compression()" with
"xbzrle_enabled" to make it clear.
Reasonings:
(1) When compression enabled, "!save_page_use_compression()" is exactly the
same as checking "xbzrle_enabled".
(2) When compression disabled, "!save_page_use_compression()" alway
Summary of Changes:
1) Correction of PCI_CLASS from STORAGE_EXPRESS to MEMORY_CXL on init
2) Add CXL_CAPACITY_MULTIPLIER definition to replace magic numbers
3) Refactor CDAT DSMAS Initialization for multi-region initialization
4) Multi-Region and Volatile Memory support for CXL Type-3 Devices
5) Te
Add the helper to show that postcopy preempt enabled, meanwhile active.
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Peter Xu
---
migration/ram.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/migration/ram.c b/migration/ram.c
index cfeb571800..7aaa843a21 100
Any call to ram_find_and_save_block() needs to take the bitmap mutex. We
used to not take it for most of ram_save_complete() because we thought
we're the only one left using the bitmap, but it's not true after the
preempt full patchset applied, since the return path can be taking it too.
Signed-o
This is a preparatory commit for enabling multiple memory regions within
a single CXL Type-3 device. We will need to initialize multiple CDAT
DSMAS regions (and subsequent DSLBIS, and DSEMTS entries), so generalize
the intialization into a function.
Signed-off-by: Gregory Price
---
hw/mem/cxl_t
Now that cs->interrupt_request indicates if there is any unmasked
interrupt, checking if the CPU has work to do can be simplified to a
single check that works for all CPU models.
Reviewed-by: Fabiano Rosas
Signed-off-by: Matheus Ferst
---
target/ppc/cpu_init.c | 94 +
Writes to LPCR are hypervisor privileged.
Signed-off-by: Matheus Ferst
---
target/ppc/cpu.c | 2 ++
target/ppc/cpu.h | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c
index 0ebac04bc4..e95b4c5ee1 100644
--- a/target/ppc/cpu.c
+++ b/target/p
Current code sets to STORAGE_EXPRESS and then overrides it.
Signed-off-by: Gregory Price
Reviewed-by: Davidlohr Bueso
Reviewed-by: Jonathan Cameron
---
hw/mem/cxl_type3.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 3e7ca7a
The new method is identical to ppc_next_unmasked_interrupt_generic,
processor-specific code will be added/removed in the following patches.
Signed-off-by: Matheus Ferst
---
target/ppc/excp_helper.c | 114 +++
1 file changed, 114 insertions(+)
diff --git a/tar
This new method will check if any pending interrupt was unmasked and
then call cpu_interrupt/cpu_reset_interrupt accordingly. Code that
raises/lowers or masks/unmasks interrupts should call this method to
keep CPU_INTERRUPT_HARD coherent with env->pending_interrupts.
Signed-off-by: Matheus Ferst
Le 11/10/2022 à 16:56, Jason A. Donenfeld a écrit :
On Tue, Oct 11, 2022 at 10:29:45AM +0100, Peter Maydell wrote:
On Tue, 11 Oct 2022 at 09:41, Laurent Vivier wrote:
Le 03/10/2022 à 13:02, Jason A. Donenfeld a écrit :
Rather than poking directly into RAM, add the bootinfo block as a proper
Move the interrupt masking logic out of cpu_has_work_POWER8 in a new
method, p8_interrupt_powersave, that only returns an interrupt if it can
wake the processor from power-saving mode.
Signed-off-by: Matheus Ferst
---
target/ppc/cpu_init.c | 61 +++
1 file
Remove the following unused interrupts from the POWER7 interrupt
processing method:
- PPC_INTERRUPT_RESET: only raised for 6xx, 7xx, 970 and POWER5p;
- Hypervisor Virtualization: introduced in Power ISA v3.0;
- Hypervisor Doorbell and Event-Based Branch: introduced in
Power ISA v2.07;
- Critical
Move the interrupt masking logic out of cpu_has_work_POWER7 in a new
method, p7_interrupt_powersave, that only returns an interrupt if it can
wake the processor from power-saving mode.
Signed-off-by: Matheus Ferst
---
target/ppc/cpu_init.c | 45 ---
1 file
Signed-off-by: Matheus Ferst
---
target/ppc/excp_helper.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 662daad796..aaf1c95087 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -2004,9 +2004,6 @@ static void p
Move the methods to excp_helper.c and make them static.
Reviewed-by: Fabiano Rosas
Signed-off-by: Matheus Ferst
---
target/ppc/cpu_init.c| 102 ---
target/ppc/excp_helper.c | 102 +++
target/ppc/internal.h| 6 ---
The new method is identical to ppc_deliver_interrupt, processor-specific
code will be added/removed in the following patches.
Signed-off-by: Matheus Ferst
---
target/ppc/excp_helper.c | 113 +++
1 file changed, 113 insertions(+)
diff --git a/target/ppc/excp_h
Signed-off-by: Matheus Ferst
---
target/ppc/excp_helper.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 055f1de20e..1c373c1a7c 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -2077,9 +2077,6 @@ static void p
Remove the following unused interrupts from the POWER8 interrupt
processing method:
- PPC_INTERRUPT_RESET: only raised for 6xx, 7xx, 970 and POWER5p;
- Debug Interrupt: removed in Power ISA v2.07;
- Hypervisor Virtualization: introduced in Power ISA v3.0;
- Critical Input, Watchdog Timer, and Fixed
Export p7_interrupt_powersave and use it in p7_next_unmasked_interrupt.
Signed-off-by: Matheus Ferst
---
target/ppc/cpu_init.c| 2 +-
target/ppc/excp_helper.c | 24
target/ppc/internal.h| 1 +
3 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/tar
Remove the following unused interrupts from the POWER7 interrupt masking
method:
- PPC_INTERRUPT_RESET: only raised for 6xx, 7xx, 970 and POWER5p;
- Hypervisor Virtualization: introduced in Power ISA v3.0;
- Hypervisor Doorbell and Event-Based Branch: introduced in
Power ISA v2.07;
- Critical Inp
Remove the following unused interrupts from the POWER8 interrupt masking
method:
- PPC_INTERRUPT_RESET: only raised for 6xx, 7xx, 970, and POWER5p;
- Debug Interrupt: removed in Power ISA v2.07;
- Hypervisor Virtualization: introduced in Power ISA v3.0;
- Critical Input, Watchdog Timer, and Fixed I
The new method is identical to ppc_deliver_interrupt, processor-specific
code will be added/removed in the following patches.
Signed-off-by: Matheus Ferst
---
target/ppc/excp_helper.c | 113 +++
1 file changed, 113 insertions(+)
diff --git a/target/ppc/excp_h
Export p8_interrupt_powersave and use it in p8_next_unmasked_interrupt.
Signed-off-by: Matheus Ferst
---
target/ppc/cpu_init.c| 2 +-
target/ppc/excp_helper.c | 24
target/ppc/internal.h| 1 +
3 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/tar
Move the interrupt masking logic out of cpu_has_work_POWER9 in a new
method, p9_interrupt_powersave, that only returns an interrupt if it can
wake the processor from power-saving mode.
Signed-off-by: Matheus Ferst
---
target/ppc/cpu_init.c | 126 +-
1 file
The new method is identical to ppc_next_unmasked_interrupt_generic,
processor-specific code will be added/removed in the following patches.
Signed-off-by: Matheus Ferst
---
target/ppc/excp_helper.c | 114 +++
1 file changed, 114 insertions(+)
diff --git a/tar
Export p9_interrupt_powersave and use it in p9_next_unmasked_interrupt.
Signed-off-by: Matheus Ferst
---
Putting the prototype in internal.h for a lack of better place. However,
we will un-export p9_interrupt_powersave in future patches, so it's only
temporary.
---
target/ppc/cpu_init.c| 2
The new method is identical to ppc_deliver_interrupt, processor-specific
code will be added/removed in the following patches.
Signed-off-by: Matheus Ferst
---
target/ppc/excp_helper.c | 118 +++
1 file changed, 118 insertions(+)
diff --git a/target/ppc/excp_h
Signed-off-by: Matheus Ferst
---
target/ppc/excp_helper.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index fb946385cc..fd9745c37e 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1919,18 +
Remove the following unused interrupts from the POWER9 interrupt masking
method:
- PPC_INTERRUPT_RESET: only raised for 6xx, 7xx, 970 and POWER5p;
- Debug Interrupt: removed in Power ISA v2.07;
- Critical Input, Watchdog Timer, and Fixed Interval Timer: only defined
for embedded CPUs;
- Critical
Signed-off-by: Matheus Ferst
---
target/ppc/excp_helper.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index f92b6c2b18..7d196d1581 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
Remove the following unused interrupts from the POWER9 interrupt
processing method:
- PPC_INTERRUPT_RESET: only raised for 6xx, 7xx, 970 and POWER5p;
- Debug Interrupt: removed in Power ISA v2.07;
- Critical Input, Watchdog Timer, and Fixed Interval Timer: only defined
for embedded CPUs;
- Critic
The new method is identical to ppc_next_unmasked_interrupt_generic,
processor-specific code will be added/removed in the following patches.
Signed-off-by: Matheus Ferst
---
target/ppc/excp_helper.c | 119 +++
1 file changed, 119 insertions(+)
diff --git a/tar
Split ppc_hw_interrupt into an interrupt masking method,
ppc_next_unmasked_interrupt, and an interrupt processing method,
ppc_deliver_interrupt.
Signed-off-by: Matheus Ferst
---
target/ppc/excp_helper.c | 207 +--
1 file changed, 131 insertions(+), 76 deletion
Snapshot loading is supposed to be deterministic, so we shouldn't
re-randomize the various seeds used.
Signed-off-by: Jason A. Donenfeld
---
hw/arm/boot.c | 3 ++-
hw/i386/x86.c | 2 +-
hw/mips/boston.c | 2 +-
hw/openrisc/boot.c | 2 +-
hw/riscv/boot.c| 2 +-
hw/rx/rx-gdbsim.c
When the system reboots, the rng-seed that the FDT has should be
re-randomized, so that the new boot gets a new seed. Since the FDT is in
the ROM region at this point, we add a hook right after the ROM has been
added, so that we have a pointer to that copy of the FDT.
Cc: Yoshinori Sato
Signed-of
When the system reboots, the rng-seed that the FDT has should be
re-randomized, so that the new boot gets a new seed. Since the FDT is in
the ROM region at this point, we add a hook right after the ROM has been
added, so that we have a pointer to that copy of the FDT.
Cc: Peter Maydell
Cc: qemu-.
This enum defines the bit positions in env->pending_interrupts for each
interrupt. However, except for the comparison in kvmppc_set_interrupt,
the values are always used as (1 << PPC_INTERRUPT_*). Define them
directly like that to save some clutter. No functional change intended.
Reviewed-by: Davi
Use ppc_set_irq to raise/clear interrupts to ensure CPU_INTERRUPT_HARD
will be set/reset accordingly.
Reviewed-by: Fabiano Rosas
Signed-off-by: Matheus Ferst
---
target/ppc/excp_helper.c | 17 +++--
target/ppc/misc_helper.c | 9 ++---
2 files changed, 9 insertions(+), 17 deleti
Link to v2: https://lists.gnu.org/archive/html/qemu-ppc/2022-09/msg00556.html
This series is also available as a git branch:
https://github.com/PPC64/qemu/tree/ferst-interrupt-fix-v3
Patches without review: 3-27
This new version rebases the patch series on the current master and
fixes some proble
When the system reboots, the rng-seed that the FDT has should be
re-randomized, so that the new boot gets a new seed. Since the FDT is in
the ROM region at this point, we add a hook right after the ROM has been
added, so that we have a pointer to that copy of the FDT.
Cc: Aleksandar Rikalo
Cc: Pa
When the system reboots, the rng-seed that the FDT has should be
re-randomized, so that the new boot gets a new seed. Several
architectures require this functionality, so export a function for
injecting a new seed into the given FDT.
Cc: Alistair Francis
Cc: David Gibson
Signed-off-by: Jason A.
When the system reboots, the rng-seed that the FDT has should be
re-randomized, so that the new boot gets a new seed. Since the FDT is in
the ROM region at this point, we add a hook right after the ROM has been
added, so that we have a pointer to that copy of the FDT.
Cc: Palmer Dabbelt
Cc: Alist
Snapshot loading only expects to call deterministic handlers, not
non-deterministic ones. So introduce a way of registering handlers that
won't be called when reseting for snapshots.
Signed-off-by: Jason A. Donenfeld
---
hw/arm/aspeed.c| 4 ++--
hw/arm/mps2-tz.c | 4 ++--
When the system reboots, the rng seed that QEMU passes should be
re-randomized, so that the new boot gets a new seed. This series wires
that up for FDT.
Then, since the record&replay subsystem makes use of reset as well, we
add a new reset cause for record&replay, so that we can avoid
re-randomizi
On Tue, Oct 11, 2022 at 2:06 PM Jason A. Donenfeld wrote:
>
> On Tue, Oct 11, 2022 at 09:46:01AM +0300, Pavel Dovgalyuk wrote:
> > On 10.10.2022 18:32, Peter Maydell wrote:
> > > On Mon, 10 Oct 2022 at 16:21, Jason A. Donenfeld wrote:
> > >>
> > >> On Mon, Oct 10, 2022 at 11:54:50AM +0100, Peter
When the system reboots, the rng-seed that the FDT has should be
re-randomized, so that the new boot gets a new seed. Since the FDT is in
the ROM region at this point, we add a hook right after the ROM has been
added, so that we have a pointer to that copy of the FDT.
Cc: Stafford Horne
Signed-of
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