[RESEND because the ML ate my email again]
Hi All,
In my investigations into our current Avocado tests I identified all
that ran for more than 30s for an --enable-debug build. They are:
tests/avocado/boot_linux.py:BootLinuxAarch64.test_virt_tcg_gicv2: PASS(
763.81 s)
tests/avocado/boot_linu
On Fri, Aug 12, 2022 at 10:50 PM Victor Toso wrote:
>
> Hi,
>
> On Fri, Aug 12, 2022 at 10:33:54PM -0700, Joelle van Dyne wrote:
> > On Fri, Aug 12, 2022 at 10:30 PM Victor Toso wrote:
> > >
> > > Hi,
> > >
> > > On Fri, Aug 12, 2022 at 06:10:31PM -0700, Joelle van Dyne wrote:
> > > > When launch
Hi,
On Fri, Aug 12, 2022 at 10:33:54PM -0700, Joelle van Dyne wrote:
> On Fri, Aug 12, 2022 at 10:30 PM Victor Toso wrote:
> >
> > Hi,
> >
> > On Fri, Aug 12, 2022 at 06:10:31PM -0700, Joelle van Dyne wrote:
> > > When launching QEMU with "-loadvm", usbredir_create_parser() should avoid
> > > set
On Fri, Aug 12, 2022 at 10:30 PM Victor Toso wrote:
>
> Hi,
>
> On Fri, Aug 12, 2022 at 06:10:31PM -0700, Joelle van Dyne wrote:
> > When launching QEMU with "-loadvm", usbredir_create_parser() should avoid
> > setting up the hello packet (just as with "-incoming". On the latest version
> > of lib
Hi,
On Fri, Aug 12, 2022 at 06:10:31PM -0700, Joelle van Dyne wrote:
> When launching QEMU with "-loadvm", usbredir_create_parser() should avoid
> setting up the hello packet (just as with "-incoming". On the latest version
> of libusbredir, usbredirparser_unserialize() will return error if the pa
On Fri, Aug 12, 2022 at 7:32 PM Richard Henderson
wrote:
>
> On 8/12/22 17:50, Furquan Shaikh wrote:
> >> Why do you need such fine-grained control? What is the use-case?
> >
> > I ran into a problem when I was testing a project (with a microkernel
> > in M-mode and tasks in U-mode) that uses sem
On 8/12/22 17:50, Furquan Shaikh wrote:
Why do you need such fine-grained control? What is the use-case?
I ran into a problem when I was testing a project (with a microkernel
in M-mode and tasks in U-mode) that uses semihosting for debugging.
The semihosting worked fine for M-mode but not in U
Run state is also in RUN_STATE_PRELAUNCH while "-S" is used.
This reverts commit 12d182898a4866e4be418e2abac286b497cfa1b2.
Signed-off-by: Joelle van Dyne
---
hw/usb/redirect.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c
index 1bd30
When launching QEMU with "-loadvm", usbredir_create_parser() should avoid
setting up the hello packet (just as with "-incoming". On the latest version
of libusbredir, usbredirparser_unserialize() will return error if the parser
is not "pristine."
Signed-off-by: Joelle van Dyne
---
hw/usb/redirec
This allows us to differentiate between a fresh boot and a restore boot.
Signed-off-by: Joelle van Dyne
---
softmmu/runstate.c | 1 +
softmmu/vl.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/softmmu/runstate.c b/softmmu/runstate.c
index 1e68680b9d..fa3dd3a4ab 100644
--- a/softm
Previously, there was a bug in usbredir which prevented "-loadvm" from working
because libusbredir's usbredirparser_unserialize() fails when a HELLO packet is
sent as part of the device's initalization.
The fix was to not send HELLO when in the RUN_STATE_PRELAUNCH state. However,
recently we found
On Fri, Aug 12, 2022 at 5:30 PM Richard Henderson
wrote:
>
> On 8/12/22 16:57, Furquan Shaikh wrote:
> > I am not sure if I understood your comment correctly. Currently, qemu
> > has a check in `riscv_cpu_do_interrupt` to allow semihosting calls
> > only in S and M modes. This prevents semihosting
On 8/12/22 16:57, Furquan Shaikh wrote:
I am not sure if I understood your comment correctly. Currently, qemu
has a check in `riscv_cpu_do_interrupt` to allow semihosting calls
only in S and M modes. This prevents semihosting calls from U mode.
This patch changes the default behavior of checking
On Fri, Aug 12, 2022 at 4:42 PM Richard Henderson
wrote:
>
> On 8/12/22 16:27, Richard Henderson wrote:
> > On 8/11/22 13:41, Furquan Shaikh wrote:
> >> Unlike ARM, RISC-V does not define a separate breakpoint type for
> >> semihosting. Instead, it is entirely ABI. Thus, we need an option
> >> to
On 8/12/22 16:27, Richard Henderson wrote:
On 8/11/22 13:41, Furquan Shaikh wrote:
Unlike ARM, RISC-V does not define a separate breakpoint type for
semihosting. Instead, it is entirely ABI. Thus, we need an option
to allow users to configure what the ebreak behavior should be for
different priv
On Fri, Aug 12, 2022 at 4:00 PM Palmer Dabbelt wrote:
>
> On Fri, 12 Aug 2022 15:05:08 PDT (-0700), furq...@rivosinc.com wrote:
> > On Fri, Aug 12, 2022 at 4:04 AM Andrew Jones
> > wrote:
> >>
> >> On Thu, Aug 11, 2022 at 01:41:04PM -0700, Furquan Shaikh wrote:
> >> > Unlike ARM, RISC-V does not
On 8/11/22 13:41, Furquan Shaikh wrote:
Unlike ARM, RISC-V does not define a separate breakpoint type for
semihosting. Instead, it is entirely ABI. Thus, we need an option
to allow users to configure what the ebreak behavior should be for
different privilege levels - M, S, U, VS, VU. As per the R
Unlike ARM, RISC-V does not define a separate breakpoint type for
semihosting. Instead, it is entirely ABI. Thus, we need an option
to allow users to configure what the ebreak behavior should be for
different privilege levels - M, S, U, VS, VU. As per the RISC-V
privilege specification[1], ebreak t
On Fri, Aug 12, 2022 at 4:28 AM Peter Maydell wrote:
>
> On Thu, 11 Aug 2022 at 21:47, Furquan Shaikh wrote:
> >
> > Unlike ARM, RISC-V does not define a separate breakpoint type for
> > semihosting. Instead, it is entirely ABI. Thus, we need an option
> > to allow users to configure what the ebr
On Fri, 12 Aug 2022 15:05:08 PDT (-0700), furq...@rivosinc.com wrote:
On Fri, Aug 12, 2022 at 4:04 AM Andrew Jones wrote:
On Thu, Aug 11, 2022 at 01:41:04PM -0700, Furquan Shaikh wrote:
> Unlike ARM, RISC-V does not define a separate breakpoint type for
> semihosting. Instead, it is entirely A
On 8/8/22 00:26, David Gibson wrote:
On Fri, Aug 05, 2022 at 06:39:38AM -0300, Daniel Henrique Barboza wrote:
The pSeries machine never bothered with the common machine->fdt
attribute. We do all the FDT related work using spapr->fdt_blob.
We're going to introduce HMP commands to read and sav
On Fri, Aug 12, 2022 at 4:04 AM Andrew Jones wrote:
>
> On Thu, Aug 11, 2022 at 01:41:04PM -0700, Furquan Shaikh wrote:
> > Unlike ARM, RISC-V does not define a separate breakpoint type for
> > semihosting. Instead, it is entirely ABI. Thus, we need an option
> > to allow users to configure what t
David,
On 8/8/22 00:23, David Gibson wrote:
On Fri, Aug 05, 2022 at 06:39:29AM -0300, Daniel Henrique Barboza wrote:
At this moment, arm_load_dtb() can free machine->fdt when
binfo->dtb_filename is NULL. If there's no 'dtb_filename', 'fdt' will be
retrieved by binfo->get_dtb(). If get_dtb() ret
Function "update_rx_fifo()" should operate on the RX FIFO
registers, not the TX FIFO ones.
Signed-off-by: Anton Kochkov
Resolves: https://gitlab.com/qemu-projects/qemu/-/issues/1123
---
hw/net/can/xlnx-zynqmp-can.c | 32
1 file changed, 16 insertions(+), 16 delet
arm.git
tags/pull-target-arm-20220812
for you to fetch changes up to 4311682ea8293f720730f260e8a7601117d79e65:
cutils: Add missing dyld(3) include on macOS (2022-08-12 11:33:52 +0100)
target-arm queue:
* Don't report Stat
On 8/12/22 10:41, Peter Maydell wrote:
cpu64.c has ended up in a slightly odd order -- it starts with the
initfns for most of the models-real-hardware CPUs; after that comes a
bunch of support code for SVE, SME, pauth and LPA2 properties. Then
come the initfns for the 'host' and 'max' CPU types,
Use the pc coming from db->pc_first rather than the TB.
Use the cached host_addr rather than re-computing for the
first page. We still need a separate lookup for the second
page because it won't be computed for DisasContextBase until
the translator actually performs a read from the page.
Signed-
Cache the translation from guest to host address, so we may
use direct loads when we hit on the primary translation page.
Look up the second translation page only once, during translation.
This obviates another lookup of the second page within tb_gen_code
after translation.
Fixes a bug in that pl
We currently ignore PROT_EXEC on the initial lookup, and
defer raising the exception until cpu_ld*_code().
It makes more sense to raise the exception early.
Signed-off-by: Richard Henderson
---
accel/tcg/cpu-exec.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/accel/t
From: Ilya Leoshkevich
Introduce a function that checks whether a given address is on the same
page as where disassembly started. Having it improves readability of
the following patches.
Signed-off-by: Ilya Leoshkevich
Message-Id: <20220811095534.241224-3-...@linux.ibm.com>
Reviewed-by: Richard
Reuse the result that we just used with tb_lookup.
Pass in host_pc while touching these lines, to be used shortly.
We must widen the scope of the mmap_lock, so that the page table
lookup that is finally used is covered by the lock.
Signed-off-by: Richard Henderson
---
accel/tcg/internal.h |
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 10 +-
accel/tcg/cputlb.c | 8
accel/tcg/plugin-gen.c | 4 ++--
accel/tcg/user-exec.c | 4 ++--
4 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-a
Pass these along to translator_loop -- pc may be used instead
of tb->pc, and host_pc is currently unused. Adjust all targets
at one time.
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 1 -
include/exec/translator.h | 24
accel/tcg/translate-a
The mmap_lock is held around tb_gen_code. While the comment
is correct that the lock is dropped when tb_gen_code runs out
of memory, the lock is *not* dropped when an exception is
raised reading code for translation.
Signed-off-by: Richard Henderson
---
accel/tcg/cpu-exec.c | 12 ++--
1
We will want to re-use the result of get_page_addr_code
beyond the scope of tb_lookup.
Signed-off-by: Richard Henderson
---
accel/tcg/cpu-exec.c | 34 --
1 file changed, 24 insertions(+), 10 deletions(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
in
Simplify the implementation of get_page_addr_code_hostp
by reusing the existing probe_access infrastructure.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 76 --
1 file changed, 26 insertions(+), 50 deletions(-)
diff --git a/accel/tcg/cput
The base qemu_ram_addr_from_host function is already in
softmmu/physmem.c; move the nofail version to be adjacent.
Signed-off-by: Richard Henderson
---
include/exec/cpu-common.h | 1 +
accel/tcg/cputlb.c| 12
softmmu/physmem.c | 12
3 files changed, 13
The current implementation is a no-op, simply returning addr.
This is incorrect, because we ought to be checking the page
permissions for execution.
Make get_page_addr_code inline for both implementations.
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 85 ++-
Bool is more appropriate type for the alloc parameter.
Signed-off-by: Richard Henderson
---
accel/tcg/translate-all.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index cf99b2b876..65a23f47d6 100644
--- a
This bitmap is created and discarded immediately.
We gain nothing by its existence.
Signed-off-by: Richard Henderson
---
accel/tcg/translate-all.c | 78 ++-
1 file changed, 4 insertions(+), 74 deletions(-)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/tr
This function is used only once, so merge it into
its only caller, tb_lookup. This requires moving
the support routine, tb_lookup_cmp, and its private
data structure, tb_desc, up in the file.
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 3 -
accel/tcg/cpu-exec.c| 134 +++
We're about to start validating PAGE_EXEC, which means that we've
got to the vsyscall page executable. We had been special casing
this entirely within translate.
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/
We're about to start validating PAGE_EXEC, which means that we've
got to mark page zero executable. We had been special casing this
entirely within translate.
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 34 +++---
1 file changed, 31 insertions(+), 3 d
Map the stack executable if required by default or on demand.
Signed-off-by: Richard Henderson
---
include/elf.h| 1 +
linux-user/qemu.h| 1 +
linux-user/elfload.c | 19 ++-
3 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/include/elf.h b/include/elf.h
The only user can easily use translator_lduw and
adjust the type to signed during the return.
Signed-off-by: Richard Henderson
---
include/exec/translator.h | 1 -
target/i386/tcg/translate.c | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/include/exec/translator.h b/incl
We're about to start validating PAGE_EXEC, which means
that we've got to mark the commpage executable. We had
been placing the commpage outside of reserved_va, which
was incorrect and lead to an abort.
Signed-off-by: Richard Henderson
---
linux-user/arm/target_cpu.h | 4 ++--
linux-user/elfload
We're about to start validating PAGE_EXEC, which means
that we've got to put this code into a section that is
both writable and executable.
Note that this test did not run on hardware beforehand either.
Signed-off-by: Richard Henderson
---
tests/tcg/i386/test-i386.c | 2 +-
1 file changed, 1 in
This is part of a larger body of work, but in the process of
reorganizing I was reminded that PROT_EXEC wasn't being enforced
properly for user-only. As this has come up in the context of
some of Ilya's patches, I thought I'd go ahead and post this part.
r~
Ilya Leoshkevich (1):
accel/tcg: I
On 8/12/22 08:02, Ilya Leoshkevich wrote:
tb_lookup() skips get_page_addr_code() if tb is found in tb_jmp_cache.
I assume it's a bug?
Yes, I think so. I've rearranged that for other reasons, and so may have inadvertently
fix this. I'll post the in-progress work in a moment.
r~
On 8/12/22 09:31, Peter Maydell wrote:
Is it possible to rearrange this patchset so the easy
refactoring patches that do "use a struct to return
values from get_phys_addr and friends" are at the front
(ie before the stuff that touches core code) ?
That way they're easy to take into the tree early
:17
+0200)
Pull request linux-user 20220812
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/7.1 as
appropriate.
r~
Vitaly Buka (1):
linux-user/aarch64: Reset target data on MADV_DONTNEED
accel/tcg
cpu64.c has ended up in a slightly odd order -- it starts with the
initfns for most of the models-real-hardware CPUs; after that comes a
bunch of support code for SVE, SME, pauth and LPA2 properties. Then
come the initfns for the 'host' and 'max' CPU types, and then after
that one more models-real
On Sun, 3 Jul 2022 at 09:25, Richard Henderson
wrote:
>
> This is a major reorg to arm page table walking. While the result
> here is "merely" Hardware-assited Access Flag and Dirty Bit Setting
> (HAFDBS), the ultimate goal is the Realm Management Extension (RME).
> RME "recommends" that HAFDBS b
On Wed, Aug 3, 2022 at 12:15 PM Richard W.M. Jones wrote:
> If it helps to think about this, Coverity checks for consistency.
> Across the whole code base, is the return value of a function used or
> ignored consistently. You will see Coverity errors like:
>
> Error: CHECKED_RETURN (CWE-252
On 11/08/2022 18:39, Daniel Henrique Barboza wrote:
The bulk of the work was already done by previous patches.
Use defaults_enabled() to determine whether we need to create the
default devices or not.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
---
The QOM relat
On Fri, 12 Aug 2022 09:03:02 -0700
Dan Williams wrote:
> Jonathan Cameron wrote:
> > On Thu, 11 Aug 2022 18:08:57 +0100
> > Jonathan Cameron via wrote:
> >
> > > On Tue, 9 Aug 2022 17:08:25 +0100
> > > Jonathan Cameron wrote:
> > >
> > > > On Tue, 9 Aug 2022 21:07:06 +0800
> > > > Bobo WL
On 11/08/2022 18:39, Daniel Henrique Barboza wrote:
Enable pnv-phb user created devices for powernv9 now that we have
everything in place.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
---
Same comment as in patch 6 regarding the QOM relationship of the
user-creat
Jonathan Cameron wrote:
> On Thu, 11 Aug 2022 18:08:57 +0100
> Jonathan Cameron via wrote:
>
> > On Tue, 9 Aug 2022 17:08:25 +0100
> > Jonathan Cameron wrote:
> >
> > > On Tue, 9 Aug 2022 21:07:06 +0800
> > > Bobo WL wrote:
> > >
> > > > Hi Jonathan
> > > >
> > > > Thanks for your reply!
>
On 11/08/2022 18:39, Daniel Henrique Barboza wrote:
User creatable root ports are being parented by the 'peripheral' or the
'peripheral-anon' container. This happens because this is the regular
QOM schema for sysbus devices that are added via the command line.
Let's make this QOM hierarchy si
On Wed, Aug 3, 2022 at 1:30 PM Peter Maydell wrote:
> The problem with a patch like this is that it rolls up into a
> single patch changes to the API of many functions in multiple
> subsystems across the whole codebase. Some of those changes
> might be right; some might be wrong. No single person
On Thu, Aug 4, 2022 at 12:44 PM Marc-André Lureau
wrote:
> Hi
>
> Great work so far! This seems easier to hack than my attempt to use
> clang-tidy to write some qemu checks
> (https://github.com/elmarco/clang-tools-extra)
>
> The code seems quite generic, I wonder if such a tool in python wasn't
>
On Thu, 11 Aug 2022 18:08:57 +0100
Jonathan Cameron via wrote:
> On Tue, 9 Aug 2022 17:08:25 +0100
> Jonathan Cameron wrote:
>
> > On Tue, 9 Aug 2022 21:07:06 +0800
> > Bobo WL wrote:
> >
> > > Hi Jonathan
> > >
> > > Thanks for your reply!
> > >
> > > On Mon, Aug 8, 2022 at 8:37 PM Jonat
On 11/08/2022 18:39, Daniel Henrique Barboza wrote:
Given that powernv9 and powernv10 uses the same pnv-phb backend, the
logic to allow user created pnv-phbs for powernv10 is already in place.
Let's flip the switch.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
---
On 11/08/2022 18:39, Daniel Henrique Barboza wrote:
The function assumes that we're always dealing with a PNV9_CHIP()
object. This is not the case when the pnv-phb device belongs to a
powernv10 machine.
Change pnv_phb4_get_pec() to be able to work with PNV10_CHIP() if
necessary.
Signed-off-b
On 11/08/2022 18:39, Daniel Henrique Barboza wrote:
The PHB4 backend relies on a link with the corresponding PEC element.
This is trivial to do during machine_init() time for default devices,
but not so much for user created ones.
pnv_phb4_get_pec() is a small variation of the function that w
In more recent Raspbian OS Linux kernels, the fb driver gives up
immediately if RPI_FIRMWARE_FRAMEBUFFER_GET_NUM_DISPLAYS fails or no
displays are reported.
This change simply always reports one display. It makes bcm2835_fb work
again with these more recent kernels.
Signed-off-by: Enrik Berkhan
On Fri, 12 Aug 2022 10:25:55 +0100,
Peter Maydell wrote:
>
> I've added some more relevant mailing lists to the cc.
>
> On Fri, 12 Aug 2022 at 09:45, Vitaly Chikunov wrote:
> > On Fri, Aug 12, 2022 at 05:14:27AM +0300, Vitaly Chikunov wrote:
> > > I noticed that we starting to get many errors l
On 11.08.2022 17:00, Alexander Ivanov wrote:
Fix image inflation when offset in BAT is out of image.
Replace whole BAT syncing by flushing only dirty blocks.
Move all the checks outside the main check function in
separate functions
Use WITH_QEMU_LOCK_GUARD for more clean code.
Alexander Ivano
On Thu, 2022-08-11 at 08:42 -0700, Richard Henderson wrote:
> On 8/11/22 02:28, Ilya Leoshkevich wrote:
> > How is qemu-user's get_page_addr_code() involved here?
> >
> > I tried to experiment with it, and while I agree that it looks
> > buggy,
> > it's called only from translation code paths. If
On Fri, Aug 12, 2022 at 03:51:53PM +0200, Hal Martin wrote:
> PATCH v1: add support for SMBIOS type 8 to qemu
> PATCH v2: incorporate patch v1 feedback and add smbios type=8 to qemu-options
history after --- pls
> internal_reference: internal reference designator
> external_reference: external re
On 11.08.2022 17:00, Alexander Ivanov wrote:
Replace the way we use mutex in parallels_co_check() for more clean code.
I think that "cleaness" is the same, but new code would be just shorter ;)
or less error prone.
v2: Fix an incorrect usage of WITH_QEMU_LOCK_GUARD.
Signed-off-by: Alexander I
On 11/08/2022 18:39, Daniel Henrique Barboza wrote:
When enabling user created PHBs (a change reverted by commit 9c10d86fee)
we were handling PHBs created by default versus by the user in different
manners. The only difference between these PHBs is that one will have a
valid phb3->chip that is
Hi Peter,
On Fri, 12 Aug 2022 10:25:55 +0100,
Peter Maydell wrote:
>
> I've added some more relevant mailing lists to the cc.
>
> On Fri, 12 Aug 2022 at 09:45, Vitaly Chikunov wrote:
> > On Fri, Aug 12, 2022 at 05:14:27AM +0300, Vitaly Chikunov wrote:
> > > I noticed that we starting to get ma
On 11/08/2022 18:39, Daniel Henrique Barboza wrote:
pnv_parent_qom_fixup() and pnv_parent_bus_fixup() are versions of the
helpers that were reverted by commit 9c10d86fee "ppc/pnv: Remove
user-created PHB{3,4,5} devices". They are needed to amend the QOM and
bus hierarchies of user created pnv-
On 11.08.2022 17:00, Alexander Ivanov wrote:
v2: Move fragmentation counting code to this function too.
same note here about ChnageLog and motivation
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 54 +++
1 file changed, 31 insertions(+
On 11.08.2022 17:00, Alexander Ivanov wrote:
v2: No changes.
same notes about motivation, changelog as before
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 85 +--
1 file changed, 52 insertions(+), 33 deletions(-)
diff --git a/block/pa
On Fri, 10 Jun 2022 at 17:07, Peter Maydell wrote:
>
> From: Richard Henderson
>
> With ARMv8, this field is always RES0.
> With ARMv7, targeting EL2 and TA=0, it is always 0xA.
I was just looking at this change again because we still
have the loose end of syn_simd_access_trap() not being used,
On 11.08.2022 17:00, Alexander Ivanov wrote:
v2: Move unrelated helper parallels_set_bat_entry creation to
a separate patch.
same notes as for previous patch
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 48 ++-
1 file changed, 35
On 11/08/2022 18:39, Daniel Henrique Barboza wrote:
We rely on the phb-id and chip-id, which are PHB properties, to assign
chassis and slot to the root port. For default devices this is no big
deal: the root port is being created under pnv_phb_realize() and the
values are being passed on via t
On 11.08.2022 17:00, Alexander Ivanov wrote:
v2: Revert the condition with s->header_unclean.
same comment about change log as previously
And commit message misses motivation part, why we are
doing this rework. What is the goal of this change?
The code part is clean.
Signed-off-by: Alexander
On 11/08/2022 18:39, Daniel Henrique Barboza wrote:
For default root ports we have a way of accessing chassis and slot,
before root_port_realize(), via pnv_phb_attach_root_port(). For the
future user created root ports this won't be the case: we can't use
this helper because we don't have acce
On 11/08/2022 18:39, Daniel Henrique Barboza wrote:
The same rationale provided in the PHB3 bus case applies here.
Note: we could have merged both buses in a single object, like we did
with the root ports, and spare some boilerplate. The reason we opted to
preserve both buses objects is twofo
Use generic infrastructure for BAT writing in parallels_co_check()
On 11.08.2022 17:00, Alexander Ivanov wrote:
It's too costly to write all the BAT to the disk. Let the flush function
write only dirty blocks.
Use parallels_set_bat_entry for setting a BAT entry and marking a relevant
block as di
On 11.08.2022 17:00, Alexander Ivanov wrote:
Will need to set BAT entry in multiple places.
Move the code of settings entries and marking relevant blocks dirty
to a separate helper parallels_set_bat_entry.
The comment and the patch text is ambiguous.
You say that we need to set BAT in multiple p
On Fri, 12 Aug 2022 at 15:11, Philipp Tomsich wrote:
>
> On Fri, 12 Aug 2022 at 16:01, Andrew Jones wrote:
> >
> > > Update the decode pattern to reflect the specification.
> >
> > I got hung-up on this for a bit since there isn't any "must-be-0" fields,
>
> Please refer to '“Zifencei” Instructio
Happy to lower it back into the decode file.
However, I initially pulled it up into the trans-function to more
closely match the ISA specification: there is only one FENCE
instruction with 3 arguments (FM, PRED, and SUCC).
One might argue that the decode table for "RV32I Base Instruction Set"
in th
On 11.08.2022 17:00, Alexander Ivanov wrote:
When an image is opened, data_end field in BDRVParallelsState
is setted as the biggest offset in the BAT plus cluster size.
If there is a corrupted offset pointing outside the image,
the image size increase accordingly. It potentially leads
to attempts
On Fri, 12 Aug 2022 at 16:01, Andrew Jones wrote:
>
> > Update the decode pattern to reflect the specification.
>
> I got hung-up on this for a bit since there isn't any "must-be-0" fields,
Please refer to '“Zifencei” Instruction-Fetch Fence, Version 2.0' in
the specification.
The encoding diagra
On Fri, Aug 12, 2022 at 03:13:04PM +0200, Philipp Tomsich wrote:
> Our decoding of fence-instructions is problematic in respect to the
> RISC-V ISA specification:
> - rs and rd are ignored, but need to be 0
> - fm is ignored
>
> This change adjusts the decode pattern to enfore rs and rd being 0,
>
Please use a cover-letter for multi-patch patch series.
On Fri, Aug 12, 2022 at 03:13:03PM +0200, Philipp Tomsich wrote:
> The RISC-V specification specifies imm12, rs1 and rd to be all-zeros,
> so we can't ignore these bits when decoding into fence.i.
>
> Update the decode pattern to reflect t
PATCH v1: add support for SMBIOS type 8 to qemu
PATCH v2: incorporate patch v1 feedback and add smbios type=8 to qemu-options
internal_reference: internal reference designator
external_reference: external reference designator
connector_type: hex value for port connector type (see SMBIOS 7.9.2)
por
This patch adds support for asynchronously tearing down a VM on Linux.
When qemu terminates, either naturally or because of a fatal signal,
the VM is torn down. If the VM is huge, it can take a considerable
amount of time for it to be cleaned up. In case of a protected VM, it
might take even longe
On Fri, 12 Aug 2022 at 14:17, Philipp Tomsich wrote:
>
> Our decoding of fence-instructions is problematic in respect to the
> RISC-V ISA specification:
> - rs and rd are ignored, but need to be 0
> - fm is ignored
>
> This change adjusts the decode pattern to enfore rs and rd being 0,
> and valid
The RISC-V specification specifies imm12, rs1 and rd to be all-zeros,
so we can't ignore these bits when decoding into fence.i.
Update the decode pattern to reflect the specification.
Signed-off-by: Philipp Tomsich
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deleti
Our decoding of fence-instructions is problematic in respect to the
RISC-V ISA specification:
- rs and rd are ignored, but need to be 0
- fm is ignored
This change adjusts the decode pattern to enfore rs and rd being 0,
and validates the fm-field (together with pred/succ for FENCE.TSO) to
determin
(I've added your rwth-aachen.de address because the quicinc
one seems to be bouncing :-( )
On Mon, 18 Jul 2022 at 12:54, Tobias Roehmel wrote:
>
> From: Tobias Röhmel
>
> Signed-off-by: Tobias Röhmel
Having looked a bit more carefully at the architecture
manual, I think this is not complete. I
On Mon, 18 Jul 2022 at 12:54, Tobias Roehmel wrote:
>
> From: Tobias Röhmel
>
> Cortex-R52 has the MPUIR register which has the same encoding
> has the MIDR alias with opc2=4. So we only add that alias
> when we are not realizing a Cortex-R.
>
> Signed-off-by: Tobias Röhmel
> ---
> target/arm/h
On Fri, 12 Aug 2022 at 12:44, wrote:
>
> From: Guoyi Tu
>
> qemu_socketpair() will create a pair of connected sockets
> with FD_CLOEXEC set
>
> Signed-off-by: Guoyi Tu
> ---
> include/qemu/sockets.h | 3 +++
> util/osdep.c | 24
> 2 files changed, 27 insertio
On Fri, 12 Aug 2022 08:38:59 -0300
Murilo Opsfelder Araújo wrote:
> On 8/12/22 04:26, Claudio Imbrenda wrote:
> > On Thu, 11 Aug 2022 23:05:52 -0300
> > Murilo Opsfelder Araújo wrote:
> >
> >> On 8/11/22 11:02, Daniel P. Berrangé wrote:
> >> [...]
> > Hmm, I was hoping you could just use
From: Marc-André Lureau
../tests/test-qobject-input-visitor.c: In function ‘test_visitor_in_list’:
../tests/test-qobject-input-visitor.c:454:49: warning: ‘%d’ directive output
may be truncated writing between 1 and 10 bytes into a region of size 6
[-Wformat-truncation=]
454 | snprintf
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