> On Aug 7, 2022, at 01:09, Richard Henderson
> wrote:
> All of the fpu operations are defined with TCG_CALL_NO_WG, but they
> all modify FCSR0. The most efficient way to fix this is to remove
> cpu_fcsr0, and instead use explicit load and store operations for the
> two instructions that man
> On Aug 7, 2022, at 00:18, Richard Henderson
> wrote:
>
> On 8/6/22 06:34, Qi Hu wrote:
>> In follow sequence:
>> movgr2fcsr $r0,$r0
>> movgr2fr.d $f0,$r0
>> fdiv.d $f0,$f0,$f0
>> movfcsr2gr $r12,$r0
>> The value of $r12 is "0x", but it should be "0x1010"(V flag).
>>
On 06.08.2022 22:45, Vladimir Sementsov-Ogievskiy wrote:
On 8/5/22 18:47, alexander.iva...@virtuozzo.com wrote:
From: Alexander Ivanov
There could be corruptions in the image file:
two guest memory areas refer to the same host cluster.
Is that written in parallels spec (docs/interop/parallel
On 8/5/22 18:47, alexander.iva...@virtuozzo.com wrote:
From: Alexander Ivanov
Check if original and duplicated offsets refer to the same cluster.
Repair the image and check that writing to a referred cluster
doesn't affects another referred cluster.
Signed-off-by: Natalia Kuzmina
Signed-off-b
On 8/5/22 18:47, alexander.iva...@virtuozzo.com wrote:
From: Alexander Ivanov
There could be corruptions in the image file:
two guest memory areas refer to the same host cluster.
Is that written in parallels spec (docs/interop/parallels.txt)?
Hmm yes: "- the value must be unique among all BA
On 8/5/22 18:47, alexander.iva...@virtuozzo.com wrote:
From: Alexander Ivanov
A bit strange to see this. Is your name set up correctly in ~/.gitconfig ?
We will add more and more checks of images so we need to reorganize the code.
Put each check to a separate helper function with a separate
All of the fpu operations are defined with TCG_CALL_NO_WG, but they
all modify FCSR0. The most efficient way to fix this is to remove
cpu_fcsr0, and instead use explicit load and store operations for the
two instructions that manipulate that value.
Cc: Qi Hu
Cc: Song Gao
Reported-by: Feiyang Ch
Hello,
Can I get some clarity about the fast path load/store to RAM memory for x86
systems guest? I would like to understand more about how Qemu read/write into
the guest RAM?
I’m trying to implement a type of cache to record the addresses being accessed
by load/store instructions.
Thank you
On Sat, 6 Aug 2022, Peter Maydell wrote:
On Sat, 6 Aug 2022 at 12:24, BALATON Zoltan wrote:
I may look at it later when Peter's second patch changing
this code lands if there are any cleanups possible
You mean the 2nd patch I sent in that RFC series? I'm not
Yes I mean that patch.
current
On 8/6/22 06:34, Qi Hu wrote:
In follow sequence:
movgr2fcsr $r0,$r0
movgr2fr.d $f0,$r0
fdiv.d $f0,$f0,$f0
movfcsr2gr $r12,$r0
The value of $r12 is "0x", but it should be "0x1010"(V flag).
These fp helpers are definded with wrong flag "TCG_CALL_NO_WG" (but the
helper
On 8/2/22 15:31, Thomas Huth wrote:
It is possible to hit the assertTrue(delta_t < 2.0) on very loaded
systems. Increase the value to 5.0 to ease the situation a little bit.
Signed-off-by: Thomas Huth
---
See also https://lists.gnu.org/archive/html/qemu-devel/2022-07/msg03936.html
tests/qe
On 8/5/22 17:57, Emanuele Giuseppe Esposito wrote:
Am 05/08/2022 um 16:35 schrieb Vladimir Sementsov-Ogievskiy:
On 8/5/22 16:22, Emanuele Giuseppe Esposito wrote:
Am 27/07/2022 um 18:13 schrieb Vladimir Sementsov-Ogievskiy:
On 7/25/22 15:21, Emanuele Giuseppe Esposito wrote:
The aim of th
On Sat, 6 Aug 2022 at 12:24, BALATON Zoltan wrote:
> I may look at it later when Peter's second patch changing
> this code lands if there are any cleanups possible
You mean the 2nd patch I sent in that RFC series? I'm not
currently totally sure what I want to do with that. Looking
at the code and
On Sat, 6 Aug 2022 at 12:17, Daniel Henrique Barboza
wrote:
>
> Balaton,
>
> I had a change of heart. The code is too clear that it won't overflow.
> It felt overkill changing var types just for that.
>
> Peter already marked it as Ignored - False Positive in Coverity as well.
> So this would be a
In follow sequence:
movgr2fcsr $r0,$r0
movgr2fr.d $f0,$r0
fdiv.d $f0,$f0,$f0
movfcsr2gr $r12,$r0
The value of $r12 is "0x", but it should be "0x1010"(V flag).
These fp helpers are definded with wrong flag "TCG_CALL_NO_WG" (but the
helpers write the globle "fcsr"). This cau
On Sat, 6 Aug 2022, Daniel Henrique Barboza wrote:
Balaton,
I had a change of heart. The code is too clear that it won't overflow.
It felt overkill changing var types just for that.
Peter already marked it as Ignored - False Positive in Coverity as well.
So this would be a code change to "look
Balaton,
I had a change of heart. The code is too clear that it won't overflow.
It felt overkill changing var types just for that.
Peter already marked it as Ignored - False Positive in Coverity as well.
So this would be a code change to "look better". It didn't look particularly
better after th
On 8/5/22 21:30, BALATON Zoltan wrote:
On Fri, 5 Aug 2022, Daniel Henrique Barboza wrote:
Coverity reports a OVERFLOW_BEFORE_WIDEN issue in dcr_write_dma(). When
handling the DMA0_CR switch we're doing a multiplication between two
integers (count and width), and the product is assigned to an
On Fri, 5 Aug 2022, BALATON Zoltan wrote:
On Fri, 5 Aug 2022, Peter Maydell wrote:
On Fri, 5 Aug 2022 at 17:50, BALATON Zoltan wrote:
This also
allows to get the cpu without a link with something like:
PPC4XX_MACHINE(current_machine /* or qdev_get_machine() */)->soc.cpu
...and now you have
On 2022/8/5 02:23, Richard Henderson wrote:
On 8/4/22 10:29, Qi Hu wrote:
Signed-off-by: Qi Hu
---
disas.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/disas.c b/disas.c
index e31438f349..d44f46 100644
--- a/disas.c
+++ b/disas.c
@@ -176,6 +176,8 @@ static void initialize_debu
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