[PULL 00/60] semihosting patch queue

The following changes since commit 29f6db75667f44f3f01ba5037dacaf9ebd9328da: Merge tag 'pull-target-arm-20220627' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-06-27 16:47:39 +0530) are available in the Git repository at: https://gitlab.com/rth7680/qem

[PULL 41/60] semihosting: Fix docs comment for qemu_semihosting_console_inc

The implementation of qemu_semihosting_console_inc does not defer to gdbstub, but only reads from the fifo in console.c. Reviewed-by: Luc Michel Signed-off-by: Richard Henderson --- include/semihosting/console.h | 9 - 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/includ

[PULL 56/60] target/mips: Use an exception for semihosting

Within do_interrupt, we hold the iothread lock, which is required for Chardev access for the console, and for the round trip for use_gdb_syscalls(). Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/mips/cpu.h | 3 ++- target/mips/tcg/tcg-i

[PULL 35/60] semihosting: Split out semihost_sys_remove

Split out the non-ARM specific portions of SYS_REMOVE to a reusable function. Reviewed-by: Luc Michel Signed-off-by: Richard Henderson --- include/semihosting/syscalls.h | 3 +++ semihosting/arm-compat-semi.c | 13 +-- semihosting/syscalls.c | 40 ++

[PULL 38/60] semihosting: Create semihost_sys_{stat,fstat}

These syscalls will be used by m68k and nios2 semihosting. Reviewed-by: Luc Michel Signed-off-by: Richard Henderson --- include/semihosting/syscalls.h | 7 ++ semihosting/syscalls.c | 137 + 2 files changed, 144 insertions(+) diff --git a/include/semih

[PULL 06/12] docs/vhost-user: Fix mismerge

From: Kevin Wolf This reverts commit 76b1b64370007234279ea4cc8b09c98cbd2523de. The commit only duplicated some text that had already been merged in commit 31009d13cc5. Signed-off-by: Kevin Wolf Message-Id: <20220627134500.94842-2-kw...@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by

[PULL 34/60] semihosting: Split out semihost_sys_flen

The ARM-specific SYS_FLEN isn't really something that can be reused by other semihosting apis, but there are parts that can reused for the implementation of semihost_sys_fstat. Reviewed-by: Luc Michel Signed-off-by: Richard Henderson --- include/semihosting/syscalls.h | 4 ++ semihosting/arm-c

[PULL 53/60] semihosting: Create semihost_sys_poll_one

This will be used for implementing the xtensa select_one system call. Choose "poll" over "select" so that we can reuse Glib's g_poll constants and to avoid struct timeval. Reviewed-by: Luc Michel Signed-off-by: Richard Henderson --- include/semihosting/console.h | 16 include/semihos

[PULL 32/60] semihosting: Split out semihost_sys_lseek

Split out the non-ARM specific portions of SYS_SEEK to a reusable function. This handles all GuestFD. Isolate the curious ARM-specific return value processing to a new callback, common_semi_seek_cb. Expand the internal type of the offset to int64_t, and provide the whence argument, which will be

[PULL 36/60] semihosting: Split out semihost_sys_rename

Split out the non-ARM specific portions of SYS_RENAME to a reusable function. Reviewed-by: Luc Michel Signed-off-by: Richard Henderson --- include/semihosting/syscalls.h | 4 +++ semihosting/arm-compat-semi.c | 21 + semihosting/syscalls.c | 57

[PULL 03/12] vhost: add method vhost_set_vring_err

From: Konstantin Khlebnikov Kernel and user vhost may report virtqueue errors via eventfd. This is only reliable way to get notification about protocol error. Signed-off-by: Konstantin Khlebnikov Message-Id: <20220623161325.18813-2-vsement...@yandex-team.ru> Reviewed-by: Michael S. Tsirkin Sig

[PULL 31/60] semihosting: Bound length for semihost_sys_{read,write}

Fixes a minor bug in which a 64-bit guest on a 32-bit host could truncate the length. This would only ever cause a problem if there were no bits set in the low 32, so that it truncates to 0. Reviewed-by: Luc Michel Signed-off-by: Richard Henderson --- semihosting/syscalls.c | 16 ++

[PULL 51/60] semihosting: Use console_out_gf for SYS_WRITE0

Reviewed-by: Luc Michel Signed-off-by: Richard Henderson --- semihosting/arm-compat-semi.c | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c index d61b773f98..1a1e2a6960 100644 --- a/semihosting/arm-compa

[PULL 21/60] semihosting: Split is_64bit_semihosting per target

We already have some larger ifdef blocks for ARM and RISCV; split the function into multiple implementations per arch. Reviewed-by: Peter Maydell Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- semihosting/arm-compat-semi.c | 19 --- 1 file changed, 8 inserti

[PULL 02/12] msi: fix MSI vector limit check in msi_set_mask()

From: Jagannathan Raman MSI supports a maximum of PCI_MSI_VECTORS_MAX vectors - from 0 to PCI_MSI_VECTORS_MAX - 1. msi_set_mask() was previously using PCI_MSI_VECTORS_MAX as the upper limit for MSI vectors. Fix the upper limit to PCI_MSI_VECTORS_MAX - 1. Fixes: Coverity CID 1490141 Fixes: 08cf3

[PULL 42/60] semihosting: Pass CPUState to qemu_semihosting_console_inc

We don't need CPUArchState, and we do want the CPUState of the thread performing the operation -- use this instead of current_cpu. Reviewed-by: Luc Michel Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/semihosting/console.h | 4 ++-- linux-user/semihost.c | 2

[PULL 28/60] semihosting: Split out semihost_sys_close

Split out the non-ARM specific portions of SYS_CLOSE to a reusable function. This handles all GuestFD. Note that gdb_do_syscall %x reads target_ulong, not int. Reviewed-by: Luc Michel Signed-off-by: Richard Henderson --- include/semihosting/syscalls.h | 3 +++ semihosting/arm-compat-semi.c

[PULL 17/60] include/exec: Move gdb_stat and gdb_timeval to gdbstub.h

We have two copies of these structures, and require them in semihosting/ going forward. Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/gdbstub.h| 25 + target/m68k/m68k-semi.c | 32 +---

[PULL 40/60] gdbstub: Adjust gdb_syscall_complete_cb declaration

Change 'ret' to uint64_t. This resolves a FIXME in the m68k and nios2 semihosting that we've lost data. Change 'err' to int. There is nothing target-specific about the width of the errno value. Reviewed-by: Luc Michel Signed-off-by: Richard Henderson --- include/exec/gdbstub.h| 3 +--

[PULL 24/60] semihosting: Split out common-semi-target.h

Move the ARM and RISCV specific helpers into their own header file. Reviewed-by: Alex Bennée Reviewed-by: Luc Michel Signed-off-by: Richard Henderson --- target/arm/common-semi-target.h | 62 target/riscv/common-semi-target.h | 50 semihosting/arm-compat

[PATCH v7 2/4] target/riscv: Set minumum priv spec version for mcountinhibit

The minimum priv spec versino for mcountinhibit to v1.11 so that it is not available for v1.10 (or lower). Fixes: eab4776b2bad ("target/riscv: Add support for hpmcounters/hpmevents") Signed-off-by: Anup Patel --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --gi

[PULL 14/60] semihosting: Move common-semi.h to include/semihosting/

This header is not private to the top-level semihosting directory, so place it in the public include directory. Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- {semihosting => include/semihosting}/common-semi.h | 0 1 file changed, 0 insertions(+), 0 de

[PULL 23/60] semihosting: Split out common_semi_has_synccache

We already have some larger ifdef blocks for ARM and RISCV; split out a boolean test for SYS_SYNCCACHE. Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- semihosting/arm-compat-semi.c | 20 +--- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/semi

Re: [PATCH 11/12] acpi/tests/bits: add README file for bits qtests

On Tue, Jun 28, 2022 at 3:56 AM Michael S. Tsirkin wrote: > > On Mon, Jun 27, 2022 at 12:58:55PM +0530, Ani Sinha wrote: > > The README file is added describing the directory structure and the purpose > > of every file it contains. It also describes how to add new tests, make > > changes > > to e

[PATCH v7 1/4] Revert "target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher"

This reverts commit 33cc1c0b69e457f5c526f64297353cba6f7bfdb4 because commit eab4776b2badd4088a4f807c9bb3dc453c53dc23 already implements proper mcountinhibit CSR emulation. Signed-off-by: Anup Patel --- target/riscv/cpu_bits.h | 3 --- target/riscv/csr.c | 2 -- 2 files changed, 5 deletions(

[PULL 13/60] semihosting: Return void from do_common_semihosting

Perform the cleanup in the FIXME comment in common_semi_gdb_syscall. Do not modify guest registers until the syscall is complete, which in the gdbstub case is asynchronous. In the synchronous non-gdbstub case, use common_semi_set_ret to set the result. Merge set_swi_errno into common_semi_cb. Rel

[PULL 29/60] semihosting: Split out semihost_sys_read

Split out the non-ARM specific portions of SYS_READ to a reusable function. This handles all GuestFD. Isolate the curious ARM-specific return value processing to a new callback, common_semi_rw_cb. Note that gdb_do_syscall %x reads target_ulong, not int. Reviewed-by: Luc Michel Signed-off-by: R

[PULL 19/60] gdbstub: Convert GDB error numbers to host error numbers

Provide the callback with consistent state -- always use host error numbers. The individual callback can then decide if the errno requires conversion for the guest. Reviewed-by: Luc Michel Signed-off-by: Richard Henderson --- gdbstub.c | 31 +++ 1 file changed, 31 i

[PATCH v4 45/45] linux-user/aarch64: Add SME related hwcap entries

Signed-off-by: Richard Henderson --- linux-user/elfload.c | 20 1 file changed, 20 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 163fc8a1ee..a496c37855 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -605,6 +605,18 @@ enum {

[PULL 12/60] semihosting: Clean up common_semi_open_cb

Use common_semi_cb to return results instead of calling set_swi_errno and common_semi_set_ret directly. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- semihosting/arm-compat-semi.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/semihosting/arm-compat-se

[PULL 30/60] semihosting: Split out semihost_sys_write

Split out the non-ARM specific portions of SYS_WRITE to a reusable function. This handles all GuestFD. This removes the last use of common_semi_syscall_len. Note that gdb_do_syscall %x reads target_ulong, not int. Reviewed-by: Luc Michel Signed-off-by: Richard Henderson --- include/semihosti

[PULL 18/60] include/exec: Define errno values in gdbstub.h

Define constants for the errno values defined by the gdb remote fileio protocol. Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/gdbstub.h | 22 ++ 1 file changed, 22 insertions(+) diff --git a/include/exec/gdbstub.h b/

[PULL 06/60] semihosting: Add target_strlen for softmmu-uaccess.h

Mirror the interface of the user-only function of the same name. Use probe_access_flags for the common case of ram, and cpu_memory_rw_debug for the uncommon case of mmio. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Use probe_access_flags (pmm) --- include/semihosting/sof

[PATCH v4 41/45] linux-user: Rename sve prctls

Add "sve" to the sve prctl functions, to distinguish them from the coming "sme" prctls with similar names. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_prctl.h | 8 linux-user/syscall.c | 12 ++-- 2 files changed, 10 insertions(+), 10 deletions(-)

[PULL 09/60] semihosting: Inline set_swi_errno into common_semi_cb

Do not store 'err' into errno only to read it back immediately. Use 'ret' for the return value, not 'reg0'. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- semihosting/arm-compat-semi.c | 19 ++- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/semi

[PULL 10/60] semihosting: Adjust error checking in common_semi_cb

The err parameter is non-zero if and only if an error occured. Use this instead of ret == -1 for determining if we need to update the saved errno. This fixes the errno setting of SYS_ISTTY, which returns 0 on error, not -1. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- semihost

[PULL 01/60] semihosting: Move exec/softmmu-semi.h to semihosting/softmmu-uaccess.h

We have a subdirectory for semihosting; move this file out of exec. Rename to emphasize the contents are a replacement for the functions in linux-user/bsd-user uaccess.c. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- .../{exec/softmmu-semi.h => semihosting/softmmu-uaccess.h}

[PULL 04/60] semihosting: Move softmmu-uaccess.h functions out of line

Rather that static (and not even inline) functions within a header, move the functions to semihosting/uaccess.c. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/semihosting/softmmu-uaccess.h | 42 +++--- semihosting/uaccess.c | 51

[PULL 08/12] libvhost-user: Fix VHOST_USER_ADD_MEM_REG reply

From: Kevin Wolf With REPLY_NEEDED, libvhost-user sends both the acutal result and an additional ACK reply for VHOST_USER_ADD_MEM_REG. This is incorrect, the spec mandates that it behave the same with and without REPLY_NEEDED because it always sends a reply. Fixes: ec94c8e621de96c50c2d381c8c9ec9

[PULL 05/60] accel/stubs: Add tcg stub for probe_access_flags

Reviewed-by: Luc Michel Signed-off-by: Richard Henderson --- accel/stubs/tcg-stub.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c index ea4a0dd2fb..6ce8a34228 100644 --- a/accel/stubs/tcg-stub.c +++ b/accel/stubs/tcg-stub.c @@ -21,6 +2

[PATCH v4 39/45] linux-user/aarch64: Move sve record checks into restore

Move the checks out of the parsing loop and into the restore function. This more closely mirrors the code structure in the kernel, and is slightly clearer. Reject rather than silently skip incorrect VL and SVE record sizes. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 51

[PULL 02/60] semihosting: Return failure from softmmu-uaccess.h functions

We were reporting unconditional success for these functions; pass on any failure from cpu_memory_rw_debug. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/semihosting/softmmu-uaccess.h | 91 --- 1 file changed, 39 insertions(+), 52 deletions(-) d

[PULL 12/12] include/hw/virtio: document vhost_ack_features

From: Alex Bennée Signed-off-by: Alex Bennée Message-Id: <20220524154056.2896913-5-alex.ben...@linaro.org> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: Stefan Hajnoczi --- include/hw/virtio/vhost.h | 10 ++ 1 file changed, 10 insertions(+) diff --gi

[PULL 03/60] semihosting: Improve condition for config.c and console.c

While CONFIG_SEMIHOSTING is currently only set for softmmu, this will not continue to be true. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- semihosting/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/semihosting/meson.build b/semihosting/meson.

[PATCH v4 38/45] linux-user/aarch64: Verify extra record lock succeeded

Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 8fbe98d72f..9ff79da4be 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -340,6 +340,

[PULL 11/12] include/hw/virtio: document vhost_get_features

From: Alex Bennée Signed-off-by: Alex Bennée Message-Id: <20220524154056.2896913-4-alex.ben...@linaro.org> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: Stefan Hajnoczi --- include/hw/virtio/vhost.h | 11 +++ 1 file changed, 11 insertions(+) diff --g

[PATCH v4 35/45] linux-user/aarch64: Add SM bit to SVE signal context

Make sure to zero the currently reserved fields. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 7da0e36c6d..3cef2f44cf 100644 --- a/linux-

[PULL 05/12] virtio-iommu: Fix migration regression

From: Zhenzhong Duan We also need to switch to the right address space on dest side after loading the device status. DMA to wrong address space is destructive. Fixes: 3facd774962fd ("virtio-iommu: Add bypass mode support to assigned device") Suggested-by: Eric Auger Signed-off-by: Zhenzhong Du

[PULL 10/12] contrib/vhost-user-blk: fix 32 bit build and enable

From: Alex Bennée We were not building the vhost-user-blk server due to 32 bit compilation problems. The problem was due to format string types so fix that and then enable the build. Tweak the rule to follow the same rules as other vhost-user daemons. Signed-off-by: Alex Bennée Message-Id: <202

[PULL 09/12] MAINTAINERS: Collect memory device files in "Memory devices"

From: David Hildenbrand Xiao Guangrong doesn't have enough time to actively review or contribute to our NVDIMM implementation. Let's dissolve the "NVDIMM" section, moving relevant ACPI parts to "ACPI/SMBIOS" and moving memory device stuff into a new "Memory devices" section. Make that new section

[PATCH v4 34/45] linux-user/aarch64: Reset PSTATE.SM on syscalls

Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 9 + 1 file changed, 9 insertions(+) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 3b273f6299..4af6996d57 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c

[PULL 00/12] virtio: fixes

The following changes since commit 097ccbbbaf2681df1e65542e5b7d2b2d0c66e2bc: Merge tag 'qemu-sparc-20220626' of https://github.com/mcayland/qemu into staging (2022-06-27 05:21:05 +0530) are available in the Git repository at: git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_upstr

[PULL 07/12] libvhost-user: Fix VHOST_USER_GET_MAX_MEM_SLOTS reply

From: Kevin Wolf With REPLY_NEEDED, libvhost-user sends both the acutal result and an additional ACK reply for VHOST_USER_GET_MAX_MEM_SLOTS. This is incorrect, the spec mandates that it behave the same with and without REPLY_NEEDED because it always sends a reply. Fixes: 6fb2e173d20c9bbb5466183d

[PULL 01/12] virtio-iommu: Fix the partial copy of probe request

From: Zhenzhong Duan The structure of probe request doesn't include the tail, this leads to a few field missed to be copied. Currently this isn't an issue as those missed field belong to reserved field, just in case reserved field will be used in the future. Changed 4th parameter of virtio_iommu

[PATCH v4 32/45] target/arm: Enable SME for -cpu max

Note that SME remains effectively disabled for user-only, because we do not yet set CPACR_EL1.SMEN. This needs to wait until the kernel ABI is implemented. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- docs/system/arm/emulation.rst | 4 target/arm/cpu64.c| 1

[PATCH v4 43/45] target/arm: Only set ZEN in reset if SVE present

There's no reason to set CPACR_EL1.ZEN if SVE disabled. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4a35890853..20cb622083 100644 --- a/target/arm/cpu.c +++ b/target/arm

[PATCH v7 4/4] target/riscv: Force disable extensions if priv spec version does not match

We should disable extensions in riscv_cpu_realize() if minimum required priv spec version is not satisfied. This also ensures that machines with priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter extensions. Fixes: a775398be2e9 ("target/riscv: Add isa extenstion strings to the

[PATCH v4 26/45] target/arm: Implement FMOPA, FMOPS (widening)

Signed-off-by: Richard Henderson --- target/arm/helper-sme.h| 2 ++ target/arm/sme.decode | 1 + target/arm/sme_helper.c| 68 ++ target/arm/translate-sme.c | 1 + 4 files changed, 72 insertions(+) diff --git a/target/arm/helper-sme.h b/target/a

[PATCH v7 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

We should write transformed instruction encoding of the trapped instruction in [m|h]tinst CSR at time of taking trap as defined by the RISC-V privileged specification v1.12. Reviewed-by: Alistair Francis Signed-off-by: Anup Patel --- target/riscv/cpu.h| 5 + target/riscv/cpu_helper.c

[PULL 04/12] vhost: setup error eventfd and dump errors

From: Konstantin Khlebnikov Vhost has error notifications, let's log them like other errors. For each virt-queue setup eventfd for vring error notifications. Signed-off-by: Konstantin Khlebnikov [vsementsov: rename patch, change commit message and dump error like other errors in t

[PATCH v7 0/4] QEMU RISC-V nested virtualization fixes

This series does fixes and improvements to have nested virtualization on QEMU RISC-V. These patches can also be found in riscv_nested_fixes_v7 branch at: https://github.com/avpatel/qemu.git The RISC-V nested virtualization was tested on QEMU RISC-V using Xvisor RISC-V which has required hyperviso

[PATCH v4 18/45] target/arm: Implement SME ZERO

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v4: Fix ZA[] comment in helper_sme_zero. --- target/arm/helper-sme.h| 2 ++ target/arm/sme.decode | 4 target/arm/sme_helper.c| 25 + target/arm/translate-sme.c | 13 + 4 files

[PATCH v4 31/45] target/arm: Reset streaming sve state on exception boundaries

We can handle both exception entry and exception return by hooking into aarch64_sve_change_el. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 15 +-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/ar

[PATCH v4 44/45] target/arm: Enable SME for user-only

Enable SME, TPIDR2_EL0, and FA64 if supported by the cpu. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 20cb622083..87d836fb2f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @

[PATCH v4 21/45] target/arm: Export unpredicated ld/st from translate-sve.c

Add a TCGv_ptr base argument, which will be cpu_env for SVE. We will reuse this for SME save and restore array insns. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 3 +++ target/arm/translate-sve.c | 48 -- 2 fi

[PATCH v4 42/45] linux-user/aarch64: Implement PR_SME_GET_VL, PR_SME_SET_VL

These prctl set the Streaming SVE vector length, which may be completely different from the Normal SVE vector length. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_prctl.h | 48 +++ linux-user/syscall.c | 16 +++ 2 files changed,

[PATCH v4 33/45] linux-user/aarch64: Clear tpidr2_el0 if CLONE_SETTLS

Signed-off-by: Richard Henderson --- linux-user/aarch64/target_cpu.h | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/target_cpu.h b/linux-user/aarch64/target_cpu.h index 97a477bd3e..f90359faf2 100644 --- a/linux-user/aarch64/target_cpu.h +++ b/linux-user

[PATCH v4 28/45] target/arm: Implement PSEL

This is an SVE instruction that operates using the SVE vector length but that it is present only if SME is implemented. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sve.decode | 20 + target/arm/translate-sve.c | 57

[PATCH v4 20/45] target/arm: Implement SME LD1, ST1

We cannot reuse the SVE functions for LD[1-4] and ST[1-4], because those functions accept only a Zreg register number. For SME, we want to pass a pointer into ZA storage. Signed-off-by: Richard Henderson --- target/arm/helper-sme.h| 82 + target/arm/sme.decode | 9 + target/arm/s

[PATCH v4 30/45] target/arm: Implement SCLAMP, UCLAMP

This is an SVE instruction that operates using the SVE vector length but that it is present only if SME is implemented. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h| 18 +++ target/arm/sve.decode | 5 ++ target/arm/translate-sve.c | 102

[PATCH v4 17/45] target/arm: Implement SME RDSVL, ADDSVL, ADDSPL

These SME instructions are nominally within the SVE decode space, so we add them to sve.decode and translate-sve.c. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v4: Add streaming_{vec,pred}_reg_size. --- target/arm/translate-a64.h | 12 target/arm/sve.decode

[PATCH v4 40/45] linux-user/aarch64: Implement SME signal handling

Set the SM bit in the SVE record on signal delivery, create the ZA record. Restore SM and ZA state according to the records present on return. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 162 +--- 1 file changed, 151 insertions(+), 11 deleti

[PATCH v4 25/45] target/arm: Implement BFMOPA, BFMOPS

Signed-off-by: Richard Henderson --- target/arm/helper-sme.h| 2 ++ target/arm/sme.decode | 2 ++ target/arm/sme_helper.c| 52 ++ target/arm/translate-sme.c | 30 ++ 4 files changed, 86 insertions(+) diff --git a/target/arm/h

[PATCH v4 29/45] target/arm: Implement REVD

This is an SVE instruction that operates using the SVE vector length but that it is present only if SME is implemented. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 2 ++ target/arm/sve.decode | 1 + target/arm/sve_helper.c| 16

[PATCH v4 37/45] linux-user/aarch64: Do not allow duplicate or short sve records

In parse_user_sigframe, the kernel rejects duplicate sve records, or records that are smaller than the header. We were silently allowing these cases to pass, dropping the record. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 5 - 1 file changed, 4 insertions(+), 1 delet

[PATCH v4 22/45] target/arm: Implement SME LDR, STR

We can reuse the SVE functions for LDR and STR, passing in the base of the ZA vector and a zero offset. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme.decode | 7 +++ target/arm/translate-sme.c | 24 2 files changed, 31 insertio

[PATCH v4 14/45] target/arm: Mark LD1RO as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 3 --- target/arm/translate-sve.c | 2 ++ 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/target/ar

[PATCH v4 36/45] linux-user/aarch64: Tidy target_restore_sigframe error return

Fold the return value setting into the goto, so each point of failure need not do both. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 26 +++--- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch

[PATCH v4 24/45] target/arm: Implement FMOPA, FMOPS (non-widening)

Signed-off-by: Richard Henderson --- target/arm/helper-sme.h| 5 +++ target/arm/sme.decode | 9 ++ target/arm/sme_helper.c| 63 ++ target/arm/translate-sme.c | 32 +++ 4 files changed, 109 insertions(+) diff --git a/target/ar

[PATCH v4 19/45] target/arm: Implement SME MOVA

We can reuse the SVE functions for implementing moves to/from horizontal tile slices, but we need new ones for moves to/from vertical tile slices. Signed-off-by: Richard Henderson --- target/arm/helper-sme.h| 12 target/arm/helper-sve.h| 2 + target/arm/translate-a64.h | 8 +++

[PATCH v4 12/45] target/arm: Mark gather prefetch as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. In this case, introduce PRF_ns (prefetch non-streaming) to handle the checks. Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 3 --- target/arm/sve.decode

[PATCH v4 23/45] target/arm: Implement SME ADDHA, ADDVA

Signed-off-by: Richard Henderson --- v4: Drop restrict. --- target/arm/helper-sme.h| 5 +++ target/arm/sme.decode | 11 + target/arm/sme_helper.c| 90 ++ target/arm/translate-sme.c | 31 + 4 files changed, 137 insertions(+) diff -

[PATCH v4 11/45] target/arm: Mark gather/scatter load/store as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 9 - target/arm/translate-sve.c | 6 ++ 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a

[PATCH v4 27/45] target/arm: Implement SME integer outer product

This is SMOPA, SUMOPA, USMOPA_s, UMOPA, for both Int8 and Int16. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sme.h| 16 target/arm/sme.decode | 10 + target/arm/sme_helper.c| 82 ++ target/arm/tr

[PATCH v4 16/45] target/arm: Handle SME in sve_access_check

The pseudocode for CheckSVEEnabled gains a check for Streaming SVE mode, and for SME present but SVE absent. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 22 -- 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/target/arm/translate-a64.c b/ta

[PATCH v4 05/45] target/arm: Mark RDFFR, WRFFR, SETFFR as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 2 -- target/arm/translate-sve.c | 9 ++--- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/tar

[PATCH v4 10/45] target/arm: Mark string/histo/crypto as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 1 - target/arm/translate-sve.c | 35 ++- 2 files changed, 18 insertions(+), 18 d

[PATCH v4 07/45] target/arm: Mark PMULL, FMMLA as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 2 -- target/arm/translate-sve.c | 18 ++ 2 files changed, 10 insertions(+), 10 deletions(-) dif

[PATCH v4 04/45] target/arm: Mark ADR as non-streaming

Mark ADR as a non-streaming instruction, which should trap if full a64 support is not enabled in streaming mode. Removing entries from sme-fa64.decode is an easy way to see what remains to be done. Signed-off-by: Richard Henderson --- target/arm/translate.h | 7 +++ target/arm/sme-fa64.

[PATCH v4 08/45] target/arm: Mark FTSMUL, FTMAD, FADDA as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 3 --- target/arm/translate-sve.c | 15 +++ 2 files changed, 11 insertions(+), 7 deletions(-) diff -

[PATCH v4 15/45] target/arm: Add SME enablement checks

These functions will be used to verify that the cpu is in the correct state for a given instruction. Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 21 + target/arm/translate-a64.c | 34 ++ 2 files changed, 55 insertions(+)

[PATCH v4 06/45] target/arm: Mark BDEP, BEXT, BGRP, COMPACT, FEXPA, FTSSEL as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 3 --- target/arm/translate-sve.c | 22 -- 2 files changed, 12 insertions(+), 13 deletions(-)

[PATCH v4 13/45] target/arm: Mark LDFF1 and LDNF1 as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 2 -- target/arm/translate-sve.c | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm

[PATCH v4 03/45] target/arm: Trap non-streaming usage when Streaming SVE is active

This new behaviour is in the ARM pseudocode function AArch64.CheckFPAdvSIMDEnabled, which applies to AArch32 via AArch32.CheckAdvSIMDOrFPEnabled when the EL to which the trap would be delivered is in AArch64 mode. Given that ARMv9 drops support for AArch32 outside EL0, the trap EL detection ought

[PATCH v4 01/45] target/arm: Handle SME in aarch64_cpu_dump_state

Dump SVCR, plus use the correct access check for Streaming Mode. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 17 - 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index bb44ad45aa..4a35890853 100644 --- a/target/arm/cp

[PATCH v4 09/45] target/arm: Mark SMMLA, UMMLA, USMMLA as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 1 - target/arm/translate-sve.c | 12 ++-- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a

[PATCH v4 02/45] target/arm: Add infrastructure for disas_sme

This includes the build rules for the decoder, and the new file for translation, but excludes any instructions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 1 + target/arm/sme.decode | 20 target/arm/translate-a64.c |

[PATCH v4 00/45] target/arm: Scalable Matrix Extension

Changes for v4: * Rebase on mainline (20 patches upstreamed). * Adjust sve_access_check when PSTATE.SM set. * Adjust sve insns to indicate not valid while streaming. * Other misc adjustments per review. r~ Richard Henderson (45): target/arm: Handle SME in aarch64_cpu_dump_state targ

Re: [PATCH 2/2] tap: initialize TAPState->enabled according to the actual state of queue

在 2022/6/14 19:21, Andrey Ryabinin 写道: Currently TAPState->enabled initialized as true. If fd was passed to qemu in a disabled state it will cause an assert at the attempt to detach queue in virtio_net_set_queues(): virtio_net_set_queues() : r = peer_detach() -> tap_disable():

Re: [PATCH v6 4/4] target/riscv: Force disable extensions if priv spec version does not match

On Tue, Jun 28, 2022 at 4:47 AM Alistair Francis wrote: > > On Sat, Jun 11, 2022 at 6:07 PM Anup Patel wrote: > > > > We should disable extensions in riscv_cpu_realize() if minimum required > > priv spec version is not satisfied. This also ensures that machines with > > priv spec v1.11 (or lower)

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