The MIPS n32 ABI is basically n64 with the address space (i.e. pointer
width) shrinked to 32 bits. Meanwhile the current code treats it as
o32-like based on TARGET_ABI_BITS, which causes problems with n32
syscalls utilizing 64-bit offsets, like pread64, affecting most (if not
all) recently built n3
在 2022/3/12 下午2:28, ~eopxd 写道:
From: eopXD
According to v-spec (section 5.4):
When vstart ≥ vl, there are no body elements, and no elements are
updated in any destination vector register group, including that
no tail elements are updated with agnostic values.
Signed-off-by: eop Chen
Reviewe
在 2022/3/7 下午5:43, ~eopxd 写道:
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/vector_helper.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 6d79908ffe..9a08d14689 100
在 2022/3/7 下午5:38, ~eopxd 写道:
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
target/riscv/vector_helper.c| 12
2 files changed, 13 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.i
Is this waiting on me for anything?
I wanted to ensure this is wrapped up before starting a new project.
Thanks,
- David Miller
On Mon, Mar 7, 2022 at 11:09 PM David Miller wrote:
>
>
> I've reviewed all changes, looks good.
> Ran all of my own tests including vstrs, all passed.
>
> Thank you
Signed-off-by: Zongyuan Li
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/811
---
hw/arm/realview.c | 52 +++
1 file changed, 44 insertions(+), 8 deletions(-)
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index 7b424e94a5..741ed5c2c7 1006
This is a WIP patch set trying to resolve
https://gitlab.com/qemu-project/qemu/-/issues/811
which tries to totally remove 'qemu_irq_split', and
uses QOM object 'TYPE_SPLIT_IRQ' device instead.
I just want to make sure I'm on the right way.
Zongyuan Li (1):
hw/arm/realview: use qom to replace
> Am 18.03.2022 um 17:47 schrieb Stefano Garzarella :
>
> On Fri, Mar 18, 2022 at 04:48:18PM +0100, Peter Lieven wrote:
>>
>>
Am 18.03.2022 um 09:25 schrieb Stefano Garzarella :
>>>
>>> On Thu, Mar 17, 2022 at 07:27:05PM +0100, Peter Lieven wrote:
>> Am 17.03.2022 um 1
在 2022/3/19 下午8:50, ~eopxd 写道:
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, qemu should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s". An opt
在 2022/3/14 下午3:38, ~eopxd 写道:
From: eopXD
No functional change intended in this commit.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/vector_helper.c | 1132 +-
1 file changed, 565 insertions(+), 567 deletions(-)
diff --git a/target/
On Fri, 18 Mar 2022 at 14:09, Gerd Hoffmann wrote:
>
> The following changes since commit 1d60bb4b14601e38ed17384277aa4c30c57925d3:
>
> Merge tag 'pull-request-2022-03-15v2' of https://gitlab.com/thuth/qemu into
> staging (2022-03-16 10:43:58 +)
>
> are available in the Git repository at:
>
On 2022/03/19 22:56, Philippe Mathieu-Daudé wrote:
Hi Akihiko, Paolo, Peter.
On 17/3/22 13:55, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
Posting v4 in case someone want to iterate.
Pending issue raised by Akihiko Odaki:
* this actually breaks the "runas" option with ui/coco
在 2022/3/7 下午3:32, ~eopxd 写道:
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 5 +
target/riscv/vector_helper.c| 311 +---
2 files changed, 178 insertions(+), 138 deletions(-)
diff --git a/targ
在 2022/3/1 下午5:07, ~eopxd 写道:
From: eopXD
This is the first commit regarding the tail agnostic behavior.
Added option 'rvv_ta_all_1s' to enable the behavior, the option
is default to false.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/cpu.c | 1
On 2022/03/19 22:49, Philippe Mathieu-Daudé wrote:
On 19/3/22 04:25, Akihiko Odaki wrote:
On 2022/03/19 1:14, Philippe Mathieu-Daudé wrote:
Commit 29cf16db23 says:
Since commits 0979ed017f0 ("meson: rename .inc.h files to .h.inc")
and 139c1837db7 ("meson: rename included C source files to .c.i
在 2022/3/12 下午2:28, ~eopxd 写道:
From: eopXD
According to v-spec (section 5.4):
When vstart ≥ vl, there are no body elements, and no elements are
updated in any destination vector register group, including that
no tail elements are updated with agnostic values.
Signed-off-by: eop Chen
Reviewe
Hi Akihiko, Paolo, Peter.
On 17/3/22 13:55, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
Posting v4 in case someone want to iterate.
Pending issue raised by Akihiko Odaki:
* this actually breaks the "runas" option with ui/cocoa.
[+NSApplication sharedApplication] calls isse
On 19/3/22 04:25, Akihiko Odaki wrote:
On 2022/03/19 1:14, Philippe Mathieu-Daudé wrote:
Commit 29cf16db23 says:
Since commits 0979ed017f0 ("meson: rename .inc.h files to .h.inc")
and 139c1837db7 ("meson: rename included C source files to .c.inc")
'git-diff --function-context' stopped displayin
On Sat, Mar 19, 2022 at 1:40 PM Ilya Dryomov wrote:
>
> On Fri, Mar 18, 2022 at 9:25 AM Stefano Garzarella
> wrote:
> >
> > On Thu, Mar 17, 2022 at 07:27:05PM +0100, Peter Lieven wrote:
> > >
> > >
> > >> Am 17.03.2022 um 17:26 schrieb Stefano Garzarella :
> > >>
> > >> Commit d24f80234b ("bloc
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/vector_helper.c | 16
1 file changed, 16 insertions(+)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 63746f3321..37dc0eb9b3 100644
--- a/target/riscv/vector_helper.c
From: eopXD
This is the first commit regarding the tail agnostic behavior.
Added option 'rvv_ta_all_1s' to enable the behavior, the option
is default to false.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 4
target/riscv/vector_helper.c| 27 +
2 files changed, 31 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/in
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/vector_helper.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 6d79908ffe..9a08d14689 100644
--- a/target/riscv/vector_helper
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 2 ++
target/riscv/vector_helper.c| 39 +
2 files changed, 41 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 11 +
target/riscv/vector_helper.c| 450 +---
2 files changed, 265 insertions(+), 196 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
target/riscv/vector_helper.c| 12
2 files changed, 13 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_r
From: eopXD
No functional change intended in this commit.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/vector_helper.c | 1132 +-
1 file changed, 565 insertions(+), 567 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/vector_helper.c | 220 ++-
1 file changed, 114 insertions(+), 106 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index ce96ae61dc..a025e4b640 10
From: eopXD
No functional change intended in this commit.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/vector_helper.c | 76 ++--
1 file changed, 38 insertions(+), 38 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/ve
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 5 +
target/riscv/vector_helper.c| 311 +---
2 files changed, 178 insertions(+), 138 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, qemu should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s". An option
'rvv_ta_all_1s' is added to ena
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 4
target/riscv/vector_helper.c| 24
2 files changed, 28 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/ins
From: eopXD
According to v-spec (section 5.4):
When vstart ≥ vl, there are no body elements, and no elements are
updated in any destination vector register group, including that
no tail elements are updated with agnostic values.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/risc
On Fri, Mar 18, 2022 at 9:25 AM Stefano Garzarella wrote:
>
> On Thu, Mar 17, 2022 at 07:27:05PM +0100, Peter Lieven wrote:
> >
> >
> >> Am 17.03.2022 um 17:26 schrieb Stefano Garzarella :
> >>
> >> Commit d24f80234b ("block/rbd: increase dynamically the image size")
> >> added a workaround to su
On 25/02/2022 08:01, Xiaojuan Yang wrote:
This series patch add softmmu support for LoongArch.
The latest kernel:
* https://github.com/loongson/linux/tree/loongarch-next
The latest uefi:
* https://github.com/loongson/edk2
* https://github.com/loongson/edk2-platforms
The manual:
* htt
On 25/02/2022 08:03, Xiaojuan Yang wrote:
This patch add ls7a rtc device support.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
MAINTAINERS| 1 +
hw/loongarch/Kconfig | 1 +
hw/loongarch/loongson3.c | 4 +
hw/rtc/Kconfig | 3 +
hw/r
On Thu, Mar 17, 2022 at 5:26 PM Stefano Garzarella wrote:
>
> Commit d24f80234b ("block/rbd: increase dynamically the image size")
> added a workaround to support growing images (eg. qcow2), resizing
> the image before write operations that exceed the current size.
>
> We recently added support fo
On 25/02/2022 08:02, Xiaojuan Yang wrote:
This patch realize the EIOINTC interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig| 3 +
hw/intc/loongarch_extioi.c | 417 +
hw/intc/meson.build
On 17/03/2022 10:45, Peter Maydell wrote:
On Wed, 16 Mar 2022 at 22:23, Alistair Francis wrote:
Hmm... This seems like a bug. We shouldn't allow the user to specify a
`-bios` option if using KVM. Would you mind preparing a patch to catch
this?
You don't want to allow the possibility of a b
On 25/02/2022 08:02, Xiaojuan Yang wrote:
This patch realize the PCH-PIC interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 4 +
hw/intc/loongarch_pch_pic.c | 488
hw/intc/meson.build
On 25/02/2022 08:02, Xiaojuan Yang wrote:
This patch realize the IPI interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
MAINTAINERS | 2 +
hw/intc/Kconfig | 3 +
hw/intc/loongarch_ipi.c | 164 +
On 25/02/2022 08:02, Xiaojuan Yang wrote:
Emulate a 3A5000 board use the new loongarch instruction.
3A5000 belongs to the Loongson3 series processors.
The board consists of a 3A5000 cpu model and the virt
bridge. The host 3A5000 board is really complicated and
contains many functions.Now for the
On Fri, 18 Mar 2022 at 14:02, Laurent Vivier wrote:
>
> The following changes since commit 1d60bb4b14601e38ed17384277aa4c30c57925d3:
>
> Merge tag 'pull-request-2022-03-15v2' of https://gitlab.com/thuth/qemu into
> staging (2022-03-16 10:43:58 +)
>
> are available in the Git repository at:
On Fri, Mar 18, 2022 at 04:51:10PM -0300, Daniel Henrique Barboza wrote:
>
>
> On 3/18/22 00:43, David Gibson wrote:
> > On Thu, Mar 17, 2022 at 04:29:14PM +, Dr. David Alan Gilbert wrote:
> > > * Peter Maydell (peter.mayd...@linaro.org) wrote:
> > > > On Thu, 17 Mar 2022 at 14:03, Daniel Hen
On Fri, 18 Mar 2022 at 13:23, Peter Maydell wrote:
>
> Mostly straightforward bugfixes. The new Xilinx devices are
> arguably 'new feature', but they're fixing a regression where
> our changes to PSCI in commit 3f37979bf mean that EL3 guest
> code now needs to talk to a proper emulated power-contr
On 18/03/2022 15:06, Jonathan Cameron wrote:
From: Jonathan Cameron
Once a read or write reaches a CXL type 3 device, the HDM decoders
on the device are used to establish the Device Physical Address
which should be accessed. These functions peform the required maths
and then use a device spec
On 18/03/2022 15:06, Jonathan Cameron wrote:
From: Ben Widawsky
CXL host bridges themselves may have MMIO. Since host bridges don't have
a BAR they are treated as special for MMIO. This patch includes
i386/pc support.
Also hook up the device reset now that we have have the MMIO
space in which
On 18/03/2022 15:06, Jonathan Cameron via wrote:
From: Ben Widawsky
A CXL memory device (AKA Type 3) is a CXL component that contains some
combination of volatile and persistent memory. It also implements the
previously defined mailbox interface as well as the memory device
firmware interface.
From: Longpeng
Implements the .unrealize interface.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/vdpa-dev.c b/hw/virtio/vdpa-dev.c
index 4defe6c33d..1713818bc3 100644
--- a/hw/virtio/vdpa-dev.c
From: Longpeng
Implements the .realize interface.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev-pci.c | 18 -
hw/virtio/vdpa-dev.c | 132 +++
include/hw/virtio/vdpa-dev.h | 10 +++
3 files changed, 159 insertions(+), 1 deletion(-)
diff --git
From: Longpeng
Hi guys,
With the generic vDPA device, QEMU won't need to touch the device
types any more, such like vfio.
We can use the generic vDPA device as follow:
-device vhost-vdpa-device-pci,vdpa-dev=/dev/vhost-vdpa-X
I've done some simple tests on Huawei's offloading card (net, 0.95)
From: Longpeng
Implements the .set_status interface.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev.c | 100 ++-
1 file changed, 99 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/vdpa-dev.c b/hw/virtio/vdpa-dev.c
index 9536982061..c6847df7aa 100644
From: Longpeng
Implements the .get_features interface.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/vdpa-dev.c b/hw/virtio/vdpa-dev.c
index f28d3ed5f9..9536982061 100644
--- a/hw/virtio/vdpa-dev.c
+++ b/h
From: Longpeng
The generic vDPA device doesn't support migration currently, so
mark it as unmigratable temporarily.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/virtio/vdpa-dev.c b/hw/virtio/vdpa-dev.c
index c6847df7aa..5224617574 1006
From: Longpeng
Update linux headers to 5.xxx (kernel part is not merged yet)
To support generic vdpa deivce, we need add the following ioctls:
- VHOST_VDPA_GET_CONFIG_SIZE: get the configuration size.
- VHOST_VDPA_GET_VQS_COUNT: get the count of supported virtqueues.
Signed-off-by: Longpeng
--
From: Longpeng
Add the infrastructure of vdpa-dev (the generic vDPA device), we
can add a generic vDPA device as follow:
-device vhost-vdpa-device-pci,vdpa-dev=/dev/vhost-vdpa-X
Signed-off-by: Longpeng
---
hw/virtio/Kconfig| 5 +++
hw/virtio/meson.build| 2 ++
hw/virtio
From: Longpeng
Add helpers to get the "Transitional PCI Device ID" and "class_id"
of the device specified by the "Virtio Device ID".
These helpers will be used to build the generic vDPA device later.
Signed-off-by: Longpeng
---
hw/virtio/virtio-pci.c | 77 +
From: Longpeng
Implements the .get_config and .set_config interface.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/hw/virtio/vdpa-dev.c b/hw/virtio/vdpa-dev.c
index 1713818bc3..f28d3ed5f9 100644
--- a/hw/vir
From: Longpeng
Implements the .instance_init and the .class_init interface.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev-pci.c | 22 +++-
hw/virtio/vdpa-dev.c | 69 ++--
include/hw/virtio/vdpa-dev.h | 3 ++
3 files changed, 91 insertions(+
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