From: Alistair Francis
The RISC-V specification states that:
"Supervisor-level external interrupts are made pending based on the
logical-OR of the software-writable SEIP bit and the signal from the
external interrupt controller."
We currently only allow either the interrupt controller or s
Kshitij Suri writes:
> On 16/03/22 6:55 pm, Markus Armbruster wrote:
>> Kshitij Suri writes:
>>
>>> From: "kshitij.suri"
>>>
>>> Currently screendump only supports PPM format, which is un-compressed and
>>> not
>>> standard. Added a "format" parameter to qemu monitor screendump capabilites
>>>
From: Alistair Francis
The RISC-V specification states that:
"Supervisor-level external interrupts are made pending based on the
logical-OR of the software-writable SEIP bit and the signal from the
external interrupt controller."
We currently only allow either the interrupt controller or s
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ddda4906ff..41b757995d 10
Could you provide more detail, please? For a bug report it
is useful to know:
* what you were trying to do
* what happened
* what you expected to happen
* full details like the QEMU command line
* what guest software you were running
Ideally, the report should have everything we need to be
ab
On Wed, Mar 16, 2022 at 04:57:39PM +0100, Peter Krempa wrote:
> On Tue, Mar 08, 2022 at 12:34:38 +0100, Paolo Bonzini wrote:
> > From: Yang Zhong
> >
> > Kernel allocates 4K xstate buffer by default. For XSAVE features
> > which require large state component (e.g. AMX), Linux kernel
> > dynamical
Add a regression test for tcg indirect global lowering.
This appeared with nios2, with cps != 0, so that we use
indirection into the shadow register set. An indirect
call verifies alignment of rA. The use of rA was live
across the brcond leading to a tcg_debug_assert failure.
Cc: Alex Bennée
S
The runtime we build for Nios2 requires building a static archive,
so supply the ar tool for that case.
Cc: Alex Bennée
Signed-off-by: Richard Henderson
---
tests/tcg/Makefile.qemu | 7 +++
tests/tcg/configure.sh | 14 ++
2 files changed, 21 insertions(+)
diff --git a/tests/t
From: Amir Gonnen
Demonstrate how to use nios2 VIC on a machine.
Introduce a new machine property to attach a VIC.
When VIC is present, let the CPU know that it should use the
External Interrupt Interface instead of the Internal Interrupt Interface.
The devices on the machine are attached to the
Convert to contiguous allocation, as much as possible so far.
The two timer objects are not exposed for subobject allocation.
Reviewed-by: Mark Cave-Ayland
Signed-off-by: Richard Henderson
---
hw/nios2/10m50_devboard.c | 30 --
1 file changed, 16 insertions(+), 14 de
We want to move data from the heap into Nios2MachineState,
which is not possible with DEFINE_MACHINE.
Reviewed-by: Mark Cave-Ayland
Signed-off-by: Richard Henderson
---
hw/nios2/10m50_devboard.c | 24 ++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/hw/nio
When CRS = 0, we restore from estatus; otherwise from sstatus.
Update for the new CRS.
Signed-off-by: Richard Henderson
---
target/nios2/cpu.h | 1 +
target/nios2/op_helper.c | 3 ++-
target/nios2/translate.c | 13 -
3 files changed, 11 insertions(+), 6 deletions(-)
diff --g
Implement these out of line, so that tcg global temps
(aka the architectural registers) are synced back to
tcg storage as required. This makes sure that we get
the proper results when status.PRS == status.CRS.
Signed-off-by: Richard Henderson
---
target/nios2/cpu.h | 1 +
target/nios2/he
Add runtime supporting the nios2-semi.c interface.
Execute the hello and memory multiarch tests.
Cc: Alex Bennée
Signed-off-by: Richard Henderson
---
tests/tcg/nios2/semicall.h | 25 +++
tests/tcg/nios2/10m50-ghrd.ld | 59 +
tests/tcg/nios2/Makefile.so
Create an array of masks which detail the writable and readonly
bits for each control register. Apply them when writing to
control registers, including the write to status during eret.
Signed-off-by: Richard Henderson
---
target/nios2/cpu.h | 13 +
target/nios2/cpu.c | 100
This is the cpu side of the operation. Register one irq line,
called EIC. Split out the rather different processing to a
separate function.
Delay initialization of gpio irqs until realize. We need to
provide a window after init in which the board can set eic_present.
Signed-off-by: Richard Hen
The register is entirely read-only for software, and we do not
implement ECC, so we need not deposit the cause into an existing
value; just create a new value from scratch.
Furthermore, exception.CAUSE is not written for break exceptions.
Signed-off-by: Richard Henderson
---
target/nios2/helper
Split out do_exception and do_iic_irq to handle bulk of the interrupt and
exception processing. Parameterize the changes required to cpu state.
The status.EH bit, which protects some data against double-faults,
is only present with the MMU. Several exception cases did not check
for status.EH bei
Depending on the reason for ending the TB, we can chain
to the next TB because the PC is constant.
Signed-off-by: Richard Henderson
---
target/nios2/translate.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 51907
From: Amir Gonnen
Implement nios2 Vectored Interrupt Controller (VIC).
VIC is connected to EIC. It needs to update rha, ril, rrs and rnmi
fields on Nios2CPU before raising an IRQ.
For that purpose, VIC has a "cpu" property which should refer to the
nios2 cpu and set by the board that connects VIC
Rather than force all callers to set this, do it
within the subroutine.
Signed-off-by: Richard Henderson
---
target/nios2/translate.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index f61ba92052..51907586ab 100644
---
Do not actually enable them so far, but add all of the
plumbing to address them. Do not enable them for user-only.
Add an env->regs pointer that handles the indirection to
the current register set. The naming of the pointer hides
the difference between old and new, user-only and sysemu.
>From t
Use FIELD_DP32 instead of manual shifting and masking.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/nios2/cpu.h| 4
target/nios2/helper.c | 37 ++---
2 files changed, 26 insertions(+), 15 deletions(-)
diff --git a/target/nios2
Indirect branches, plus eret and bret optionally raise
an exception when branching to a misaligned address.
The exception is required when an mmu is enabled, but
enable it always because the fallback behaviour is not
documented (though presumably it discards low bits).
For the purposes of the linu
Do not print control registers for user-only mode.
Rename reserved control registers to "resN", where
N is the control register index.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/nios2/translate.c | 19 +--
1 file changed, 9 insertions(+), 10 deletions
Unaligned traps are optional, but required with an mmu.
Turn them on always, because the fallback behaviour is not
documented (though presumably it discards low bits).
Enable alignment checks in the config file.
Unwind the guest pc properly from do_unaligned_access.
Signed-off-by: Richard Henders
We missed out on a couple of exception types that may
legitimately be raised by a userland program.
Signed-off-by: Richard Henderson
---
linux-user/nios2/cpu_loop.c | 8
1 file changed, 8 insertions(+)
diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c
index 6722012
There's nothing about EH that affects translation,
so there's no need to include it in tb->flags.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/nios2/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index
Place the control registers into their own array, env->ctrl[].
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/nios2/cpu.h | 43
target/nios2/cpu.c | 19 +++
target/nios2/helper.c| 106 +++
target/
Split out a function to perform an indirect branch.
Signed-off-by: Richard Henderson
---
target/nios2/translate.c | 27 +--
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index d5f2e98de9..f61ba92052 100
Use lookup_and_goto_ptr for indirect chaining between TBs.
Signed-off-by: Richard Henderson
---
target/nios2/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 6f31b6cc50..f7bab0908b 100644
--- a/target/ni
Replace current uses of tcg_const_tl, and remove the frees.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/nios2/translate.c | 30 ++
1 file changed, 6 insertions(+), 24 deletions(-)
diff --git a/target/nios2/translate.c b/target/nios2/transl
We don't need to reference them often, and when we do it
is just as easy to load/store from cpu_env directly.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/nios2/translate.c | 33 ++---
1 file changed, 26 insertions(+), 7 deletions(-)
diff -
Constrain all references to cpu_R[] to load_gpr and dest_gpr.
This will be required for supporting shadow register sets.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/nios2/translate.c | 153 ++-
1 file changed, 55 insertions(+), 98 d
Division may (optionally) raise a division exception.
Since the linux kernel has been prepared for this for
some time, enable it by default.
Signed-off-by: Richard Henderson
---
target/nios2/cpu.h | 2 ++
target/nios2/helper.h | 2 ++
linux-user/nios2/cpu_loop.c | 4 +++
target
Without EIC, this bit is RES1. So set the bit at reset,
and add it to the readonly fields of CR_STATUS.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/nios2/cpu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/nios2/cpu.c b/target/nios2/
The 4 lower bits, D, PERM, BAD, DBL, are unconditionally set on any
exception with EH=0, or so says Table 42 (Processor Status After
Taking Exception).
We currently do not set PERM or BAD at all, and only set/clear
DBL for tlb miss, and do not clear DBL for any other exception.
It is a bit confus
Performing this early means that we can merge more cases
within the non-logging switch statement.
Signed-off-by: Richard Henderson
---
target/nios2/helper.c | 58 +++
1 file changed, 47 insertions(+), 11 deletions(-)
diff --git a/target/nios2/helper.c b/t
We had failed to copy BSTATUS back to STATUS, and diagnose
supervisor-only. The spec is light on the specifics of the
implementation of bret, but it is an easy assumption that
the restore into STATUS should work the same as eret.
Therefore, reuse the existing helper_eret.
Reviewed-by: Peter Mayd
This interrupt bit is never set, so testing it in
nios2_cpu_has_work is pointless.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/nios2/cpu.h | 2 --
target/nios2/cpu.c | 2 +-
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios
Decode 'break 1' during translation, rather than doing
it again during exception processing.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/nios2/cpu.h | 1 +
target/nios2/helper.c| 14 ++
target/nios2/translate.c | 17 -
3 files ch
It is cleaner to have a separate name for this variable.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/nios2/cpu.h | 10 +++-
linux-user/elfload.c| 2 +-
linux-user/nios2/cpu_loop.c | 17 ++---
linux-user/nios2/signal.c | 6 ++---
target
Use FIELD_EX32 and FIELD_DP32 instead of managing the
masking by hand.
Signed-off-by: Richard Henderson
---
target/nios2/cpu.h | 29 +++--
target/nios2/helper.c| 7 ++-
target/nios2/mmu.c | 35 +--
target/nios2/translat
Copy the existing cpu_index into the space reserved for CR_CPUID.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/nios2/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 8189937857..2f1f5e35aa 100644
--- a/target/n
These symbols become available to the debugger.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/nios2/cpu.h | 72 ++
1 file changed, 35 insertions(+), 37 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 7
From: Amir Gonnen
The implementation of eret will become much more complex
with the introduction of shadow registers.
Reviewed-by: Peter Maydell
Signed-off-by: Amir Gonnen
Message-Id: <20220303153906.2024748-3-amir.gon...@neuroblade.ai>
[rth: Split out of a larger patch for shadow register set
WE is the architectural name of the field, not WR.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/nios2/cpu.h| 2 +-
target/nios2/helper.c | 4 ++--
target/nios2/mmu.c| 4 ++--
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/nios2/cpu.h b/ta
Retain the helper macros for single bit fields as aliases to
the longer R_*_MASK names. Use FIELD_EX32 and FIELD_DP32
instead of manually manipulating the fields.
Since we're rewriting the references to CR_TLBACC_IGN_* anyway,
we correct the name of this field to IG, which is its name in
the offi
These misaligned data and misaligned destination exceptions
are defined, but not currently raised.
Signed-off-by: Richard Henderson
---
target/nios2/helper.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index 285f3aae1d..0392c0ea84 100
Whether the cpu is in user-mode or not is something that we
know at translation-time. We do not need to generate code
after having raised an exception.
Suggested-by: Peter Maydell
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/nios2/translate.c | 20 +++
Drop the set of estatus in init_thread; it was clearly intended
to be setting the value of CR_STATUS for the application, but we
never actually performed that copy. However, the proper value is
set in nios2_cpu_reset so we don't need to do anything here.
We only initialize SP and EA in init_threa
Use FIELD_EX32 and FIELD_DP32 instead of manual manipulation
of the fields.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/nios2/cpu.h | 8
target/nios2/helper.c| 4 ++--
target/nios2/mmu.c | 17 +
target/nios2/translate.c | 2
Add all fields; retain the helper macros for single bit fields.
So far there are no uses of the multi-bit status fields.
Signed-off-by: Richard Henderson
---
target/nios2/cpu.h | 28 +++-
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/target/nios2/cpu.h b/
From: Amir Gonnen
eret instruction is only allowed in supervisor mode.
Reviewed-by: Peter Maydell
Reviewed-by: Richard Henderson
Signed-off-by: Amir Gonnen
Message-Id: <20220303153906.2024748-2-amir.gon...@neuroblade.ai>
Signed-off-by: Richard Henderson
---
target/nios2/translate.c | 2 ++
This function is unused. The real computation of this value
is located in nios2_cpu_exec_interrupt.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/nios2/cpu.h | 5 -
1 file changed, 5 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 9be128d63
From: Amir Gonnen
Split NUM_CORE_REGS into components that can be used elsewhere.
Reviewed-by: Peter Maydell
Signed-off-by: Amir Gonnen
Message-Id: <20220303153906.2024748-3-amir.gon...@neuroblade.ai>
[rth: Split out of a larger patch for shadow register sets.]
Signed-off-by: Richard Henderson
With TCG_OPF_COND_BRANCH, we extended the lifetimes of
globals across extended basic blocks. This means that
the liveness computed in pass 1 does not kill globals
in the same way as normal temps.
Introduce TYPE_EBB to match this lifetime, so that we
get correct register allocation for the temps t
This has grown quite beyond merely implementing $SUBJECT,
which are only the last 8 patches of the set.
Version 6 fixes a tcg problem with indirect global lowering,
and adds a test harness and regression test.
Version 5 addresses all of the feedback from v4, fixes some
further bugs in the base ex
On 15.03.2022 17:41, Markus Armbruster wrote:
g_new(T, n) is neater than g_malloc(sizeof(T) * n). It's also safer,
for two reasons. One, it catches multiplication overflowing size_t.
Two, it returns T * rather than void *, which lets the compiler catch
more type errors.
This commit only touche
On Thu, Mar 17, 2022 at 12:10 PM Weiwei Li wrote:
>
>
> 在 2022/3/17 上午6:35, Alistair Francis 写道:
> > On Thu, Mar 17, 2022 at 1:13 AM Weiwei Li wrote:
> >>
> riscv_raise_exception(env, ret, GETPC());
> @@ -90,7 +90,7 @@ void helper_csrw_i128(CPURISCVState *env, int csr,
>
HI Michael:
Want to take this series?
Thanks
On Thu, Feb 10, 2022 at 5:28 PM Jason Wang wrote:
>
> This fault reason is not used and is duplicated with SPT.2 condition
> code. So let's remove it.
>
> Signed-off-by: Jason Wang
> ---
> hw/i386/intel_iommu.c | 6 --
> hw/i386/intel_
On Thu, Mar 17, 2022 at 1:58 AM Atish Patra wrote:
>
> The Linux kernel parses the ISA extensions from "riscv,isa" DT
> property. It used to parse only the single letter base extensions
> until now. A generic ISA extension parsing framework was proposed[1]
> recently that can parse multi-letter IS
On Wed, Mar 16, 2022 at 11:51 PM Stefan Hajnoczi wrote:
>
> On Wed, Mar 16, 2022 at 09:49:19PM +0800, Yongji Xie wrote:
> > On Wed, Mar 16, 2022 at 9:28 PM Stefan Hajnoczi wrote:
> > >
> > > On Tue, Mar 15, 2022 at 07:38:12PM +0800, Yongji Xie wrote:
> > > > On Tue, Mar 15, 2022 at 5:48 PM Stefan
在 2022/3/17 上午6:35, Alistair Francis 写道:
On Thu, Mar 17, 2022 at 1:13 AM Weiwei Li wrote:
riscv_raise_exception(env, ret, GETPC());
@@ -90,7 +90,7 @@ void helper_csrw_i128(CPURISCVState *env, int csr,
{
RISCVException ret = riscv_csrrw_i128(env, csr, NULL,
On Wed, 16 Mar 2022 21:29:51 +0100
Eric Auger wrote:
> The CRB command buffer currently is a RAM MemoryRegion and given
> its base address alignment, it causes an error report on
> vfio_listener_region_add(). This region could have been a RAM device
> region, easing the detection of such safe sit
On Wed, Mar 16, 2022 at 04:15:53PM -0500, Eric Blake wrote:
> On Wed, Mar 16, 2022 at 04:07:21PM -0500, Eric Blake wrote:
> > On Tue, Mar 15, 2022 at 01:14:41PM +, Richard W.M. Jones wrote:
> > > The patches seem OK to me, but I don't really know enough about the
> > > internals of qemu-nbd to
On Thu, Mar 17, 2022 at 1:13 AM Weiwei Li wrote:
>
>
> 在 2022/3/16 下午9:07, Bin Meng 写道:
> > On Fri, Mar 11, 2022 at 5:46 PM Weiwei Li wrote:
> >> For csrrs and csrrc, if rs1 specifies a register other than x0, holding
> >> a zero value, the instruction will still attempt to write the unmodified
>
On Tue, Mar 15, 2022 at 10:51 PM Ralf Ramsauer
wrote:
>
>
>
> On 15/03/2022 13:42, Peter Maydell wrote:
> > On Tue, 15 Mar 2022 at 12:29, Ralf Ramsauer
> > wrote:
> >> I have no kernel specified in the guest, so I'd then expect to boot into
> >> an completely empty machine (besides the tiny start
The patch introduces baseline implementation of a draft proposal
of RISC-V IOMMU specification as discussed in the RISC-V Forum [1] [2].
The implementation follows a draft version of the specification published
at [3] including all updates available on 2022/03/10.
This patch covers baseline featu
Enable rivos-iommu device support in riscv:virt machine emulation.
Signed-off-by: Tomasz Jeznach
---
hw/riscv/Kconfig| 1 +
hw/riscv/virt.c | 115 +++-
include/hw/riscv/virt.h | 2 +
3 files changed, 94 insertions(+), 24 deletions(-)
diff
This is the series of patches to introduce RISC-V IOMMU emulation in QEMU.
The Rivos IOMMU device implementation is based on a draft proposal of a
RISC-V I/O Management Unit (IOMMU) [1] as published on 2022/03/10, shared and
discussed with RISCV-V IOMMU Task Group [2].
Specification is in *draft*
On Tue, Mar 15, 2022 at 12:32:26AM +0300, Vladimir Sementsov-Ogievskiy wrote:
> From: Vladimir Sementsov-Ogievskiy
>
> Add simple test that new interface introduced in previous commit works.
>
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> ---
> tests/qemu-iotests/223 | 16 +
>
Am 09/03/2022 um 14:26 schrieb Emanuele Giuseppe Esposito:
>> Next, I have a problem in mind, that in past lead to a lot of iotest 30
>> failures. Next there were different fixes and improvements, but the core
>> problem (as far as I understand) is still here: nothing protects us when
>> we are
On Wed, Mar 16, 2022 at 12:27:02PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> Old vsement...@virtuozzo.com is not accessible anymore.
>
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> ---
>
> v2: @ya.ru mailbox works bad with mailing lists and git send-email
> command, @mail.ru works normally.
On Tue, Mar 15, 2022 at 12:32:25AM +0300, Vladimir Sementsov-Ogievskiy wrote:
> From: Vladimir Sementsov-Ogievskiy
>
> Hi all! Current logic of relying on search through backing chain is not
> safe neither convenient.
>
> Sometimes it leads to necessity of extra bitmap copying. Also, we are
> go
On Tue, Mar 15, 2022 at 12:32:24AM +0300, Vladimir Sementsov-Ogievskiy wrote:
> From: Vladimir Sementsov-Ogievskiy
>
> Rename the type to be reused. Old name is "what is it for". To be
> natively reused for other needs, let's name it exactly "what is it".
>
> Signed-off-by: Vladimir Sementsov-Og
On Wed, Mar 16, 2022 at 04:07:21PM -0500, Eric Blake wrote:
> On Tue, Mar 15, 2022 at 01:14:41PM +, Richard W.M. Jones wrote:
> > The patches seem OK to me, but I don't really know enough about the
> > internals of qemu-nbd to give a line-by-line review. I did however
> > build and test qemu-n
On Tue, Mar 15, 2022 at 01:14:41PM +, Richard W.M. Jones wrote:
> The patches seem OK to me, but I don't really know enough about the
> internals of qemu-nbd to give a line-by-line review. I did however
> build and test qemu-nbd with the patches:
>
> $ ./build/qemu-nbd /var/tmp/test.qcow2
On Wed, 16 Mar 2022 at 19:29, Peter Maydell wrote:
>
> On Wed, 16 Mar 2022 at 17:31, Paolo Bonzini wrote:
> >
> > On 3/16/22 17:22, Akihiko Odaki wrote:
> > > I was thinking that it may be better to let softmmu/main.c do the
> > > details if it involves the internals of qemu_main() like qemu_main
Power ISA v3.1 formalizes the previously undefined result in
words 1 and 3 to be a copy of the result in words 0 and 2.
This affects: xvcvsxdsp, xvcvuxdsp, xvcvdpsp.
And the previously undefined result in word 1 to be a copy of
the result in word 0.
This affects: xscvdpsp.
Signed-off-by: Lucas
The CRB command buffer currently is a RAM MemoryRegion and given
its base address alignment, it causes an error report on
vfio_listener_region_add(). This region could have been a RAM device
region, easing the detection of such safe situation but this option
was not well received. So let's add a he
On 3/16/22 13:04, Lucas Coutinho wrote:
Power ISA v3.1 formalizes the previously undefined result in
words 1 and 3 to be a copy of the result in words 0 and 2.
This affects: xvcvsxdsp, xvcvuxdsp, xvcvdpsp.
And the previously undefined result in word 1 to be a copy of
the result in word 0.
This
On Wed, Mar 16, 2022, 5:53 AM wrote:
> From: Marc-André Lureau
>
> Signed-off-by: Marc-André Lureau
> ---
> scripts/modinfo-collect.py | 5 -
> 1 file changed, 5 deletions(-)
>
> diff --git a/scripts/modinfo-collect.py b/scripts/modinfo-collect.py
> index 61b90688c6dc..4e7584df6676 100755
Hi
On Wed, Mar 16, 2022 at 5:28 PM Thomas Huth wrote:
>
> On 16/03/2022 14.16, Philippe Mathieu-Daudé wrote:
> > On 16/3/22 10:52, marcandre.lur...@redhat.com wrote:
> >> From: Marc-André Lureau
> >>
> >> One less qemu-specific macro. It also helps to make some headers/units
> >> only depend on
Christoph Muellner writes:
> QEMU plugins can be loaded via command line arguments or via
> the QEMU_PLUGIN environment variable. Currently, only the first method
> is documented. Let's document QEMU_PLUGIN.
>
> As drive-by cleanup, this patch fixes the path to the plugins
> in the same section
On Wed, 16 Mar 2022 at 17:31, Paolo Bonzini wrote:
>
> On 3/16/22 17:22, Akihiko Odaki wrote:
> > I was thinking that it may be better to let softmmu/main.c do the
> > details if it involves the internals of qemu_main() like qemu_main_loop().
> >
> > More concretely, softmmu/main.c would provide a
Timothy,
On 3/16/22 17:29, Cédric Le Goater wrote:
Hello,
I've been struggling for some time with what is looking like a
potential bug in QEMU/KVM on the POWER9 platform. It appears that
in XIVE mode, when the in-kernel IRQ chip is enabled, an external
device that rapidly asserts IRQs via th
On Wed, 16 Mar 2022 17:58:46 +
Jonathan Cameron wrote:
> On Wed, 16 Mar 2022 17:16:55 +
> Mark Cave-Ayland wrote:
>
> > On 16/03/2022 16:50, Jonathan Cameron via wrote:
> >
> > > On Thu, 10 Mar 2022 16:02:22 +0800
> > > Peter Xu wrote:
> > >
> > >> On Wed, Mar 09, 2022 at 11:28
On Mittwoch, 16. März 2022 12:10:43 CET Greg Kurz wrote:
> On Mon, 14 Mar 2022 19:58:11 +0100
>
> Christian Schoenebeck wrote:
> > The 'synth' driver's root node and the 'synth' driver's first
> > subdirectory node falsely share the same inode number (zero), which
> > makes it impossible for 9p c
On 16/03/22 6:55 pm, Markus Armbruster wrote:
Kshitij Suri writes:
From: "kshitij.suri"
Currently screendump only supports PPM format, which is un-compressed and not
standard. Added a "format" parameter to qemu monitor screendump capabilites
to support PNG image capture using libpng. The p
QEMU plugins can be loaded via command line arguments or via
the QEMU_PLUGIN environment variable. Currently, only the first method
is documented. Let's document QEMU_PLUGIN.
As drive-by cleanup, this patch fixes the path to the plugins
in the same section of the documentation.
Signed-off-by: Chr
On Wed, Mar 16, 2022 at 4:01 PM Alex Bennée wrote:
>
> Christoph Muellner writes:
>
> > QEMU plugins can be loaded via command line arguments or via
> > the QEMU_PLUGIN environment variable. Currently, only the first method
> > is documented. Let's document QEMU_PLUGIN.
> >
> > Signed-off-by: Ch
On 15/03/22 3:49 pm, Daniel P. Berrangé wrote:
On Tue, Mar 15, 2022 at 11:06:31AM +0100, Markus Armbruster wrote:
Kshitij Suri writes:
On 11/03/22 5:50 pm, Markus Armbruster wrote:
Kshitij Suri writes:
Currently screendump only supports PPM format, which is un-compressed and not
standar
On Wed, 16 Mar 2022 17:16:55 +
Mark Cave-Ayland wrote:
> On 16/03/2022 16:50, Jonathan Cameron via wrote:
>
> > On Thu, 10 Mar 2022 16:02:22 +0800
> > Peter Xu wrote:
> >
> >> On Wed, Mar 09, 2022 at 11:28:27AM +, Jonathan Cameron wrote:
> >>> Hi Peter,
> >>
> >> Hi, Jonathan,
>
The Linux kernel parses the ISA extensions from "riscv,isa" DT
property. It used to parse only the single letter base extensions
until now. A generic ISA extension parsing framework was proposed[1]
recently that can parse multi-letter ISA extensions as well.
Generate the extended ISA string by app
On Wed, Mar 16, 2022 at 05:48:04PM +, David Edmondson wrote:
> On Wednesday, 2022-03-16 at 16:05:01 GMT, Daniel P. Berrangé wrote:
>
> > On Wed, Mar 16, 2022 at 04:57:39PM +0100, Peter Krempa wrote:
> >> On Tue, Mar 08, 2022 at 12:34:38 +0100, Paolo Bonzini wrote:
> >> > From: Yang Zhong
> >>
On Wednesday, 2022-03-16 at 16:05:01 GMT, Daniel P. Berrangé wrote:
> On Wed, Mar 16, 2022 at 04:57:39PM +0100, Peter Krempa wrote:
>> On Tue, Mar 08, 2022 at 12:34:38 +0100, Paolo Bonzini wrote:
>> > From: Yang Zhong
>> >
>> > Kernel allocates 4K xstate buffer by default. For XSAVE features
>>
Cornelia Huck writes:
> On Wed, Mar 09 2022, Alex Bennée wrote:
>
>> While writing my own VirtIO devices I've gotten confused with how
>> things are structured and what sort of shared infrastructure there is.
>> If we can document how everything is supposed to work we can then
>> maybe start c
On 3/16/22 17:22, Akihiko Odaki wrote:
I was thinking that it may be better to let softmmu/main.c do the
details if it involves the internals of qemu_main() like qemu_main_loop().
More concretely, softmmu/main.c would provide a function to register a
function pointer to take over the main thre
On 3/16/22 17:05, Daniel P. Berrangé wrote:
On Wed, Mar 16, 2022 at 04:57:39PM +0100, Peter Krempa wrote:
On Tue, Mar 08, 2022 at 12:34:38 +0100, Paolo Bonzini wrote:
From: Yang Zhong
Kernel allocates 4K xstate buffer by default. For XSAVE features
which require large state component (e.g. AM
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