在 2022/2/16 15:42, Peter Xu 写道:
On Wed, Feb 16, 2022 at 12:13:31PM +0800, huang...@chinatelecom.cn wrote:
From: Hyman Huang(黄勇)
v15
- rebase on master
- drop the 'init_time_ms' parameter in function vcpu_calculate_dirtyrate
- drop the 'setup' field in dirtylimit_state and call dirtylimit_pr
Will be reused in postcopy fast load thread.
Signed-off-by: Peter Xu
---
migration/ram.c | 2 +-
migration/ram.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/migration/ram.c b/migration/ram.c
index 1ed70b17d7..f8bc3cd882 100644
--- a/migration/ram.c
+++ b/migration/ram.c
From: Anup Patel
The hgeie and hgeip CSRs are required for emulating an external
interrupt controller capable of injecting virtual external interrupt
to Guest/VM running at VS-level.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
Me
Per the title, remove the return code and simplify the callers as the errors
will never be triggered. No functional change intended.
Signed-off-by: Peter Xu
---
migration/postcopy-ram.c | 25 -
1 file changed, 4 insertions(+), 21 deletions(-)
diff --git a/migration/post
From: Anup Patel
The AIA specification introduces new [m|s|vs]topi CSRs for
reporting pending local IRQ number and associated IRQ priority.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Frank Chang
Message-id: 20220204174700.534953-14-a...@brainfault.org
[ Changed by AF:
-
From: Anup Patel
We should be returning illegal instruction trap when RV64 HS-mode tries
to access RV32 HS-mode CSR.
Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions")
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Bin M
Previously migration didn't have an easy way to cleanup the listening
transport, migrate recovery only allows to execute once. That's done with a
trick flag in postcopy_recover_triggered.
Now the facility is already there.
Drop postcopy_recover_triggered and instead allows a new migrate-recover
From: Philipp Tomsich
Signed-off-by: Philipp Tomsich
Reviewed-by: Alistair Francis
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Message-Id: <20220202005249.3566542-2-philipp.toms...@vrull.eu>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 78 +
This patch enables postcopy-preempt feature.
It contains two major changes to the migration logic:
(1) Postcopy requests are now sent via a different socket from precopy
background migration stream, so as to be isolated from very high page
request delays.
(2) For huge page enabled hosts:
Add a helper to cleanup the transport listener.
When do it, we should also null-ify the cleanup hook and the data, then it's
even safe to call it multiple times.
Move the socket_address_list cleanup altogether, because that's a mirror of the
listener channels and only for the purpose of query-mig
From: Petr Tesarik
The documentation for the generic loader says that "the maximum size of
the data is 8 bytes". However, attempts to set data-len=8 trigger the
following assertion failure:
../hw/core/generic-loader.c:59: generic_loader_reset: Assertion `s->data_len <
sizeof(s->data)' failed.
From: Anup Patel
A hypervisor can optionally take guest external interrupts using
SGEIP bit of hip and hie CSRs.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
Message-id: 20220204174700.534953-3-a...@brainfault.org
Signed-off-by: A
From: Wilfred Mallawa
This patch removes the left-over/unused `ibex_plic.h` file. Previously
used by opentitan, which now follows the RISC-V standard and uses the
SiFivePlicState.
Fixes: 434e7e021 ("hw/intc: Remove the Ibex PLIC")
Signed-off-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
Re
When pc_system_parse_ovmf_flash() parses the optional GUIDed table in
the end of the OVMF flash memory area, the table length field is checked
for sizes that are too small, but doesn't error on sizes that are too
big (bigger than the flash content itself).
Add a check for maximal size of the OVMF
From: LIU Zhiwei
The guest should be able to set the vill bit as part of vsetvl.
Currently we may set env->vill to 1 in the vsetvl helper, but there
is nowhere that we set it to 0, so once it transitions to 1 it's stuck
there until the system is reset.
Signed-off-by: LIU Zhiwei
Reviewed-by: Ri
We used to use postcopy_try_recover() to replace migration_incoming_setup() to
setup incoming channels. That's fine for the old world, but in the new world
there can be more than one channels that need setup. Better move the channel
setup out of it so that postcopy_try_recover() only handles the
From: Philipp Tomsich
To split up the decoder into multiple functions (both to support
vendor-specific opcodes in separate files and to simplify maintenance
of orthogonal extensions), this changes decode_op to iterate over a
table of decoders predicated on guard functions.
This commit only adds
From: Alistair Francis
The following changes since commit ad38520bdeb2b1e0b487db317f29119e94c1c88d:
Merge remote-tracking branch
'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2022-02-15
19:30:33 +)
are available in the Git repository at:
g...@github.com:alistair23/q
This boolean flag shows whether the current page during migration is triggered
by postcopy or not. Then in ram_save_host_page() and deeper stack we'll be
able to have a reference on the priority of this page.
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Peter Xu
---
migration/ram.c | 6 +
From: Philipp Tomsich
The Zb[abcs] support code still uses the RISCV_CPU macros to access
the configuration information (i.e., check whether an extension is
available/enabled). Now that we provide this information directly
from DisasContext, we can access this directly via the cfg_ptr field.
Si
From: Philipp Tomsich
As the number of extensions is growing, copying them individiually
into the DisasContext will scale less and less... instead we populate
a pointer to the RISCVCPUConfig structure in the DisasContext.
This adds an extra indirection when checking for the availability of
an ex
From: Weiwei Li
- sinval.vma, hinval.vvma and hinval.gvma do the same as sfence.vma,
hfence.vvma and hfence.gvma except extension check
- do nothing other than extension check for sfence.w.inval and sfence.inval.ir
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Anup Patel
From: Weiwei Li
For non-leaf PTEs, the D, A, and U bits are reserved for future standard use.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Anup Patel
Reviewed-by: Alistair Francis
Message-Id: <20220204022658.18097-3-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
We used to have quite a few places making sure -EIO happened and that's the
only way to trigger postcopy recovery. That's based on the assumption that
we'll only return -EIO for channel issues.
It'll work in 99.99% cases but logically that won't cover some corner cases.
One example is e.g. ram_bl
Static variable is very unfriendly to threading of ram_block_from_stream().
Move it into MigrationIncomingState.
Make the incoming state pointer to be passed over to ram_block_from_stream() on
both caller sites.
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Peter Xu
---
migration/migratio
From: Frédéric Pétrot
The addition of uxl support in gdbstub adds a few checks on the maximum
register length, but omitted MXL_RV128, an experimental feature.
This patch makes rv128 react as rv64, as previously.
Signed-off-by: Frédéric Pétrot
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: LI
Postcopy create threads. A common manner is we init a sem and use it to sync
with the thread. Namely, we have fault_thread_sem and listen_thread_sem and
they're only used for this.
Make it a shared infrastructure so it's easier to create yet another thread.
Signed-off-by: Peter Xu
---
migratio
From: Anup Patel
The AIA specificaiton adds interrupt filtering support for M-mode
and HS-mode. Using AIA interrupt filtering M-mode and H-mode can
take local interrupt 13 or above and selectively inject same local
interrupt to lower privilege modes.
At the moment, we don't have any local interr
This variable, along with its helpers, is used to detect whether multiple
channel will be supported for migration. In follow up patches, there'll be
other capability that requires multi-channels. Hence move it outside multifd
specific code and make it public. Meanwhile rename it from "multifd" t
On Tue, Feb 15, 2022 at 9:39 PM Peter Maydell wrote:
>
> On Sat, 12 Feb 2022 at 00:07, Alistair Francis
> wrote:
> >
> > From: Alistair Francis
> >
> > The following changes since commit 0a301624c2f4ced3331ffd5bce85b4274fe132af:
> >
> > Merge remote-tracking branch
> > 'remotes/pmaydell/tags/
In ram_load_postcopy() we'll try to detect non-same-page case and dump error.
This error is very helpful for debugging. Adding ramblock & offset into the
error log too.
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Peter Xu
---
migration/ram.c | 8 ++--
1 file changed, 6 insertions(+)
From: Anup Patel
The AIA hvictl and hviprioX CSRs allow hypervisor to control
interrupts visible at VS-level. This patch implements AIA hvictl
and hviprioX CSRs.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
Message-id: 20220204174
Remove the old two tracepoints and they're even near each other:
trace_loadvm_postcopy_handle_run_cpu_sync()
trace_loadvm_postcopy_handle_run_vmstart()
Add trace_loadvm_postcopy_handle_run_bh() with a finer granule trace.
Signed-off-by: Peter Xu
---
migration/savevm.c | 12
Postcopy handles huge pages in a special way that currently we can only have
one "channel" to transfer the page.
It's because when we install pages using UFFDIO_COPY, we need to have the whole
huge page ready, it also means we need to have a temp huge page when trying to
receive the whole content
From: Philipp Tomsich
The implementation in trans_{rvi,rvv,rvzfh}.c.inc accesses the shallow
copies (in DisasContext) of some of the elements available in the
RISCVCPUConfig structure. This commit redirects accesses to use the
cfg_ptr copied into DisasContext and removes the shallow copies.
Sig
The enablement of postcopy listening has a few steps, add a few tracepoints to
be there ready for some basic measurements for them.
Signed-off-by: Peter Xu
---
migration/savevm.c | 9 -
migration/trace-events | 2 +-
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/migr
It'll be easier to read the name rather than index of sub-cmd when debugging.
Signed-off-by: Peter Xu
---
migration/savevm.c | 3 ++-
migration/trace-events | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/migration/savevm.c b/migration/savevm.c
index 1599b02fbc..7bb65e
This is v1 of postcopy preempt series. It can also be found here:
https://github.com/xzpeter/qemu/tree/postcopy-preempt
This series added a new migration capability called "postcopy-preempt". It can
be enabled when postcopy is enabled, and it'll simply (but greatly) speed up
postcopy page req
From: Wilfred Mallawa
This patch updates the SPI_DEVICE, SPI_HOST0, SPI_HOST1
base addresses. Also adds these as unimplemented devices.
The address references can be found [1].
[1]
https://github.com/lowRISC/opentitan/blob/6c317992fbd646818b34f2a2dbf44bc850e461e4/hw/top_earlgrey/sw/autogen/top
On 15/02/22 3:00 pm, Markus Armbruster wrote:
Rohit Kumar writes:
Qemu might crash when provided incomplete '-global' option.
For example:
qemu-system-x86_64 -global driver=isa-fdc
qemu-system-x86_64: ../../devel/qemu/qapi/string-input-visitor.c:394:
string_input_v
On Tue, Feb 15, 2022 at 06:41:48PM -0300, Fabiano Rosas wrote:
> Let's leave cpu_init with just generic CPU initialization and
> QOM-related functions.
>
> The rest of the SPR registration functions will be moved in the
> following patches along with the code that uses them. These are only
> the c
>On Wed, Feb 16, 2022 at 11:46:58AM +1000, Nicholas Piggin wrote:
> Excerpts from Fabiano Rosas's message of February 15, 2022 10:21 pm:
> > Nicholas Piggin writes:
> >
> >> Excerpts from Fabiano Rosas's message of February 14, 2022 11:13 pm:
> >>> Nicholas Piggin writes:
> >>>
> Use KVM_C
On Tue, Feb 15, 2022 at 06:41:43PM -0300, Fabiano Rosas wrote:
> The important part of this function is that it applies to non-embedded
> CPUs, not that it also applies to the 601. We removed support for the
> 601 anyway, so rename this function.
>
> Signed-off-by: Fabiano Rosas
Reviewed-by: Dav
On Tue, Feb 15, 2022 at 06:41:45PM -0300, Fabiano Rosas wrote:
> The following patches will move CPU-specific code into separate files,
> so expose the most used SPR registration functions:
>
> register_sdr1_sprs | 22 callers
> register_low_BATs | 20 callers
> register_non_embedde
On Wed, Feb 16, 2022 at 01:24:55PM +1100, David Gibson wrote:
> On Tue, Feb 15, 2022 at 06:41:36PM -0300, Fabiano Rosas wrote:
> > Signed-off-by: Fabiano Rosas
>
> There's only one caller of the new function, and no commit message, so
> the rationale for splitting these out isn't obvious.
Ok, sa
On Wed, Feb 16, 2022 at 11:50:34AM +1000, Nicholas Piggin wrote:
> Excerpts from David Gibson's message of February 15, 2022 11:10 am:
> > On Mon, Feb 14, 2022 at 09:17:48PM +1000, Nicholas Piggin wrote:
> >> diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
> >> index 222c1b6bbd..5dec056796
On Tue, Feb 15, 2022 at 06:41:36PM -0300, Fabiano Rosas wrote:
> Signed-off-by: Fabiano Rosas
There's only one caller of the new function, and no commit message, so
the rationale for splitting these out isn't obvious.
> ---
> target/ppc/cpu_init.c | 24 +++-
> 1 file changed
On Tue, Feb 15, 2022 at 06:41:33PM -0300, Fabiano Rosas wrote:
> Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
> ---
> target/ppc/cpu_init.c | 17 +++--
> 1 file changed, 7 insertions(+), 10 deletions(-)
>
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> ind
On Tue, Feb 15, 2022 at 06:41:35PM -0300, Fabiano Rosas wrote:
> The 745 and 755 can share the HID registration, so move it all into
> register_755_sprs, which applies for both CPUs.
>
> Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
> ---
> target/ppc/cpu_init.c | 44
On Tue, Feb 15, 2022 at 06:41:31PM -0300, Fabiano Rosas wrote:
> Move some of the 440 registers that are being repeated in the 440*
> CPUs to register_440_sprs.
>
> Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
> ---
> target/ppc/cpu_init.c | 100 +++--
On Tue, Feb 15, 2022 at 06:41:46PM -0300, Fabiano Rosas wrote:
> Put the SPR registration macros in a header that is accessible outside
> of cpu_init.c. The following patches will move CPU-specific code to
> separate files and will need to access it.
>
> Signed-off-by: Fabiano Rosas
Reviewed-by:
On Tue, Feb 15, 2022 at 06:41:47PM -0300, Fabiano Rosas wrote:
> These will need to be accessed from other files once we move the CPUs
> code to separate files.
>
> Signed-off-by: Fabiano Rosas
> ---
> target/ppc/cpu.h | 57 +++
> target/ppc/cpu_init.
On Tue, Feb 15, 2022 at 06:41:30PM -0300, Fabiano Rosas wrote:
> We're considering these two to be from different CPU families, so
> duplicate some code to keep them separate.
>
> Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
> ---
> target/ppc/cpu_init.c | 107 ++
On Tue, Feb 15, 2022 at 06:41:21PM -0300, Fabiano Rosas wrote:
> The goal of this series is to do some untangling of SPR registration
> code in cpu_init.c and prepare for moving the CPU initialization into
> separate files for each CPU family.
>
> The first 23 patches are all simple cleanups:
> -
On Tue, Feb 15, 2022 at 06:41:38PM -0300, Fabiano Rosas wrote:
> Signed-off-by: Fabiano Rosas
Now that I've looked at 19/27
Reviewed-by: David Gibson
> ---
> target/ppc/cpu_init.c | 43 ---
> 1 file changed, 24 insertions(+), 19 deletions(-)
>
> diff -
On Tue, Feb 15, 2022 at 06:41:44PM -0300, Fabiano Rosas wrote:
> This function registers just one SPR and has only two callers, so open
> code it.
>
> Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
> ---
> target/ppc/cpu_init.c | 21 +++--
> 1 file changed, 11 insertio
On Tue, Feb 15, 2022 at 06:41:29PM -0300, Fabiano Rosas wrote:
> We're considering these two to be in different CPU families (6xx and
> 7xx), so keep their SPR registration separate.
>
> The code was copied into register_G2_sprs and the common function was
> renamed to apply only to the 755.
>
>
On Tue, Feb 15, 2022 at 06:41:27PM -0300, Fabiano Rosas wrote:
> Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
> ---
> target/ppc/cpu_init.c | 24 +---
> 1 file changed, 13 insertions(+), 11 deletions(-)
>
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init
On Tue, Feb 15, 2022 at 06:41:41PM -0300, Fabiano Rosas wrote:
> The init_proc_755 function is identical to the 745 one except for the
> L2 cache registers. I think it is worth it to make them share code.
>
> Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
With one nit to consider as a
On Tue, Feb 15, 2022 at 06:41:42PM -0300, Fabiano Rosas wrote:
> With the removal of the 7450 software TLB code, the only software TLBs
> that we support currently are the 6xx and 7xx, so there's no need for
> this function to indicate that in its name anymore.
I don't think this is a good idea.
On Tue, Feb 15, 2022 at 06:41:39PM -0300, Fabiano Rosas wrote:
> init_proc_603 is defined after init_proc_e300, so I had to move some
> code around to make it work.
>
> Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
> ---
> target/ppc/cpu_init.c | 104 +++--
On Tue, Feb 15, 2022 at 06:41:24PM -0300, Fabiano Rosas wrote:
> The top level init_proc calls register_generic_sprs but also registers
> some other SPRs outside of that function. Let's group everything into
> a single place.
>
> Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
Of course
On Tue, Feb 15, 2022 at 06:41:40PM -0300, Fabiano Rosas wrote:
> Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
> ---
> target/ppc/cpu_init.c | 12 +---
> 1 file changed, 1 insertion(+), 11 deletions(-)
>
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index 8fb
On Tue, Feb 15, 2022 at 06:41:37PM -0300, Fabiano Rosas wrote:
> Signed-off-by: Fabiano Rosas
Rationale for this only becomes clear at patch 18/27, a commit message
would have helped.
Reviewed-by: David Gibson
> ---
> target/ppc/cpu_init.c | 64 +++
> 1
On Tue, Feb 15, 2022 at 06:41:22PM -0300, Fabiano Rosas wrote:
65;6602;1c> The /* XXX : not implemented */ comments all over cpu_init are
> confusing and ambiguous.
>
> Do they mean not implemented by QEMU, not implemented in a specific
> access mode? Not implemented by the CPU? Do they apply to j
On Tue, Feb 15, 2022 at 06:41:32PM -0300, Fabiano Rosas wrote:
> Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
> ---
> target/ppc/cpu_init.c | 28 +---
> 1 file changed, 9 insertions(+), 19 deletions(-)
>
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_i
On Tue, Feb 15, 2022 at 06:41:28PM -0300, Fabiano Rosas wrote:
> Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
> ---
> target/ppc/cpu_init.c | 41 ++---
> 1 file changed, 22 insertions(+), 19 deletions(-)
>
> diff --git a/target/ppc/cpu_init.c b/ta
On Tue, Feb 15, 2022 at 06:41:34PM -0300, Fabiano Rosas wrote:
> Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
One nit: this doesn't cover 745 and 755, since they're handled by the
next patch - a note of that would have been useful.
That said, it only stands out because in general thi
On Tue, Feb 15, 2022 at 06:41:23PM -0300, Fabiano Rosas wrote:
> The G2LE CPU initialization code is the same as the G2. Use the latter
> for both.
>
> Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
> ---
> target/ppc/cpu_init.c | 42 +-
> 1 fil
On Tue, Feb 15, 2022 at 06:41:26PM -0300, Fabiano Rosas wrote:
> Make sure that every register_*_sprs function only has calls to
> spr_register* to register individual SPRs. Do not allow nesting. This
> makes the code easier to follow and a look at init_proc_* should
> suffice to know what SPRs a C
The float??_minnum implementation differs from Hexagon for SNaN,
it returns NaN, but Hexagon returns the other input. So, we use
float??_minimum_number. For double precision, we check for QNaN and
raise the invalid flag.
test cases added in a subsequent patch to more extensively test USR bits
S
On Tue, Feb 15, 2022 at 06:41:25PM -0300, Fabiano Rosas wrote:
> Now that the 601 was removed, all of our CPUs have a timebase, so that
> can be moved into the common function.
>
> Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
> ---
> target/ppc/cpu_init.c | 98 --
From: Hyman Huang(黄勇)
Implement dirtyrate calculation periodically basing on
dirty-ring and throttle virtual CPU until it reachs the quota
dirty page rate given by user.
Introduce qmp commands "set-vcpu-dirty-limit",
"cancel-vcpu-dirty-limit", "query-vcpu-dirty-limit"
to enable, disable, query d
From: Hyman Huang(黄勇)
Introduce the third method GLOBAL_DIRTY_LIMIT of dirty
tracking for calculate dirtyrate periodly for dirty page
rate limit.
Add dirtylimit.c to implement dirtyrate calculation periodly,
which will be used for dirty page rate limit.
Add dirtylimit.h to export util functions
From: Hyman Huang(黄勇)
Setup a negative feedback system when vCPU thread
handling KVM_EXIT_DIRTY_RING_FULL exit by introducing
throttle_us_per_full field in struct CPUState. Sleep
throttle_us_per_full microseconds to throttle vCPU
if dirtylimit is in service.
Signed-off-by: Hyman Huang(黄勇)
---
From: Hyman Huang(黄勇)
v15
- rebase on master
- drop the 'init_time_ms' parameter in function vcpu_calculate_dirtyrate
- drop the 'setup' field in dirtylimit_state and call dirtylimit_process
directly, which makes code cleaner.
- code clean in dirtylimit_adjust_throttle
- fix miss dirtylimit_st
From: Hyman Huang(黄勇)
Introduce kvm_dirty_ring_size util function to help calculate
dirty ring ful time.
Signed-off-by: Hyman Huang(黄勇)
---
accel/kvm/kvm-all.c| 5 +
accel/stubs/kvm-stub.c | 5 +
include/sysemu/kvm.h | 2 ++
3 files changed, 12 insertions(+)
diff --git a/accel/k
From: Hyman Huang(黄勇)
Introduce cpu_list_generation_id to track cpu list generation so
that cpu hotplug/unplug can be detected during measurement of
dirty page rate.
cpu_list_generation_id could be used to detect changes of cpu
list, which is prepared for dirty page rate measurement.
Signed-off
From: Hyman Huang(黄勇)
abstract out dirty log change logic into function
global_dirty_log_change.
abstract out dirty page rate calculation logic via
dirty-ring into function vcpu_calculate_dirtyrate.
abstract out mathematical dirty page rate calculation
into do_calculate_dirtyrate, decouple it f
From: Hyman Huang(黄勇)
Add a non-required argument 'CPUState' to kvm_dirty_ring_reap so
that it can cover single vcpu dirty-ring-reaping scenario.
Signed-off-by: Hyman Huang(黄勇)
---
accel/kvm/kvm-all.c | 23 +--
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a
Hi postmas...@amsat.org,
Apparently your system is rejected by Gmail. Could you fix the problem?
Thanks,
Akihiko Odaki
-- Forwarded message -
From: Mail Delivery System
Date: Wed, Feb 16, 2022 at 11:29 AM
Subject: Undelivered Mail Returned to Sender
To:
This is the mail syste
On Wed, Feb 16, 2022 at 5:39 AM Atish Patra wrote:
>
> The Linux kernel parses the ISA extensions from "riscv,isa" DT
> property. It used to parse only the single letter base extensions
> until now. A generic ISA extension parsing framework was proposed[1]
> recently that can parse multi-letter IS
On Wed, Feb 16, 2022 at 3:57 AM Peter Maydell wrote:
>
> There are no longer any VMStateDescription structs in the tree which
> use the load_state_old support for custom handling of incoming
> migration from very old QEMU. Remove the mechanism entirely.
>
> This includes removing one stray useles
On Wed, Feb 16, 2022 at 2:01 AM Philippe Mathieu-Daudé wrote:
>
> GCC 10.1 introduced the -moutline-atomics option on Aarch64.
> This options is enabled by default, and triggers a link failure:
>
> Undefined symbols for architecture arm64:
> "___aarch64_cas1_acq_rel", referenced from:
>
On Wed, Feb 16, 2022 at 2:01 AM Philippe Mathieu-Daudé wrote:
>
> When building with GCC on macOS Catalina we get 2254 times:
>
> include/qemu/osdep.h:780:5: warning: 'pthread_jit_write_protect_np' is only
> available on macOS 11.0 or newer [-Wunguarded-availability-new]
> pthread_jit_wri
On Tue, Feb 15, 2022 at 10:25 PM Philippe Mathieu-Daudé wrote:
>
> On 15/2/22 14:06, Akihiko Odaki wrote:
> > On Tue, Feb 15, 2022 at 9:06 PM Philippe Mathieu-Daudé
> > wrote:
> >>
> >> Few fixes to be able to use GCC extensions which are not
> >> available on Clang.
> >>
> >> Philippe Mathieu-D
> On Feb 15, 2022, at 6:50 AM, Thanos Makatos
> wrote:
>
>>>
>
> On second thought, should we dump the entire header in case of such errors?
> If not by default then at least in debug builds?
I was thinking of adding qemu tracepoints in the recv and send paths
for your other debug
Excerpts from David Gibson's message of February 15, 2022 11:10 am:
> On Mon, Feb 14, 2022 at 09:17:48PM +1000, Nicholas Piggin wrote:
>> diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
>> index 222c1b6bbd..5dec056796 100644
>> --- a/hw/ppc/spapr_hcall.c
>> +++ b/hw/ppc/spapr_hcall.c
>> @@
Excerpts from Fabiano Rosas's message of February 15, 2022 10:21 pm:
> Nicholas Piggin writes:
>
>> Excerpts from Fabiano Rosas's message of February 14, 2022 11:13 pm:
>>> Nicholas Piggin writes:
>>>
Use KVM_CAP_PPC_AIL_MODE_3 to determine cap-ail-mode-3 support for KVM
guests. Keep
resolves: https://gitlab.com/qemu-project/qemu/-/issues/737
implements:
AND WITH COMPLEMENT (NCRK, NCGRK)
NAND (NNRK, NNGRK)
NOT EXCLUSIVE OR (NXRK, NXGRK)
NOR (NORK, NOGRK)
OR WITH COMPLEMENT(OCRK, OCGRK)
SELECT(SELR, SELGR)
SELECT HIG
tests/tcg/s390x/mie3-compl.c: [N]*K instructions
tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction
tests/tcg/s390x/mie3-sel.c: SELECT instruction
Signed-off-by: David Miller
---
tests/tcg/s390x/Makefile.target | 2 +-
tests/tcg/s390x/mie3-compl.c| 56 +
tests
Add partial support for s390x z15 ga1 and specific tests for minste3
v2 -> v3:
* Moved tests to separate patch.
* Combined patches into series.
David Miller (3):
s390x/tcg: Implement Miscellaneous-Instruction-Extensions Facility 3
for the s390x
s390x/cpumodel: Bump up QEMU model to a str
TCG implements everything we need to run basic z15 OS+software.
Signed-off-by: David Miller
---
hw/s390x/s390-virtio-ccw.c | 3 +++
target/s390x/cpu_models.c | 6 +++---
target/s390x/gen-features.c | 7 +--
3 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/hw/s390x/s390-vir
Excerpts from Cédric Le Goater's message of February 16, 2022 4:21 am:
> On 2/15/22 04:16, Nicholas Piggin wrote:
>> This implements the Nested KVM HV hcall API for spapr under TCG.
>>
>> The L2 is switched in when the H_ENTER_NESTED hcall is made, and the
>> L1 is switched back in returned from t
Excerpts from BALATON Zoltan's message of February 16, 2022 5:19 am:
> On Tue, 15 Feb 2022, Cédric Le Goater wrote:
>> On 2/15/22 04:16, Nicholas Piggin wrote:
>>> Introduce virtual hypervisor methods that can support a "Nested KVM HV"
>>> implementation using the bare metal 2-level radix MMU, and
Excerpts from Cédric Le Goater's message of February 16, 2022 4:36 am:
> On 2/15/22 04:16, Nicholas Piggin wrote:
>> Machines which don't emulate the HDEC facility are able to use the
>> timer for something else. Provide functions to start and stop the
>> hdecr timer.
>>
>> Signed-off-by: Nicholas
The Linux kernel parses the ISA extensions from "riscv,isa" DT
property. It used to parse only the single letter base extensions
until now. A generic ISA extension parsing framework was proposed[1]
recently that can parse multi-letter ISA extensions as well.
Generate the extended ISA string by app
On Tue, Feb 15, 2022 at 6:09 PM Eric Blake wrote:
>
> On Tue, Feb 15, 2022 at 05:08:53PM -0500, John Snow wrote:
> > re-configure qemu_img() into a function that will by default raise a
> > VerboseProcessException (extended from CalledProcessException) on
> > non-zero return codes. This will produ
On 16/2/22 00:53, John Snow wrote:
On Tue, Feb 15, 2022 at 5:55 PM Eric Blake wrote:
On Tue, Feb 15, 2022 at 05:08:50PM -0500, John Snow wrote:
print(enboxify(msg, width=72, name="commit message"))
┏━ commit message ━┓
┃ enboxify() takes a
On Tue, Feb 15, 2022 at 6:05 PM Eric Blake wrote:
>
> On Tue, Feb 15, 2022 at 05:08:52PM -0500, John Snow wrote:
> > qemu_img() returning zero ought to be the rule, not the
> > exception. Remove all explicit checks against the condition in
> > preparation for making non-zero returns an Exception.
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