This implements the nested-hv hcall API for spapr under TCG.
It's still a bit rough around the edges, concept seems to work.
Some HV exceptions can be raised now in the TCG spapr machine when
running a nested guest. The main ones are the lev==1 syscall, the
hdecr, hdsi and hisi, and h_virt externa
On Thu, Feb 10, 2022 at 12:16:34AM +0100, BB wrote:
> Am 30. Januar 2022 23:53:42 MEZ schrieb "Philippe Mathieu-Daudé"
> :
> >On 14/1/22 14:36, Peter Maydell wrote:
> >> On Wed, 12 Jan 2022 at 22:02, Bernhard Beschow wrote:
> >>>
> >>> Now that piix4_set_irq's opaque parameter references own PIIX
Here's a little thing I've been hacking on. I was pretty amazed I
could even get it working, let alone being so small and not too
horrible to look at. A few people thought it would be useful for
prototyping and hacking and running kvm tests, etc. So, thoughts
on the overall idea and code structure?
These are an HV exception. Not 100% sure what HDSISR bits to set in case of
an empty table -- not sure what hardware does.
not-yet-Signed-off-by: Nicholas Piggin
---
target/ppc/mmu-radix64.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/mmu-radix64.c b/target
The spapr virtual hypervisor does not require the hdecr timer.
Remove it.
not-yet-Signed-off-by: Nicholas Piggin
---
hw/ppc/ppc.c| 2 +-
hw/ppc/spapr_cpu_core.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index 462c87dba8..a7
This series adds device tree support for the OpenRISC SIM hardware.
The simulator will generate an FDT and pass it to the kernel.
For example:
qemu-system-or1k -cpu or1200 -M or1k-sim \
-kernel /home/shorne/work/linux/vmlinux \
-initrd /home/shorne/work/linux/initramfs.cpio.gz \
-se
This will allow us to attach machine state attributes like
the device tree fdt.
Signed-off-by: Stafford Horne
---
hw/openrisc/openrisc_sim.c | 31 +--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.
Move magic numbers to variables and enums. These will be
reused for upcoming fdt initialization.
Signed-off-by: Stafford Horne
---
hw/openrisc/openrisc_sim.c | 42 ++
1 file changed, 34 insertions(+), 8 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/h
Using the device tree means that qemu can now directly tell
the kernel what hardware is configured rather than use having
to maintain and update a separate device tree file.
This patch adds device tree support for the OpenRISC simulator.
A device tree is built up based on the state of the configur
The loaded initrd is loaded into memory. It's location and size is then
added to the device tree so the kernel knows where to find it.
Signed-off-by: Stafford Horne
---
hw/openrisc/openrisc_sim.c | 32 +++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git
From: Frank Chang
RISC-V privilege spec defines that:
* In RV32, memory-mapped writes to mtimecmp modify only one 32-bit part
of the register.
* For RV64, naturally aligned 64-bit memory accesses to the mtime and
mtimecmp registers are additionally supported and are atomic.
It's possible to
From: Frank Chang
This patchset makes ACLINT mtime to be writable as RISC-V privilege
spec defines that mtime is exposed as a memory-mapped machine-mode
read-write register. Also, mtimecmp and mtime should be 32/64-bit memory
accessible registers.
This patchset is the updated verion of:
https://
From: Frank Chang
If device's MemoryRegion doesn't have .impl.[min|max]_access_size
declaration, the default access_size_min would be 1 byte and
access_size_max would be 4 bytes (see: softmmu/memory.c).
This will cause a 64-bit memory access to ACLINT to be splitted into
two 32-bit memory accesse
From: Frank Chang
RISC-V privilege spec defines that mtime is exposed as a memory-mapped
machine-mode read-write register. However, as QEMU uses host monotonic
timer as timer source, this makes mtime to be read-only in RISC-V
ACLINT.
This patch makes mtime to be writable by recording the time de
Hi Joel,
On Tue, Feb 8, 2022 at 6:46 PM Joel Stanley wrote:
>
> Hello Troy,
>
> On Wed, 12 Jan 2022 at 08:10, Troy Lee wrote:
> >
> > Accumulative mode will supply a initial state and append padding bit at
> > the end of hash stream. However, the crypto library will padding those
> > bit automa
On 11-01-22, 20:28, Viresh Kumar wrote:
> VIRTIO_I2C_F_ZERO_LENGTH_REQUEST is a mandatory feature, that must be
> implemented by everyone. Add its support.
>
> Signed-off-by: Viresh Kumar
> ---
> hw/virtio/vhost-user-i2c.c | 10 --
> include/hw/virtio/vhost-user-i2c.h | 3 +++
>
On Tue, Feb 08, 2022 at 04:48:36PM -0300, Daniel Henrique Barboza wrote:
> Fix indentation of powerpc_set_excp_state() and ppc_excp_apply_ail()
> parameters.
>
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: David Gibson
> ---
> target/ppc/excp_helper.c | 8
> 1 file changed, 4
For FEAT_LPA2, we will need other ARMVAParameters, which themselves
depend on the translation granule in use. We might as well validate
that the given TG matches; the architecture "does not require that
the instruction invalidates any entries" if this is not true.
Signed-off-by: Richard Henderson
This feature widens physical addresses (and intermediate physical
addresses for 2-stage translation) from 48 to 52 bits, when using
4k or 16k pages.
This introduces the DS bit to TCR_ELx, which is RES0 unless the
page size is enabled and supports LPA2, resulting in the effective
value of DS for a
With FEAT_LPA2, rather than introducing translation level 4,
we introduce level -1, below the current level 0. Extend
arm_fi_to_lfsc to handle these faults.
Assert that this new translation level does not leak into
faults types for which it is not defined, which allows some
masking of fi->level t
The macro is a bit more readable than the inlined computation.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index cf38ebd816..94304804cb 100644
--- a/target/arm/helper.c
This feature widens physical addresses (and intermediate physical
addresses for 2-stage translation) from 48 to 52 bits, when using
64k pages. The only thing left at this point is to handle the
extra bits in the TTBR and in the table descriptors.
Note that PAR_EL1 and HPFAR_EL2 are nominally exte
This field controls the output (intermediate) physical address size
of the translation process. V8 requires to raise an AddressSize
fault if the page tables are programmed incorrectly, such that any
intermediate descriptor address, or the final translated address,
is out of range.
Add a PS field
This feature is relatively small, as it applies only to
64k pages and thus requires no additional changes to the
table descriptor walking algorithm, only a change to the
minimum TSZ (which is the inverse of the maximum virtual
address space size).
Note that this feature widens VBAR_ELx, but we alr
The original A.a revision of the AArch64 ARM required that we
force-extend the addresses in these registers from 49 bits.
This language has been loosened via a combination of IMPLEMENTATION
DEFINED and CONSTRAINTED UNPREDICTABLE to allow consideration of
the entire aligned address.
This means that
The shift of the BaseADDR field depends on the translation
granule in use.
Fixes: 84940ed8255 ("target/arm: Add support for FEAT_TLBIRANGE")
Reported-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
Pass down the width of the output address from translation.
For now this is still just PAMax, but a subsequent patch will
compute the correct value from TCR_ELx.{I}PS.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 21 ++---
1 file changed, 10 insertions(+), 11 deleti
Without FEAT_LVA, the behaviour of programming an invalid value
is IMPLEMENTATION DEFINED. With FEAT_LVA, programming an invalid
minimum value requires a Translation fault.
It is most self-consistent to choose to generate the fault always.
Signed-off-by: Richard Henderson
---
v2: Continue to bo
Merge tlbi_aa64_range_get_length and tlbi_aa64_range_get_base,
returning a structure containing both results. Pass in the
ARMMMUIdx, rather than the digested two_ranges boolean.
This is in preparation for FEAT_LPA2, where the interpretation
of 'value' depends on the effective value of DS for the
We will shortly share parts of this function with other portions
of address translation.
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 19 +--
target/arm/helper.c| 22 ++
2 file
Set this as the kernel would, to 48 bits, to keep the computation
of the address space correct for PAuth.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 5a9c02a256..92f19f919a 1
Changes for v2:
* Introduce FIELD_SEX64, instead of open-coding w/ sextract64.
* Set TCR_EL1 more completely for user-only.
* Continue to bound tsz within aa64_va_parameters;
provide an out-of-bound indicator for raising AddressSize fault.
* Split IPS patch.
* Fix debug registers for
Add new macros to manipulate signed fields within the register.
Suggested-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/hw/registerfields.h | 48 -
1 file changed, 47 insertions(+), 1 deletion(-)
diff --git a/include/hw/registerfields.h b/in
On Wed, Feb 9, 2022 at 1:49 AM Yu Li wrote:
>
> Since the hypervisor extension been non experimental and enabled for
> default CPU, the previous command is no longer available and the
> option `x-h=true` or `h=true` is also no longer required.
>
> Signed-off-by: Yu Li
Thanks!
Applied to riscv-t
On Fri, Feb 4, 2022 at 12:32 PM Weiwei Li wrote:
>
> This patchset implements virtual memory related RISC-V extensions: Svnapot
> version 1.0, Svinval vesion 1.0, Svpbmt version 1.0.
>
> Specification:
> https://github.com/riscv/virtual-memory/tree/main/specs
>
> The port is available here:
> htt
On 1/8/22 01:39, Peter Maydell wrote:
(1) The handling of the BaseADDR field for TLB range
invalidates needs updating (there's a TODO to this effect in
tlbi_aa64_range_get_base()).
Side note: in that function, we shift the field by TARGET_PAGE_BITS,
but the docs say that the shift should depend
Hexagon has ~200 instructions that set the saturate bit in USR, these
were broken into groups of similar instructions and one instruction
from each group is tested with at least one input that does not
saturate and at least one input that does saturate.
Signed-off-by: Taylor Simpson
---
tests/tc
From: Michael Lambert
Versions V3 and earlier should treat the "K_const" and "length" values
as unsigned.
Modified circ_test_v3() in tests/tcg/hexagon/circ.c to reproduce the bug
Signed-off-by: Michael Lambert
Signed-off-by: Taylor Simpson
---
target/hexagon/op_helper.c | 6 +++---
tests/tcg
Replace consecutive inline asm blocks with a single one with proper
outputs/inputs/clobbers rather than making assumptions about register
values being carried between separate blocks.
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/preg_alias.c | 46 ++
Add a test that sets USR multiple times in a packet
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/overflow.c | 61 +++-
1 file changed, 60 insertions(+), 1 deletion(-)
diff --git a/tests/tcg/hexagon/overflow.c b/tests/tcg/hexagon/overflow.c
index 196fcf7f3a
On Hexagon, c4 is an alias for predicate registers P3:0. If we assign to
c4 inside a packet with reads from predicate registers, the predicate
reads should get the old values.
Test case added to tests/tcg/hexagon/preg_alias.c
Co-authored-by: Michael Lambert
Signed-off-by: Taylor Simpson
---
t
The arch_sf_recip_common function was calling float32_getexp which
adjusts for denorm, but the we actually need the raw exponent bits.
This function is called from 3 instructions
sfrecipa
sffixupn
sffixupd
Test cases added to tests/tcg/hexagon/fpstuff.c
Signed-off-by: Taylor Simpson
The float??_minnum implementation differs from Hexagon for SNaN,
it returns NaN, but Hexagon returns the other input. So, we add
checks for NaN before calling it.
test cases added in a subsequent patch to more extensively test USR bits
Signed-off-by: Taylor Simpson
---
target/hexagon/op_helper
Tests to confirm floating point instructions are properly
setting exception bits in USR
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/usr.c | 339
1 file changed, 339 insertions(+)
diff --git a/tests/tcg/hexagon/usr.c b/tests/tcg/hexagon/usr.c
inde
VyV operand is only used in the vshuff and vdeal instructions. These
instructions write to both VyV and VxV operands. In the case where
both operands are the same register, we need a separate location for
VyV. We use the existing vtmp field in CPUHexagonState.
Test case added in tests/tcg/hexag
Instead of checking for nan arguments, use float??_unordered_quiet
test cases added in a subsequent patch to more extensively test USR bits
Signed-off-by: Taylor Simpson
---
target/hexagon/op_helper.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/hexagon/op_he
Fix bugs reported from Hexagon users
There is a pattern of issues setting bits in user status register (USR),
so I created new tests dedicated to instructions that might set USR.
Changes in v2
Make the _chop versions of float-to-int conversions use :chop insns in usr.c
Additiona
Fix typo that checked for 32 bit nan instead of 64 bit
Test case added in tests/tcg/hexagon/usr.c
Signed-off-by: Taylor Simpson
---
target/hexagon/op_helper.c | 2 +-
tests/tcg/hexagon/usr.c| 4
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/hexagon/op_helper.c b/
Two tests added to tests/tcg/hexagon/hvx_misc.c
v21.uw = vadd(v11.uw, v10.uw):sat
v25:24.uw = vsub(v17:16.uw, v27:26.uw):sat
Signed-off-by: Taylor Simpson
---
target/hexagon/macros.h | 4 +-
tests/tcg/hexagon/hvx_misc.c | 71 +++-
2 files changed, 72
On Wed, Feb 9, 2022 at 1:49 AM Yu Li wrote:
>
> Since the hypervisor extension been non experimental and enabled for
> default CPU, the previous command is no longer available and the
> option `x-h=true` or `h=true` is also no longer required.
>
> Signed-off-by: Yu Li
Reviewed-by: Alistair Franc
On 2/9/2022 5:14 PM, Like Xu wrote:
Hi Weijiang,
On 23/1/2022 12:11 am, Yang Weijiang wrote:
KVM legacy LBR patches have been merged in kernel 5.12, this patchset
is to expose the feature to guest from the perf capability MSR. Qemu can
add LBR format in cpu option to achieve it, e.g., -cpu ho
On 1/7/22 07:23, Peter Maydell wrote:
On Wed, 8 Dec 2021 at 23:16, Richard Henderson
wrote:
This feature is relatively small, as it applies only to
64k pages and thus requires no additional changes to the
table descriptor walking algorithm, only a change to the
minimum TSZ (which is the invers
> On Feb 2, 2022, at 12:34 AM, Alex Williamson
> wrote:
>
> On Wed, 2 Feb 2022 01:13:22 +
> Jag Raman wrote:
>
>>> On Feb 1, 2022, at 5:47 PM, Alex Williamson
>>> wrote:
>>>
>>> On Tue, 1 Feb 2022 21:24:08 +
>>> Jag Raman wrote:
>>>
> On Feb 1, 2022, at 10:24 AM, Alex Willia
On 2/10/22 10:09, Philippe Mathieu-Daudé wrote:
On 9/2/22 23:50, Richard Henderson wrote:
On 2/10/22 08:54, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/m68k/mcf.h | 3 +--
target/m68k/cpu-qom.h | 2 --
target/m68k/cpu.h | 4 ++--
3 files changed,
Am 30. Januar 2022 23:53:42 MEZ schrieb "Philippe Mathieu-Daudé"
:
>On 14/1/22 14:36, Peter Maydell wrote:
>> On Wed, 12 Jan 2022 at 22:02, Bernhard Beschow wrote:
>>>
>>> Now that piix4_set_irq's opaque parameter references own PIIX4State,
>>> piix4_dev becomes redundant and pci_irq_levels can b
To reduce the inclusion of "hw/core/cpu.h", extract
MMUAccessType to its own "exec/cpu-tlb.h" header.
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/cpu-defs.h | 1 +
include/exec/cpu-tlb.h| 16
include/exec/cpu_ldst.h | 1 +
include/exec/exec-all.h
On Thu, Feb 10, 2022 at 3:20 AM Will Cohen wrote:
>
> On Wed, Feb 9, 2022 at 9:08 AM Christian Schoenebeck
> wrote:
>>
>> On Mittwoch, 9. Februar 2022 14:33:25 CET Akihiko Odaki wrote:
>> > > I like the idea of switching it to __attribute__((weak)). I should note
>> > > that I'm not sure that I
Move user-mode common prototypes from "exec/exec-all.h"
to "user/cpu-common.h".
Signed-off-by: Philippe Mathieu-Daudé
---
bsd-user/qemu.h | 2 --
include/exec/cpu-all.h | 3 +--
include/exec/exec-all.h | 10 --
include/user/cpu-common.h | 36 +
env_cpu() is declared in "exec/cpu-all.h".
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/cpu_loop-common.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/linux-user/cpu_loop-common.h b/linux-user/cpu_loop-common.h
index dc0042e4de..b0fd1ea3b1 100644
--- a/linux-user/cpu_loop-common.h
On 9/2/22 23:50, Richard Henderson wrote:
On 2/10/22 08:54, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/m68k/mcf.h | 3 +--
target/m68k/cpu-qom.h | 2 --
target/m68k/cpu.h | 4 ++--
3 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/in
Move user-mode specific prototypes from "exec/exec-all.h"
to "user/cpu-target.h".
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/user-exec.c| 1 +
bsd-user/elfload.c | 1 +
bsd-user/main.c | 1 +
bsd-user/signal.c| 1 +
include/
preexit_cleanup() is not Linux specific, move it to common-user/.
Signed-off-by: Philippe Mathieu-Daudé
---
{linux-user => common-user}/exit.c | 0
common-user/meson.build| 1 +
linux-user/meson.build | 1 -
3 files changed, 1 insertion(+), 1 deletion(-)
rename {linux-us
common-user/ has been added in commit bbf15aaf7c
("common-user: Move safe-syscall.* from linux-user").
Signed-off-by: Philippe Mathieu-Daudé
---
scripts/coverity-scan/COMPONENTS.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/coverity-scan/COMPONENTS.md
b/scripts/
qemu_plugin_user_exit() is declared in "qemu/plugin.h".
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/exit.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/linux-user/exit.c b/linux-user/exit.c
index fa6ef0b9b4..10989f17f8 100644
--- a/linux-user/exit.c
+++ b/linux-user/exit.c
@@ -17
Avoid spreading the headers in multiple directories,
unify exec/user/ and user/.
Signed-off-by: Philippe Mathieu-Daudé
---
bsd-user/qemu.h | 4 ++--
include/exec/cpu-all.h | 2 +-
include/{exec => }/user/abitypes.h | 0
include/user/safe-syscall.h | 6 ++
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/tcg-accel-ops-icount.c | 1 +
accel/tcg/tcg-accel-ops-mttcg.c | 1 +
accel/tcg/tcg-accel-ops-rr.c | 1 +
accel/tcg/tcg-accel-ops.c| 1 +
4 files changed, 4 insertions(+)
diff --git a/accel/tcg/tcg-accel-ops-icount.c b/accel/tcg/tcg
- Add missing headers
- Merge exec/user/ to user/
- Extract MMUAccessType from QOM "hw/core/cpu.h" to "exec/cpu-tlb.h"
- Extract user-specific declarations to "user/cpu-{common,target}.h"
- Share preexit_cleanup() from Linux with BSD
More to come, but flushing for early feedback.
Based-on: <20220
On 2/10/22 08:54, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/m68k/mcf.h | 3 +--
target/m68k/cpu-qom.h | 2 --
target/m68k/cpu.h | 4 ++--
3 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/include/hw/m68k/mcf.h b/include/hw/m68k/mcf.h
On 2/10/22 09:33, Philippe Mathieu-Daudé wrote:
-struct ArchCPU {
+typedef struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
@@ -188,7 +188,7 @@ struct ArchCPU {
uint32_t reset_addr;
uint32_t exception_addr;
uint32_t fast_tlb_miss_addr;
-};
+
On 2/10/22 08:54, Philippe Mathieu-Daudé wrote:
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 25c67e43a2..4dce40a360 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -143,7 +143,7 @@ typedef struct HexagonCPUClass {
DeviceReset parent_reset;
} HexagonCPUCla
On 9/2/22 22:54, Philippe Mathieu-Daudé wrote:
ArchCPU is our interface with target-specific code. Use it as
a forward-declared opaque pointer (abstract type), having its
structure defined by each target.
Signed-off-by: Philippe Mathieu-Daudé
---
include/qemu/typedefs.h | 1 +
target/al
While CPUState is our interface with generic code, CPUArchState is
our interface with target-specific code. Use CPUArchState as an
abstract type, defined by each target.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/poison.h | 2 --
include/hw/core/cpu.
On 2/10/22 08:54, Philippe Mathieu-Daudé wrote:
hwaddr type is defined in "exec/hwaddr.h".
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/m68k/mcf.h | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Richard Henderson
r~
On 2/10/22 08:54, Philippe Mathieu-Daudé wrote:
TriCore boards certainly don't need the ARM loader API :)
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/tricore/triboard.h | 1 -
1 file changed, 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 9/2/22 20:15, Bernhard Beschow wrote:
Other ISA devices such as serial-isa use the properties in their
build_aml functions. fdc-isa not using them is probably an oversight.
Signed-off-by: Bernhard Beschow
---
hw/block/fdc-isa.c | 11 +++
1 file changed, 7 insertions(+), 4 deletion
excp_helper.c requires "exec/exec-all.h" for tlb_set_page_with_attrs()
and misc_helper.c for tlb_flush().
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/tcg/sysemu/excp_helper.c | 1 +
target/i386/tcg/sysemu/misc_helper.c | 1 +
2 files changed, 2 insertion
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/sh4/sh.h | 3 +--
target/sh4/cpu-qom.h | 2 --
target/sh4/cpu.h | 4 ++--
3 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/include/hw/sh4/sh.h b/include/hw/sh4/sh.h
index ec716cdd45..a4245399d5 100644
--- a/include/hw/sh4/sh.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/mips/cpudevs.h | 6 ++
target/mips/cpu-qom.h | 2 --
target/mips/cpu.h | 4 ++--
3 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/include/hw/mips/cpudevs.h b/include/hw/mips/cpudevs.h
index f7c9728fa9..6065932b0e 1
The only accelerator allowed to use zero as default value is TCG.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index aa9e636800..16523a78d9 100644
--- a/target
On 2/9/22 22:22, Alex Bennée wrote:
linux-user wants to trap all signals in case they are related to the
guest. This however results in less than helpful core dumps when the
error is internal to QEMU. We can detect when an assert failure is in
progress by examining __glib_assert_msg and fall thro
These target-specific files use the target-specific CPU state
but lack to include "cpu.h"; i.e.:
../target/riscv/pmp.h:61:23: error: unknown type name 'CPURISCVState'
void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
^
../target/nios2/mmu.h:43:18:
cpu.c requires "exec/exec-all.h" to call tlb_flush() and
"qemu/accel.h" to call accel_cpu_realizefn().
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/cpu.c b/cpu.c
index 97d42b6b2a..6b4aa53775 100644
--- a/cpu
ArchCPU is our interface with target-specific code. Use it as
a forward-declared opaque pointer (abstract type), having its
structure defined by each target.
Signed-off-by: Philippe Mathieu-Daudé
---
include/qemu/typedefs.h | 1 +
target/alpha/cpu-qom.h | 4 +++-
target/alpha/cpu.h
The CPU / CPU state are forward declared.
$ git grep -E 'struct [A-Za-z]+CPU\ \*'
target/arm/hvf_arm.h:16:void hvf_arm_set_cpu_features_from_host(struct ARMCPU
*cpu);
target/openrisc/cpu.h:234:int (*cpu_openrisc_map_address_code)(struct
OpenRISCCPU *cpu,
target/openrisc/cpu.h:238:
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/sparc/sparc64.h | 4 +---
target/sparc/cpu-qom.h | 2 --
target/sparc/cpu.h | 4 ++--
3 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/include/hw/sparc/sparc64.h b/include/hw/sparc/sparc64.h
index 4ced36fb5a..605ae4448
hwaddr type is defined in "exec/hwaddr.h".
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/m68k/mcf.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/hw/m68k/mcf.h b/include/hw/m68k/mcf.h
index decf17ce42..8cbd587bbf 100644
--- a/include/hw/m68k/mcf.h
+++ b/include/hw/m68k/mcf.h
TriCore boards certainly don't need the ARM loader API :)
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/tricore/triboard.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/hw/tricore/triboard.h b/include/hw/tricore/triboard.h
index f3844be447..094c8bd563 100644
--- a/include/hw/
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/m68k/mcf.h | 3 +--
target/m68k/cpu-qom.h | 2 --
target/m68k/cpu.h | 4 ++--
3 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/include/hw/m68k/mcf.h b/include/hw/m68k/mcf.h
index 8cbd587bbf..e84fcfb4ca 100644
--- a/include/hw/
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/cpu_ldst.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index a878fd0105..5c66de 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@
When configuring QEMU with --disable-system, meson keeps showing
libfdt as "auto". Mark it as disabled instead.
Acked-by: Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé
---
meson.build | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index 57
Hi Richard,
Kind of respin of the "exec: Move translation declarations to
'translate-all.h'" series, but without modifying translate-all.h :)
(same same but different).
Last patches are RFC, not sure worthwhile (at least for now).
Based-on: <20220207082756.82600-1-f4...@amsat.org>
"exec: Remove
On 9/2/22 00:00, Richard Henderson wrote:
On 2/9/22 02:22, Philippe Mathieu-Daudé wrote:
Translation declarations are only useful to TCG accelerator.
Signed-off-by: Philippe Mathieu-Daudé
Ug.
So, like, what's you vision of exec-all.h vs translate-all.h? Certainly
there's not much in transl
On 8/2/22 23:40, Richard Henderson wrote:
On 2/9/22 02:22, Philippe Mathieu-Daudé wrote:
While CPUState is our interface with generic code, CPUArchState is
our interface with target-specific code. Use CPUArchState as an
abstract type, defined by each target.
Signed-off-by: Philippe Mathieu-Daud
On Wed, 9 Feb 2022 at 16:57, Dr. David Alan Gilbert (git)
wrote:
>
> From: "Dr. David Alan Gilbert"
>
> There's a nice new Rust implementation out there; recommend people
> do new work on that.
>
> Signed-off-by: Dr. David Alan Gilbert
> ---
> docs/about/deprecated.rst | 14 ++
> 1
On Wed, 09 Feb 2022 18:24:56 +0100
Cornelia Huck wrote:
> On Wed, Feb 09 2022, Halil Pasic wrote:
>
> > Unlike most virtio features ACCESS_PLATFORM is considered mandatory by
> > QEMU, i.e. the driver must accept it if offered by the device. The
> > virtio specification says that the driver SHO
Other ISA devices such as serial-isa use the properties in their
build_aml functions. fdc-isa not using them is probably an oversight.
Signed-off-by: Bernhard Beschow
---
hw/block/fdc-isa.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/hw/block/fdc-isa.c b/hw/bl
On Wed, Feb 09, 2022 at 04:50:40PM +, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> There's a nice new Rust implementation out there; recommend people
> do new work on that.
>
> Signed-off-by: Dr. David Alan Gilbert
Acked-by: Vivek Goyal
Vivek
> ---
> docs/ab
On Fri, Feb 4, 2022 at 5:18 PM John Snow wrote:
>
> Long story short: Python 3.7/3.8 on Fedora with setuptools v60.0.0+
> together create a bug that ultimately causes pylint to fail. See the
> first commit message for more detail.
>
> I sent out a hotfix two weeks ago to fix this behavior on our C
On Wed, Feb 09, 2022 at 06:18:01PM +, Jonathan Cameron wrote:
> On Mon, 24 Jan 2022 17:16:46 +
> Jonathan Cameron wrote:
>
> > From: Ben Widawsky
> >
> > Following patches will add a new ACPI table, the
> > CXL Early Discovery Table (CEDT).
> >
> > Signed-off-by: Ben Widawsky
> > Sign
On Wed, Feb 9, 2022 at 10:29 AM Eduardo Habkost wrote:
>
> On Mon, 7 Feb 2022 at 19:05, John Snow wrote:
> >
> > Eduardo Habkost has left Red Hat and has other daily responsibilities to
> > attend to. In order to stop spamming him on every series, remove him as
> > "Reviewer" for the python/ libr
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